TWI517332B - Semiconductor stacking structure and packing and testing method thereof - Google Patents

Description

Semiconductor stack structure and its sealing and measuring method

The present invention relates to a semiconductor stacked structure and a method for packaging and testing, and more particularly to a semiconductor stacked structure applied to a three-dimensional integrated circuit board and a method for sealing the same.

In order to be small and multi-functional, the size of the internal components must be smaller and smaller, that is, the density of the components is increased. In contrast, the wire pitch in the wafer needs to be continuously reduced. The integrated circuit has been developed for half a century, and the process from the micron level to the 20 nm process can be said to have reached the peak. However, the limitation of the two-dimensional structure still causes difficulty in the process. For example, it is quite difficult to reduce the components to below 20 nm, and the quality of the wire or the heat dissipation effect are affected. Therefore, in order to get rid of the size limitation, the three-dimensional integrated circuit becomes the most forward-looking technology, because it is vertical electrical conduction, eliminating the need for a traditional two-dimensional circuit board, taking a computer as an example, a three-dimensional integrated circuit There is no longer a need for a motherboard or internal wire connection, which can reduce the size and weight of the package. In addition, it has parallel processing capability, eliminating the need to complete all the programs through the central processor and speed up the operation.

The traditional three-dimensional packaging method uses a Through-Silicon Via (TSV) and a Micro Bumps to form a vertical internal electrical connection and package between the three-dimensional integrated circuit boards. The opposite position. In addition, maintaining product yield is also very important. The semi-finished products of the three-dimensional integrated circuit still need to be electrically tested to ensure that the quality is flawless and can be further assembled. The wafer of the conventional two-dimensional integrated circuit uses a film or a probe for electrical testing in the horizontal direction. However, for a three-dimensional integrated circuit, it is necessary to vertically conduct each layer of the circuit for electrical testing, so the conventional method cannot be applied. At present, the technology has a dielectric layer with micro bumps (Micro bumps) to contact three-dimensional integrated electrical contacts and electrical detectors. However, because of the need for precise alignment, a slight offset may cause unsatisfactory signal measurement, and the electrical contact between the microbump and the contact is less intimate, which may affect the measurement result. It may also be due to stress concentration during contact. Causes damage to components. In addition, because a single piece cannot be detected separately The electrical properties of the integrated circuit board, if the package is completed, it is found that there is a problem with the single-chip integrated circuit board, and it is necessary to replace the package of the entire three-dimensional integrated circuit board, which is quite wasteful.

In summary, how to develop a sealed and measured structure of a three-dimensional integrated circuit with good detection efficiency and good electrical contact is an urgent task.

The invention provides a semiconductor stack structure and a method for sealing the same. By the elastic structure of the elastic bridge, it can withstand the deformation of the press, forming a better electrical contact, making the detection result more accurate, and avoiding component damage caused by stress concentration; it can also be directly used for soldering and packaging, avoiding semiconductor The problem of offset alignment of the stack structure up and down. In addition, if the semiconductor stack structure is an interleaved stack of the interposer substrate and the integrated circuit board, the electrical properties of each integrated circuit board can be individually checked, thus avoiding the fact that after the entire package, if the monolithic integrated circuit board is found The problem is that the entire semiconductor stack structure needs to be forced to replace the cost waste.

A semiconductor stack structure according to an embodiment of the present invention is used in a semiconductor package tester. The semiconductor stacked structure comprises a plurality of semiconductor conductive plate structures stacked one on top of the other, wherein the semiconductor conductive plate structure comprises a substrate and a plurality of elastic bridges. The substrate has a first surface and a second surface, wherein the first surface and the second surface have a plurality of electrical contacts. a plurality of elastic bridges are disposed on the substrate, respectively having a bridge base, a bridge portion and a solder region on the bridge portion; the bridge base is located above the electrical contacts on the substrate, and the bridge portion and the substrate have a The gap is to withstand the deformation of the press. The plurality of elastic bridges of the semiconductor conductive plate structure located above form a vertical electrical contact with the plurality of elastic bridges of the semiconductor conductive plate structure located below.

A semiconductor package testing method according to an embodiment of the invention comprises the following steps. First, a plurality of semiconductor conductive plate structures are provided, wherein the semiconductor conductive plate structure comprises a substrate and a plurality of elastic bridge structures. The substrate has a first surface and a second surface, wherein the first surface and the second surface have a plurality of electrical contacts. a plurality of elastic bridges are disposed on the substrate, respectively having a bridge base, a bridge portion and a solder region, wherein the bridge base is located on the substrate Above the contact, the solder area is above the bridge and there is a gap between the bridge and the substrate to withstand the press deformation. Next, a plurality of semiconductor conductive plate structures are stacked vertically to form a semiconductor stacked structure, and a semiconductor electrical tester is vertically electrically detected using a semiconductor package tester, wherein a plurality of elastic bridges of the semiconductor conductive plate structure located above The plurality of elastic bridges of the semiconductor conductive plate structure underneath form a vertical electrical contact; the substrate of the semiconductor conductive plate structure located above is an interposer substrate, and the interposer substrate comprises a plurality of through holes extending through the interposer substrate a surface and a second surface, wherein each of the through holes receives a conductive member, and both ends of the conductive member protrude from the first surface and the second surface of the interposer and respectively form a plurality of electrical contacts thereon; The substrate of the semiconductor conductive plate structure below is an integrated circuit board. Finally, through vertical electrical detection, the integrated circuit board of the semiconductor stacked structure and the interposer substrate are soldered through the solder region to complete the package.

A semiconductor package test method according to another embodiment of the present invention includes the following steps. First, a plurality of semiconductor conductive plate structures are provided, wherein the semiconductor conductive plate structure comprises a substrate and a plurality of elastic bridges. The substrate has a first surface and a second surface, wherein the first surface and the second surface have a plurality of electrical contacts. A plurality of elastic bridges are disposed on the substrate, respectively having a bridge base, a bridge portion and a solder region, wherein the bridge base is located above the electrical contacts on the substrate, the solder regions are located above the bridge portion, and the bridge portion and the substrate There is a gap between them to withstand the pressing deformation. Finally, a plurality of semiconductor conductive plate structures are vertically stacked to form a semiconductor stacked structure, and a vertical electrical detection of the semiconductor stacked structure is performed using a semiconductor package measuring machine, wherein a plurality of elastic bridges of the semiconductor conductive plate structure located above are located The plurality of elastic bridges of the lower semiconductor conductive plate structure form a vertical electrical contact; and the substrate of the conductive plate structure located above is an integrated circuit board, and the substrate of the conductive plate structure located below is another integrated circuit board. Finally, through vertical electrical detection, the integrated circuit board of the semiconductor stacked structure is soldered through the solder region to complete the package.

The purpose, technical contents, features, and effects achieved by the present invention will become more apparent from the detailed description of the appended claims.

Please refer to FIG. 1. FIG. 1 is a schematic structural view of a semiconductor conductive plate according to an embodiment of the present invention. The semiconductor conductive plate structure 100 includes a substrate 110 and a plurality of elastic bridges 120. The substrate 110 has a first surface 111 and a second surface 112. The first surface 111 and the second surface 112 have a plurality of electrical contacts 130. The plurality of elastic bridges 120 are disposed on the substrate 110, and have a bridge base portion 121 and a bridge portion 122 respectively. The bridge base portion 121 is located above the electrical contacts 130 on the substrate 110, and between the bridge portion 122 and the substrate 110. There is a gap G to withstand pressing deformation. Since the elastic bridge 120 needs to have good electrical conductivity and elasticity, it can be composed of a conductive elastic film such as indium tin compound (ITO), zinc oxide or other metal thin film or the like.

Preferably, as shown in FIG. 1, the semiconductor conductive plate structure 100 further includes a solder region M located above the bridge portion 122. As such, the elastic bridge 120 can be used for soldering to complete the package in addition to electrical detection. The form of the solder region M is not particularly limited, and may be a solder ball or a thin solder layer on the elastic bridge 120.

Referring to FIG. 1 again, in an embodiment, the elastic bridge 120 can be disposed on different forms of the substrate 110, such as an interposer substrate or an integrated circuit board. When the substrate 110 is an integrated circuit board, the electrical contacts 130 can be Thorough-Silicon Via (TSV) terminals or electrodes on the integrated circuit board.

Please refer to FIG. 2. FIG. 2 is a schematic structural view of a semiconductor conductive plate according to another embodiment of the present invention. As shown in the figure, when the substrate 210 of the semiconductor conductive plate structure 200 is an interposer substrate, the interposer substrate may include a plurality of through holes 240 penetrating through the first surface 211 and the second surface 212 of the interposer substrate, wherein each through hole The conductive member 250 is disposed on the first surface 211 and the second surface 212 of the interposer substrate, and the electrical contacts 230 are respectively formed thereon. The bridge base 221 of the plurality of elastic bridges 220 is located on the electrical contacts 230 (where the gap between the bridge portion 222 and the substrate 210 is G'). Preferably, as shown in Fig. 2, a solder region M' is further disposed over the bridge portion 222.

The above semiconductor conductive plate has a monolithic structure. If a plurality of semiconductor conductive plate structures are stacked on top of each other to electrically contact the elastic bridges of the upper and lower layers, a semiconductor stacked structure is formed and can be used in a semiconductor package tester. Preferably, the upper and lower elastic bridges are Electrical contact is formed by cross-compression, for example, at ninety degrees, so that even if the alignment between the upper and lower elastic bridges is slightly offset, electrical contact can be formed, and the problem of inaccurate alignment is avoided.

According to an embodiment of the present invention, the semiconductor stacked structure 300, as shown in FIG. 3, employs a stacking manner of ninety-degree cross-over piezoelectric contacts of elastic bridges of upper and lower semiconductor conductive plates, wherein any of the semiconductor conductive plate structures 100, As shown in the embodiment of FIG. 1, a substrate 110 and a plurality of elastic bridges 120 are included. The substrate 110 has a first surface 111 and a second surface 112. The first surface 111 and the second surface 112 have a plurality of electrical contacts 130. The plurality of elastic bridges 120 are disposed on the substrate 110, and have a bridge base portion 121, a bridge portion 122, and a solder portion M on the bridge portion 122. The bridge base portion 121 is located above the electrical contacts 130 on the substrate 110. And a gap G is formed between the bridge portion 122 and the substrate 110 to withstand pressing deformation. Referring to FIG. 3 again, in the semiconductor stacked structure 300, the elastic bridge 120 of the semiconductor conductive plate structure 100 located above forms a nine-degree cross-voltage with the elastic bridge 120 of the other semiconductor conductive plate structure 100 located below. Sexual contact. It should be noted that the present embodiment is only used to facilitate the description of the relative positional relationship of the internal components in the semiconductor stacked structure of the present invention, and is not intended to limit the positional relationship between the upper and lower sides. In addition, the number of stacked layers of the semiconductor conductive plate 100 in the semiconductor stacked structure 300 is not limited herein, and may be adjusted from L1, L2 to Ln layers (where n is a positive integer), depending on user requirements.

In the present invention, the design of the elastic bridge utilizes its elasticity to form a preferred electrical contact. According to Hooke's law and Newton's third law, when the elastic bridge is subjected to the compression deformation of the foreign object, within the elastic limit, a reverse elastic stress is applied to the foreign object, thereby forming a relatively close contact. Taking the elastic bridges 120 and 220 of the present invention and the other elastic bridges 120 and 220 as an example (as shown in FIGS. 1 and 2), if they are pressed up and down, they can form an electrical contact more closely. Moreover, because of the elastic structure of the elastic bridge, it does not damage the structure of each other during electrical contact, and avoids the damage of stress concentration. In addition, preferably, in the semiconductor stack structure, the upper and lower elastic bridges 120 may be cross-compressed (ie, have an angle overlooking the upper and lower layers of the elastic bridge) to form an electrical contact, for example, at ninety degrees, so that even the upper and lower elastic The alignment between the bridges is slightly offset and electrical contact can still be formed.

It will be appreciated that the substrates in the semiconductor stack structure may be the same or different. For example, the substrate may be an upper and lower stacked structure of the interposer substrate and the integrated circuit board, or the substrate may be a stacked structure of the integrated circuit board. Similarly, the elastic bridge can be disposed on different forms of the substrate, such as an interposer substrate or an integrated circuit board. In one embodiment, referring again to FIG. 3, the substrate 110 of the semiconductor conductive plate structure 100 located above and below the semiconductor stacked structure 300 is an integrated circuit board. Other technical contents regarding the integrated circuit board are as described above, and it goes without saying. It should be noted that the present embodiment is only used to facilitate the description of the relative positional relationship of the internal components in the semiconductor stacked structure of the present invention, and is not intended to limit the positional relationship between the upper and lower sides. In addition, there is no limitation on the number of stacked layers of the semiconductor conductive plates in the semiconductor stacked structure, and the layers from L1, L2 to Ln (where n is a positive integer) are all adjusted according to user requirements.

In another embodiment, as shown in FIG. 4, the substrate 210 of the semiconductor conductive plate structure 200 located above the semiconductor stacked structure 400 is an interposer substrate, and the substrate 110 of the lower semiconductor conductive plate structure 100 is an integrated circuit. The plate, the elastic bridge 220 on the upper interposer substrate, forms a ninety-degree cross-piezoelectric contact with the elastic bridge 120 on the underlying integrated circuit board. Regarding the structure of the upper interposer substrate, referring to FIG. 2, when the substrate 210 is an interposer substrate, it includes a plurality of through holes 240 penetrating through the first surface 211 and the second surface 212 of the interposer substrate, wherein each via hole The conductive member 250 is disposed on the first surface 211 and the second surface 212 of the interposer substrate, and a plurality of electrical contacts 230 are formed thereon, and the plurality of elastic bridges 220 are respectively formed. The bridge base 221 is located on the electrical contact 230 (where the gap between the bridge portion 222 and the substrate 210 is G', and the solder region on the bridge portion 222 is M'). The substrate 110 of the semiconductor conductive plate structure 100 located below is an integrated circuit board. Other technical contents regarding the interposer substrate and the integrated circuit board are as described above, and it goes without saying. In short, the semiconductor stacked structure 400 of the present embodiment is formed by interleaving an integrated circuit board and an interposer substrate. It should be noted that the present embodiment is only used to facilitate the description of the relative positional relationship of the internal components in the semiconductor stacked structure of the present invention, and is not intended to limit the positional relationship between the upper and lower sides. In addition, the number of stacked layers of the semiconductor conductive plates 100 and 200 in the semiconductor stacked structure 400 is not limited here, and can be adjusted from L1', L2' to Ln' layers (where n is a positive integer), depending on the user's needs.

The present invention also provides a semiconductor package test method. In an embodiment, the following steps are included. Please refer to FIG. 5A for the flow chart of the steps. First, a plurality of semiconductor conductive plate structures (S1) are provided. As for the semiconductor conductive plate structure 100, as shown in FIG. 1, a substrate 100 and a plurality of elastic bridges 120 are included. The substrate 100 has a first surface 111 and a second surface 112 , wherein the first surface 111 and the second surface 112 have a plurality of electrical contacts 130 . The elastic bridges 120 are disposed on the substrate 110 and have a bridge base portion 121, a bridge portion 122 and a solder region M. The bridge base portion 121 is located above the electrical contacts 130 on the substrate 110, and the solder region M is located at the bridge portion 122. Above, and there is a gap G between the bridge portion 122 and the substrate 110 to withstand pressing deformation. Next, as shown in FIG. 3, a plurality of semiconductor conductive plate structures 100 are vertically stacked to form a semiconductor stacked structure 300, and a vertical electrical detection (S2) of the semiconductor stacked structure 300 is performed using a semiconductor package measuring machine, wherein the upper portion is located above The elastic bridge 120 of the semiconductor conductive plate structure 100 is in perpendicular electrical contact with the elastic bridge 120 of the other semiconductor conductive plate structure 100 located below; and the substrate 110 of the semiconductor conductive plate structure 100 located above is an integrated circuit board The substrate 110 of the semiconductor conductive plate structure 100 located below is another integrated circuit board (as shown in FIG. 3). It should be noted that the present embodiment is only used to facilitate the description of the relative positional relationship of the internal components in the semiconductor stacked structure of the present invention, and is not intended to limit the positional relationship between the upper and lower sides. In addition, there is no limitation on the number of stacked layers of the semiconductor conductive plate structure in the semiconductor stacked structure, which can be adjusted according to user requirements. Finally, after the vertical electrical detection, a plurality of integrated circuit boards of the semiconductor stacked structure 300 are solder bonded through the solder region M (as shown in FIG. 1) to complete the package (S3). In short, in the embodiment, the semiconductor stack structure is formed by stacking integrated circuit boards and used for electrical detection and packaging of the entire set. Preferably, referring to FIG. 5B, in step S2, if the electrical detection result is normal (Y), the next step S3 is performed, and the bonding is performed to complete the packaging. If the result of the electrical detection is abnormal (N), the process proceeds to another step S2', the semiconductor conductive plate structure 100 (or the semiconductor stacked structure 300 composed thereof) is replaced, and then electrical detection is performed, if the electrical detection is performed. The result is normal (Y) before the next step S3 is performed, solder bonding to complete the package. If the result of the electrical detection is abnormal (N), the semiconductor conductive plate structure 100 (or the semiconductor stacked structure 300 composed thereof) is replaced again and electrically tested until the electrical detection result is normal (Y). Going to step S3, the solder joint is completed to complete the package.

In another embodiment, the steps S1, S2 and most of the technical contents of the semiconductor package test method are as described in the previous embodiment and FIG. 5A, and it is not to be understood here. The difference is that the semiconductor stack structure 400 is used in the embodiment, that is, the substrate 210 of the conductive plate structure 200 located above is an interposer substrate, and the substrate 110 of the conductive plate structure 100 located below is an integrated circuit board. . It should be noted that this embodiment is only used to facilitate the description of the relative positional relationship of the internal components in the semiconductor stacked structure of the present invention, and is not intended to limit the position of the upper and lower sides. In addition, there is no limitation on the number of stacked layers of the semiconductor conductive plate structure in the semiconductor stacked structure, which can be adjusted according to user requirements. Finally, after the vertical electrical detection, the plurality of interposer substrates of the semiconductor stacked structure and the plurality of integrated circuit boards are soldered through the solder regions M' and M (as shown in FIG. 1 and FIG. 2) to complete the package (S3). ). In short, in the embodiment, the semiconductor stack structure is an interleaved stack of integrated circuit boards and interposer substrates for electrical detection and packaging. Preferably, please refer to FIG. 5B again. In step S2, if the electrical detection result is normal (Y), the next step S3 is performed, and the bonding is performed to complete the packaging. If the electrical detection result is abnormal (N), it will proceed to another step S2', replace the semiconductor conductive plate structure 100, and then perform electrical detection. If the electrical detection result is normal (Y), the next step will be performed. In a step S3, solder bonding is performed to complete the package. If the electrical detection result is abnormal (N), the semiconductor conductive plate structure 100 is replaced again and electrically tested until the electrical detection result is normal (Y), then the process proceeds to step S3, and the solder joint is completed to complete the package. The advantage is that each integrated circuit board can be separately detected by interposing the integrated circuit board between the interposer substrates. If the detection result shows that one of the defects is defective, it can be directly replaced into a good product and then packaged. This avoids the cost of the entire semiconductor stack structure being forced to be replaced if the single-chip integrated circuit board is found to be problematic after all the packages are packaged.

In addition, the semiconductor conductive plate structure can be used for electrical measurement and packaging of the line spacing, in addition to the electrical measurement and packaging of the line spacing. Please refer to FIG. 6. FIG. 6 is a schematic structural diagram of a semiconductor conductive plate according to another embodiment of the present invention. As shown in the figure, the substrate 210 ′ of the semiconductor conductive plate 200 ′ is taken as an example. The first surface 211 ′ of the substrate 210 ′ and the second surface 212 ′ are not perpendicular to each other. Instead, it is offset by a distance, so that the effect of span measurement and packaging can be achieved by stacking up and down.

Regarding the manner of detection, in an embodiment, as shown in FIG. 7, the semiconductor stacked structure 300 or 400 is inserted into an accommodating space 501 of a semiconductor packager 500, wherein the semiconductor stacked structure 300 The bridge portion of the plurality of elastic bridges in 400 or 400 is pressed and deformed by the bridge portion of the elastic bridge of the other semiconductor stacked structure and forms an electrical contact. The semiconductor package testing machine 500 determines whether the electrical properties of the semiconductor conductive plate structure and the semiconductor stacked structure 300 or 400 are normal by reading signals passing through the semiconductor stacked structure 300 or 400.

In summary, the present invention provides a semiconductor conductive plate structure, a stacked structure, and a method for sealing and testing the same, and the elastic structure of the elastic bridge can form a better electrical contact, thereby making the detection result more accurate; and can be directly used for soldering and packaging. To avoid the problem of up and down alignment offset. In addition, if the semiconductor stack structure is an interleaved stack of the interposer substrate and the integrated circuit board, the electrical properties of each integrated circuit board can be individually checked, thus avoiding the fact that after the entire package, if the monolithic integrated circuit board is found The problem is that the entire semiconductor stack structure needs to be forced to replace the cost waste.

The embodiments described above are only intended to illustrate the technical idea and the features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to implement the present invention. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention.

100, 200, 200'‧‧‧ semiconductor conductive plate structure

110, 210, 210'‧‧‧ substrates

111, 211, 211'‧‧‧ first surface

112, 212, 212'‧‧‧ second surface

120, 220, 220’ ‧ ‧ elastic bridge

121, 221, 221' ‧ ‧ base of the bridge

122, 222, 222’‧‧‧ Bridge Department

130, 230, 230'‧‧‧ electrical contacts

240, 240’‧‧‧through holes

250, 250’‧‧‧Connecting parts

300, 400‧‧‧ semiconductor stack structure

500‧‧‧Semiconductor packaging machine

501‧‧‧ accommodating space

G, G’, G” ‧ ‧ gap

L1, L1', L2, L2', Ln, Ln'‧‧‧ stacked layers

M, M', M"‧‧‧ solder zone

S1~S3, S2’‧‧‧ steps

1 is a schematic structural view of a semiconductor conductive plate according to an embodiment of the present invention.

2 is a schematic structural view of a semiconductor conductive plate according to another embodiment of the present invention.

FIG. 3 is a schematic diagram of a semiconductor stack structure according to an embodiment of the invention.

4 is a schematic view showing a structure of a semiconductor stack according to another embodiment of the present invention.

5A and 5B are respectively a flow chart showing the steps of a semiconductor detecting method according to an embodiment of the present invention.

FIG. 6 is a schematic structural view of a semiconductor conductive plate according to another embodiment of the present invention.

FIG. 7 is a schematic diagram of the operation of a semiconductor packaging and testing machine according to an embodiment of the invention.

100‧‧‧Semiconductor conductive plate structure

110‧‧‧Substrate

120‧‧‧Flexible Bridge

300‧‧‧Semiconductor stack structure

L1 L2, Ln‧‧‧ stacking layers

Claims (5)

A semiconductor stack structure for use in a semiconductor package tester, the semiconductor stack structure comprising a plurality of semiconductor conductive plate structures stacked on top of each other, wherein the semiconductor conductive plate structure comprises: a substrate having a first surface and a a second surface, wherein the first surface and the second surface have a plurality of electrical contacts; and a plurality of elastic bridges disposed on the substrate, each having a bridge base and a bridge portion and a solder region located on the bridge Above the portion, wherein the bridge base is located above the electrical contacts on the substrate, and a gap is formed between the bridge portion and the substrate to receive the press deformation, and the semiconductor conductive plate structure located above The elastic bridge is in perpendicular electrical contact with the resilient bridges of the semiconductor conductive plate structure located below. The semiconductor stack structure of claim 1, wherein the substrate of the semiconductor conductive plate structure located above is an interposer substrate, and the interposer substrate comprises a plurality of through holes extending through the interposer substrate. a surface and the second surface, wherein each of the through holes receives a conductive member, and the two ends of the conductive member protrude from the first surface and the second surface of the interposer and respectively form the conductive layer The electrical contact; and the substrate of the semiconductor conductive plate structure located below is an integrated circuit board. The semiconductor stack structure of claim 1, wherein the substrate of the conductive plate structure located above is an integrated circuit board, and the substrate of the conductive plate structure located below is another integrated circuit board. A semiconductor package test method comprising the steps of: providing a plurality of semiconductor conductive plate structures, wherein the semiconductor conductive plate structure comprises: a substrate having a first surface and a second surface, wherein the first surface and the second The surface has a plurality of electrical contacts; and a plurality of elastic bridges disposed on the substrate, each having a bridge base, a bridge portion, and a solder region, wherein the bridge base is located on the substrate Above the soldering portion is located above the bridge portion, and a gap is formed between the bridge portion and the substrate to withstand pressing deformation; Vertically stacking the semiconductor conductive plate structures to form a semiconductor stacked structure, and performing vertical electrical detection on the semiconductor stacked structure using a semiconductor package tester, wherein the elastic bridges of the semiconductor conductive plate structure located above The elastic bridges of the semiconductor conductive plate structure located below form a vertical electrical contact; the substrate of the semiconductor conductive plate structure located above is an interposer substrate, and the interposer substrate comprises a plurality of through holes extending through the The first surface of the interposer substrate and the second surface, wherein each of the through holes receives a conductive member, and both ends of the conductive member protrude from the first surface and the second surface of the interposer Forming the electrical contacts thereon; and the substrate of the semiconductor conductive plate structure located below is an integrated circuit board; and after the vertical electrical detection, the integrated structures of the semiconductor stacked structures The circuit board and the interposer substrate are solder bonded through the solder region to complete the package. A semiconductor package test method comprising the steps of: providing a plurality of semiconductor conductive plate structures, wherein the semiconductor conductive plate structure comprises: a substrate having a first surface and a second surface, wherein the first surface and the second The surface has a plurality of electrical contacts; and a plurality of elastic bridges disposed on the substrate, each having a bridge base, a bridge portion, and a solder region, wherein the bridge base is located on the substrate Above, the solder region is located above the bridge portion, and a gap is formed between the bridge portion and the substrate to withstand pressing deformation; the semiconductor conductive plate structures are vertically stacked to form a semiconductor stacked structure, and a semiconductor package is used The measuring machine performs vertical electrical detection on the semiconductor stack structure, wherein the elastic bridges of the semiconductor conductive plate structure located above form a vertical electrical contact with the elastic bridges of the semiconductor conductive plate structure located below; The substrate of the conductive plate structure located above is an integrated circuit board, and the substrate of the conductive plate structure located below is An integrated circuit board; and a rear vertical through electrical testing, some of the plurality of the integrated circuit boards are stacked configuration of the semiconductor region through the solder bonding of the solder to complete the package.