TWI517175B - Sense amplifier circuit of memorys and calibration method thereof - Google Patents

Description

Memory sense amplifier circuit and correction method thereof

The present invention relates to a sensing circuit for a storage device, and more particularly to a sensing amplifier circuit for a memory and a method of correcting the same.

With the development of process technology, the circuit area and operating voltage in electronic devices are continuously reduced and decreased. Among them, memory is one of the main components of power consumption in electronic devices due to the large circuit and frequent access factors. Therefore, how to reduce the power consumption of the memory and meet the requirements of low working voltage has become one of the problems that the R&D personnel are currently to solve.

Generally, the memory is composed of a plurality of memory cells, a precharge path, a write circuit, a row and column decoder, and a sense amplifier, wherein the sense amplifier can be used to sense when performing a read operation. The content of the memory cell is read, but when the operating voltage is getting lower and lower with the development of the process technology, the input signal on the bit line will become smaller and smaller, so the sensing range of the sense amplifier becomes the memory performance. One of the factors. However, because of factors such as process, the characteristics of the transistor switch in the sense amplifier are slightly different, that is, mismatch, and this problem may affect the sensing range or sensing result of the sense amplifier. Therefore, it is often necessary to pass the compensation circuit to improve the impact of the mismatch problem.

In the current compensation circuit, some designs are implemented by circuits such as digital to analog converters, but this type of compensation circuit usually requires a complicated control loop, which has relatively high circuit construction cost, and another One design is implemented by using a capacitor element and a switch, etc., but this type of compensation circuit is too sensitive and susceptible to noise interference and misjudgment.

The invention provides a memory sense amplifier circuit and a calibration method thereof, which are respectively coupled with a plurality of transistor switches on both sides of an NMOS type transistor switch in a sense amplifier circuit to correct the sense of the sense amplifier circuit. Measuring range.

Therefore, the sense amplifier circuit of the memory of the present invention includes a sense amplifier unit, a first switch unit, and a second switch unit. The sense amplifier unit is composed of a plurality of transistor switches. The sense amplifier unit has a first connection end, a second connection end, a third connection end and a fourth connection end. The first switch unit is coupled in parallel to the first connection end and the second connection end of the sense amplifier unit. The second switch unit is coupled in parallel to the third connection end and the fourth connection end of the sense amplifier unit, wherein the first switch unit and the second switch unit are respectively coupled by a plurality of transistor switches coupled in parallel with each other, and according to each parallel connection Whether the coupled transistor switch is turned on or off, thereby correcting the sensing range of the sense amplifier unit.

In addition, the method for correcting the sense amplifier circuit of the memory of the present invention includes the following steps: first, providing the same voltage signal to the first connection end and the third connection end of the sense amplifier unit; Detecting the voltage levels of the first connection end and the third connection end of the sense amplifier unit, and determining whether the voltage levels of the first connection end and the third connection end are the same; and confirming the first connection end and the third connection end When the voltage levels of the terminals are different, the control unit outputs at least one control signal to the gate terminals of the parallel-coupled transistor switches to selectively turn on the parallel-coupled transistor switches, thereby correcting the sense amplifiers. The sensing range of the unit.

In summary, the sense amplifier circuit of the memory of the present invention and the calibration method thereof are coupled to each other on the two sides of the NMOS type transistor switch in the sense amplifier circuit, and are respectively coupled with a plurality of NMOS type transistor switches for correction. The sensing range of the sense amplifier circuit. In addition, the sense amplifier circuit can control the turn-on or turn-off of the NMOS-type transistor switches coupled in parallel by the control unit to instantly correct the sensing range and advance the data interpretation time of the sense amplifier circuit. In turn, the data reading performance of the memory is improved.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Please refer to FIG. 1. FIG. 1 is a block diagram of a circuit according to a first embodiment of the present invention. As shown in FIG. 1, the sense amplifier circuit 100 of the first embodiment of the present invention includes a sense amplifier unit 10, a first switch unit 20, a second switch unit 22, and a control unit 30.

The sense amplifier unit 10 can be constructed by cross-coupling a plurality of transistor switches. The sense amplifier unit 10 can be used to sense the content of the read memory cell (not shown). The sense amplifier unit 10 can be classified into a differential type and a non-differential type. The sense amplifier unit 10 has a first connection end 12, a second connection end 14, a third connection end 16 and a fourth connection end 18.

The first switching unit 20 is disposed on a first side (eg, the right side) of the sense amplifier unit 10. The first switch unit 20 is electrically coupled to the first connection end 12 and the second connection end 14 of the sense amplifier unit 10 , respectively. Furthermore, the first switching unit 20 can be constituted by the transistor switches T1, T3 to Tn. The transistor switches T1, T3~Tn are electrically coupled in parallel with each other, wherein the 汲 terminals of the transistor switches T1, T3~Tn are electrically coupled to the first connection terminal 12, and the transistor switches T1, T3~ The source terminals of the Tn are electrically coupled to the second connection end 14 . The transistor switches T1, T3~Tn are preferably NMOS type transistor switches. In addition, the channel width to length ratio (W/L) of the transistor switches T1, T3 to Tn may be the same or different from each other. In the first embodiment of the present invention, the channel width to length ratios of the transistor switches T1, T3 to Tn are the same as each other.

It is worth mentioning that when the channel width to length ratio of the transistor switches T1, T3~Tn can be different from each other, the relationship between the channel width to length ratio can be that the channel switch length ratio of the transistor switch T1 is larger than the transistor switch. The channel width to length ratio of T3 is greater than the channel width to length ratio of the transistor switch Tn. Alternatively, the channel width to length ratio may be such that the channel width to length ratio of the transistor switch T1 is smaller than the channel width to length ratio of the transistor switch T3 is smaller than the channel width to length ratio of the transistor switch Tn.

The second switching unit 22 is disposed on a second side (eg, the left side) of the sense amplifier unit 10. The second switch unit 22 is electrically coupled to the third connection end 16 and the fourth connection end 18 of the sense amplifier unit 10 , respectively. Furthermore, the second switching unit 22 can be composed of transistor switches T2, T4~Tm. The transistor switches T2, T4~Tm are electrically coupled in parallel with each other, wherein the 汲 terminals of the transistor switches T2, T4~Tm are electrically coupled to the third connection terminal 16, and the transistor switches T2, T4~ The source terminals of the Tm are electrically coupled to the fourth connection end 18 . In addition, the channel width to length ratio of the transistor switches T2, T4 to Tm may be the same or different from each other. In the first embodiment of the present invention, the channel width to length ratios of the transistor switches T2, T4 to Tm are the same as each other. It is worth mentioning that, in the first embodiment of the present invention, the channel width-length ratio of the transistor switches T1, T3~Tn is the same as the channel width-to-length ratio of the transistor switches T2, T4~Tm.

In addition, when the channel width-to-length ratios of the transistor switches T2, T4~Tm may be different from each other, the channel width-to-length ratio may be such that the channel width-to-length ratio of the transistor switch T2 is greater than the channel width of the transistor switch T4. The length ratio is greater than the channel width to length ratio of the transistor switch Tm. Alternatively, the channel width to length ratio may be such that the channel width to length ratio of the transistor switch T2 is smaller than the channel width to length ratio of the transistor switch T4 is smaller than the channel width to length ratio of the transistor switch Tm. In addition, the channel width to length ratio of the transistor switch in the first switching unit 20 and the second switching unit 22 may correspond. For example, the channel width to length ratio of the transistor switch T1 is equal to the channel width to length ratio of the transistor switch T2, but the channel width to length ratio of the transistor switch T1 is smaller than the channel width to length ratio of the transistor switch T3 and the transistor switch T4. And the transistor switch T3 has the same channel width to length ratio as the transistor switch T4. That is, the channel width to length ratio of the transistor switch that is farther away from the sense amplifier unit 10 is smaller. If there are other design requirements, the channel length to length ratio of the transistor switch that is farther away from the sense amplifier unit 10 can be adjusted, but not limited thereto.

The control unit 30 is electrically coupled to the first switch unit 20 and the second switch unit 22, respectively. Furthermore, the control unit 30 has a first input terminal In1, a second input terminal In2, output terminals Out1, Out3~Outn and output terminals Out2, Out4~Outm. The first input terminal In1 is electrically coupled to the 汲 terminal of the transistor switch Tn to form a first feedback path. The second input terminal In2 is electrically coupled to the 汲 terminal of the transistor switch Tm to form a second feedback path. The output terminal Out1 is electrically coupled to the gate terminal of the transistor switch T1, the output terminal Out3 is electrically coupled to the gate terminal of the transistor switch T3, and the output terminal Outn is electrically coupled to the gate terminal of the transistor switch Tn. analogy. Similarly, the output terminal Out2 is electrically coupled to the gate terminal of the transistor switch T2, the output terminal Out4 is electrically coupled to the gate terminal of the transistor switch T4, and the output terminal Outm is electrically coupled to the gate terminal of the transistor switch Tm. .

Therefore, the circuit characteristics of the sense amplifier unit 10 can be obtained after an initial test phase. For example, the sensing amplifier unit 10 is given two identical input signals, and the output of the sensing amplifier unit 10 is detected to be the same. If not, it indicates that the sensing amplifier unit 10 needs to be corrected. At this time, the feedback voltage is received through the first feedback path, so that the control unit 30 outputs a control signal to the first switching unit 20 to selectively turn on the transistor switches T1, T3~Tn of the first switching unit 20. Receiving another feedback voltage through the second feedback path, so that the control unit 30 outputs a control signal to the second switching unit 22 to selectively turn on the transistor switches T2 and T4 of the second switching unit 22. Tm. Thereby the sensing range of the sense amplifier unit 10 is corrected. The control unit 30 may be constituted by a continuous approximation register (SAR), but is not limited thereto.

In addition, in another embodiment of the present invention, part of the first switching unit 20 or the second switching unit 22 may be directly or after the testing phase via an initialization and according to the circuit characteristics of the sensing amplifier unit 10 The state of all of the transistor switches is fixed to be turned on or off to correct the sensing range of the sense amplifier unit 10. Next, the control unit 30 is removed, whereby the control unit 30 can be omitted.

Next, please refer to FIG. 2, which is a block diagram of a circuit according to a second embodiment of the present invention. As shown in FIG. 2, the sense amplifier circuit 110 of the second embodiment of the present invention includes a sense amplifier unit 10, a first switch unit 24, a second switch unit 26, and a control unit 32.

The sense amplifier unit 10 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8 and a ninth switch S9 is configured, wherein the first switch S1, the second switch S2, the sixth switch S6 and the eighth switch S8 are PMOS type transistor switches, and the third switch S3, the fourth switch S4, the fifth switch S5, and the seventh switch S7 and ninth switch S9 are NMOS type transistor switches. In addition, the circuit architecture of the sense amplifier unit 10 in the second embodiment of the present invention is only an example and is not limited thereto.

Furthermore, the 汲 of the first switch S1 is electrically coupled to the first connection end 12 . The gate terminal of the first switch S1 is electrically coupled to the third connection end 16 . The 汲 terminal of the second switch S2 is electrically coupled to the third connection end 16 . The gate terminal of the second switch S2 is electrically coupled to the first connection end 12 . The source terminal of the second switch S2 is electrically coupled to the source terminal of the first switch S1. The 汲 terminal of the third switch S3 is electrically coupled to the first connection end 12 . The gate terminal of the third switch S3 is electrically coupled to the third connection end 16 . The source terminal of the third switch S3 is electrically coupled to the second connection end 14 . The 汲 terminal of the fourth switch S4 is electrically coupled to the third connection end 16 . The gate terminal of the fourth switch S4 is electrically coupled to the first connection end 12 . The source terminal of the fourth switch S4 is electrically coupled to the fourth connection terminal 18. The 汲 terminal of the fifth switch S5 is electrically coupled to the source terminal of the third switch S3 and the source terminal of the fourth switch S4, respectively. The gate terminal of the fifth switch S5 receives the enable signal saen. The source terminal of the fifth switch S5 is grounded.

Next, the source terminal of the sixth switch S6 receives the bit line signal qin. The gate terminal of the sixth switch S6 receives the enable signal saen. The 汲 terminal of the sixth switch S6 is electrically coupled to the third connection end 16 . The 汲 terminal of the seventh switch S7 receives the bit line signal qin. The gate terminal of the seventh switch S7 receives the complementary enable signal saenb. The source terminal of the seventh switch S7 is electrically coupled to the third connection end 16 . The source terminal of the eighth switch S8 receives the complementary bit line signal qinb. The gate terminal of the eighth switch S8 receives the enable signal saen. The 汲 terminal of the eighth switch S8 is electrically coupled to the first connection end 12 . The 汲 terminal of the ninth switch S9 receives the complementary bit line signal qinb. The gate terminal of the ninth switch S9 receives the complementary enable signal saenb. The source terminal of the ninth switch S9 is electrically coupled to the first connection end 12. In addition, the first connection end 12 is electrically coupled to the first input end In1 of the control unit 32, and the third connection end 16 is also electrically coupled to the second input end In2 of the control unit 32.

The first switching unit 24 includes a transistor switch T1, a transistor switch T3, and a transistor switch T5. The first switch unit 24 is electrically coupled to the sense amplifier unit 10 and the control unit 32, respectively. Furthermore, the transistor switch T1 and the transistor switch T3 are electrically coupled to the first terminal 12 of the transistor switch T5. The transistor switch T1 and the transistor switch T3 are electrically coupled to the source terminal of the transistor switch T5 to the second connection end 14. The gate terminal of the transistor switch T1 is electrically coupled to the output terminal Out1 of the control unit 32. The gate terminal of the transistor switch T3 is electrically coupled to the output terminal Out3 of the control unit 32. The gate terminal of the transistor switch T5 is electrically coupled to the output terminal Out5 of the control unit 32.

It is worth mentioning that the channel width to length ratio of the transistor switch T1 is greater than the channel width to length ratio of the transistor switch T3 is greater than the channel width to length ratio of the transistor switch T5. In other words, the ratio of the passable current when the transistor switch T1, the transistor switch T3, and the transistor switch T5 are turned on is 4:2:1. In addition, the transistor switch T1 can be regarded as the innermost transistor switch of the first switching unit 24.

The second switching unit 26 includes a transistor switch T2, a transistor switch T4 and a transistor switch T6. The second switch unit 26 is electrically coupled to the sense amplifier unit 10 and the control unit 32, respectively. Furthermore, the transistor switch T2 and the transistor switch T4 are electrically coupled to the third terminal 16 of the transistor switch T6. The transistor switch T2 and the transistor switch T4 are electrically coupled to the source terminal of the transistor switch T6 to the fourth connection terminal 18. The gate terminal of the transistor switch T2 is electrically coupled to the output terminal Out2 of the control unit 32. The gate terminal of the transistor switch T4 is electrically coupled to the output terminal Out4 of the control unit 32. The gate terminal of the transistor switch T6 is electrically coupled to the output terminal Out6 of the control unit 32.

It is worth mentioning that the channel width to length ratio of the transistor switch T2 is greater than the channel width to length ratio of the transistor switch T4 is greater than the channel width to length ratio of the transistor switch T6. In other words, the ratio of the passable current when the transistor switch T2, the transistor switch T4 and the transistor switch T6 are turned on is 4:2:1. In addition, the transistor switch T2 can be regarded as the innermost transistor switch of the second switching unit 26.

Next, please refer to FIG. 2 and FIG. 3 together. FIG. 3 is a control timing diagram of the second embodiment of the present invention. As shown in FIG. 3, when the initialization phase is performed, the bit line signal qin and the complementary bit line signal qinb are given the same voltage value, and the first connection end 12 and the third connection end 16 are detected to obtain respective Logic level. For example, when the logic level obtained by the first connection terminal 12 is '0' and the logic level obtained by the third connection terminal 16 is '1', it indicates that the fourth switch S4 needs to perform a corrective action.

Therefore, the control unit 32 can complete the corrective action through three cycles. Furthermore, at cycle 1, the output terminal Out2 of the control unit 32 is caused to output a high level control signal to the transistor switch T2 to conduct the crystal switch T2. On the other hand, the output terminal Out1 of the control unit 32 outputs a low level control signal to the transistor switch T1 and maintains the transistor switch T1 closed.

Then, through the feedback path, it can be known that the logical levels of the first connection end 12 and the third connection end 16 do not change. Therefore, at cycle 2, the output terminal Out4 of the control unit 32 is caused to output a high level control signal to the transistor switch T4 to conduct the crystal switch T4. On the other hand, the output terminal Out3 of the control unit 32 outputs a low level control signal to the transistor switch T3 and maintains the transistor switch T3 closed.

Then, when the offset voltage of the second switching unit 26 is higher than the offset value, the logic level of the first connection terminal 12 and the third connection terminal 16 can be changed through the feedback path. Therefore, at cycle 3, the output terminal Out5 of the control unit 32 is caused to output a high level control signal to the transistor switch T5 to conduct the crystal switch T5. On the other hand, the output terminal Out6 of the control unit 32 outputs a low level control signal to the transistor switch T6 and maintains the transistor switch T6 closed.

4A and FIG. 4B, FIG. 4A is a schematic diagram of signal waveform simulation of a portion of the end of the sense amplifier circuit of the prior art, and FIG. 4B is a schematic diagram of signal waveform simulation of a portion of the end of the sense amplifier circuit according to the embodiment of the present invention. schematic diagram. As shown in FIG. 4A, the sensing amplifier circuit of the prior art does not incorporate a correction circuit, and the sensing range of the sense amplifier circuit ranges from about -80 mv to +80 mv. As shown in FIG. 4B, the sense amplifier circuit 100 (shown in FIG. 1) of the embodiment of the present invention performs correction of the sensing range through the first switching unit 10, the second switching unit 20, and the control unit 30, and the sensing amplifier The sensing range of circuit 100 is from about -30 mv to +30 mv. Therefore, the sense amplifier circuit 100 of the embodiment of the present invention can advance the data interpretation time by about 37.5%, thereby improving the data reading performance of the memory.

Next, please refer to FIG. 1 , FIG. 5A and FIG. 5B together. FIG. 5A and FIG. 5B are flowcharts of steps of a method for correcting the sense amplifier circuit of the memory according to the embodiment of the present invention. First, in step S501, the same voltage signal is supplied to the first connection terminal 12 and the third connection terminal 16 of the sense amplifier unit 10 to initially test whether the sense amplifier unit 10 needs to be corrected.

Next, in step S503, at the next timing, the voltage levels of the first connection end 12 and the third connection end 16 of the sense amplifier unit 10 are detected, and the first connection end 12 and the third connection end are determined. Is the voltage level of 16 the same? For example, when the voltage levels of the first connection end 12 and the third connection end 16 are the same, the corrective action can be omitted and ended.

Then, in step S505, it is determined via the feedback path whether the voltage level of the first connection terminal 12 and the third connection terminal 16 is higher. In step S507, when it is confirmed that the voltage level of the first connection terminal 12 is higher than the voltage level of the third connection terminal 16, the control unit 30 outputs at least one control signal to the first switching unit 20 to selectively conduct the current. The parallel-coupled transistor switches T1, T3, . . . Tn, in turn, correct the sensing range of the sense amplifier circuit unit 10. In addition, in step S511, when it is confirmed that the voltage level of the first connection terminal 12 is lower than the voltage level of the third connection terminal 16, the control unit 30 outputs at least one control signal to the second switching unit 20 to selectively The parallel-coupled transistor switches T2, T4, . . . Tm are turned on, thereby correcting the sensing range of the sense amplifier circuit unit 10.

In step S509, it is determined whether the voltage level of the first connection terminal 12 and the third connection terminal 16 is in a transition state via the feedback path. When the voltage level transition state of the first connection end 12 and the third connection end 16 is confirmed, the process ends. When it is confirmed that the voltage levels of the first connection terminal 12 and the third connection terminal 16 are not changed, the process returns to step S505 to continue to determine whether the voltage levels of the first connection terminal 12 and the third connection terminal 16 are higher.

In summary, the sense amplifier circuit of the memory of the present invention and the calibration method thereof are coupled to each other on the two sides of the NMOS type transistor switch in the sense amplifier circuit, and are respectively coupled with a plurality of NMOS type transistor switches for correction. The sensing range of the sense amplifier circuit. In addition, the sense amplifier circuit can control the turn-on or turn-off of the NMOS-type transistor switches coupled in parallel by the control unit to instantly correct the sensing range and advance the data interpretation time of the sense amplifier circuit. In turn, the data reading performance of the memory is improved.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10. . . Sense amplifier unit

12. . . First connection

14. . . Second connection

16. . . Third connection

18. . . Fourth connection

100. . . Sense amplifier circuit

110. . . Sense amplifier circuit

20. . . First switch unit

twenty two. . . Second switching unit

twenty four. . . First switch unit

26. . . Second switching unit

30. . . control unit

32. . . control unit

In1. . . First input

In2. . . Second input

Out1. . . Output

Out2. . . Output

Out3. . . Output

Out4. . . Output

Out5. . . Output

Out6. . . Output

Outm. . . Output

Outn. . . Output

Qin. . . Bit line signal

Qinb. . . Complementary bit line signal

S1. . . First switch

S2. . . Second switch

S3. . . Third switch

S4. . . Fourth switch

S5. . . Fifth switch

S6. . . Sixth switch

S7. . . Seventh switch

S8. . . Eighth switch

S9. . . Ninth switch

Saen. . . Enable signal

Saenb. . . Complementary enable signal

T1. . . Transistor switch

T2. . . Transistor switch

T3. . . Transistor switch

T4. . . Transistor switch

T5. . . Transistor switch

T6. . . Transistor switch

Tm. . . Transistor switch

Tn. . . Transistor switch

S501~S5011. . . Method step description

1 is a block diagram of a circuit according to a first embodiment of the present invention.

2 is a block diagram of a circuit according to a second embodiment of the present invention.

3 is a timing chart showing the control of the second embodiment of the present invention.

4A is a schematic diagram of signal waveform simulation of a portion of an end point of a sense amplifier circuit of the prior art.

4B is a schematic diagram of signal waveform simulation of a portion of an end point of a sense amplifier circuit according to an embodiment of the invention.

5A and FIG. 5B are flowcharts showing steps of a method for correcting a sense amplifier circuit of a memory according to an embodiment of the invention.

10. . . Sense amplifier unit

12. . . First connection

14. . . Second connection

16. . . Third connection

18. . . Fourth connection

20. . . First switch unit

twenty two. . . Second switching unit

30. . . control unit

100. . . Sense amplifier circuit

T1. . . Transistor switch

T2. . . Transistor switch

T3. . . Transistor switch

T4. . . Transistor switch

Tn. . . Transistor switch

Tm. . . Transistor switch

Out1. . . Output

Out2. . . Output

Out3. . . Output

Out4. . . Output

Outm. . . Output

Outn. . . Output

In1. . . First input

In2. . . Second input

Claims (11)

A sense amplifier circuit includes: a sense amplifier unit, comprising a plurality of transistor switches, having a first connection end, a second connection end, a third connection end and a fourth connection end; a switch unit coupled in parallel to the first connection end and the second connection end of the sense amplifier unit; and a second switch unit coupled in parallel to the third connection end of the sense amplifier unit a fourth connection end; wherein the first switch unit and the second switch unit are respectively coupled by a plurality of transistor switches coupled in parallel with each other, and correcting the sense according to whether the parallel connection of the transistor switches is turned on or off The sensing range of the amplifier unit. The sensing amplifier circuit of claim 1, comprising a control unit electrically coupled to the first connection end and the third connection end to respectively form a first feedback path and a first a second feedback path, and the control unit has a plurality of output terminals electrically coupled to the gate terminals of the parallel coupled transistor switches, and the control unit transmits the first feedback path The second feedback path receives a feedback voltage to generate a control signal required to turn on the parallel coupled transistor switches. The sense amplifier circuit of claim 2, wherein the sense amplifier unit comprises: a first switch, the first switch is electrically coupled to the first connection end, the first The gate of the switch is electrically coupled to the third terminal; a second switch, the source of the second switch is electrically coupled to the source terminal of the first switch, and the gate of the second switch is electrically coupled Connected to the first connection end, the second end of the second switch is electrically coupled to the third connection end; a third switch, the third end of the third switch is electrically coupled to the third connection end, The 开关 terminal of the third switch is electrically coupled to the first connection end, and the source terminal of the third switch is electrically coupled to the second connection end; a fourth switch, the gate terminal of the fourth switch is electrically coupled Connected to the first connection end, the first switch is electrically coupled to the third connection end, the source of the fourth switch is electrically coupled to the fourth connection end; a fifth switch, the fifth switch The gate terminal of the fifth switch receives the uniform energy signal, and the 汲 terminal of the fifth switch is electrically coupled to the first a third switch and a source terminal of the fourth switch, the source terminal of the fifth switch is grounded; a sixth switch, the gate terminal of the sixth switch receives the enable signal, and the 开关 terminal of the sixth switch is electrically coupled The third terminal, the source terminal of the sixth switch receives a bit line signal; a seventh switch, the 开关 terminal of the seventh switch is electrically coupled to the source terminal of the sixth switch, and the seventh switch The gate terminal receives a complementary enable signal, the source terminal of the seventh switch is electrically coupled to the third connection end; and an eighth switch, the gate terminal of the eighth switch receives the enable signal, and the eighth switch The source terminal receives a complementary bit line signal, the 开关 terminal of the eighth switch is electrically coupled to the first connection end; and a ninth switch, the 汲 terminal of the ninth switch is electrically coupled to the eighth switch a source terminal, the gate terminal of the ninth switch receives the complementary enable signal, and the source terminal of the ninth switch is electrically coupled to the first connection end; wherein the first connection end is further electrically coupled to the control a first input end of the unit to constitute the first feedback path, the third It is also electrically connected to terminal coupled to the second input terminal of the control unit, to constitute the second feedback path. The sense amplifier circuit of claim 1, wherein the parallel coupled transistor switches have the same channel width to length ratio (W/L). The sense amplifier circuit of claim 1, wherein the parallel coupled transistor switches have different channel aspect ratios (W/L). The sense amplifier circuit of the memory of claim 1, wherein the number of the parallel-coupled transistor switches in the first switch unit is equal to the parallel couplings in the second switch unit. The number of transistor switches. The sense amplifier circuit of claim 1, wherein an innermost transistor switch of the parallel-coupled transistor switches in the first switch unit has a channel width-to-length ratio greater than a remaining transistor switch. The channel width to length ratio, and the channel width to length ratio of the innermost transistor switches of the parallel coupled transistor switches in the second switching unit is greater than the channel width to length ratio of the remaining transistor switches. The sense amplifier circuit of claim 7, wherein a channel width-to-length ratio of the innermost transistor switch of the parallel-coupled transistor switches in the first switch unit is equal to the second switch unit The channel width to length ratio of the innermost transistor switch of the parallel coupled transistor switches. A method for correcting a sense amplifier circuit includes the steps of: providing a sense amplifier circuit comprising: a sense amplifier unit, comprising a plurality of transistor switches, having a first connection end and a second connection end a third connection end and a fourth connection end; a first switch unit, which is composed of a plurality of transistor switches coupled in parallel with each other, and coupled in parallel to the first connection end of the sense amplifier unit and the first a second connection unit, the second switch unit is composed of a plurality of transistor switches coupled in parallel with each other, and coupled in parallel to the third connection end and the fourth connection end of the sense amplifier unit; and a control unit, Electrically coupled to the first connection end and the third connection end to respectively form a first feedback path and a second feedback path, and the control unit has a plurality of output ends, and the output ends are respectively electrically Is coupled to the gate terminals of the parallel-coupled transistor switches; providing the same voltage signal to the first connection end and the third connection end of the sense amplifier unit; a voltage level of the first connection end and the third connection end of the sense amplifier unit, and determining whether the voltage level of the first connection end and the third connection end are the same; and confirming the first connection end and the When the voltage levels of the third connection terminals are different, the control unit outputs at least one control signal to the gate terminals of the parallel-coupled transistor switches to selectively turn on the parallel-coupled transistor switches, thereby correcting The sensing range of the sense amplifier unit. The method for correcting a sense amplifier circuit according to claim 9, wherein when the voltage level of the first connection terminal is higher than a voltage level of the third connection terminal, turning on the first of the first switch units A transistor switch coupled in parallel. The method for correcting a sense amplifier circuit according to claim 9, wherein when the voltage level of the first connection terminal is lower than the voltage level of the third connection terminal, turning on the second switch unit A transistor switch coupled in parallel.