TWI515563B - 用於階層式記憶體系統之記憶體管理 - Google Patents
用於階層式記憶體系統之記憶體管理 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0653—Monitoring storage devices or systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1008—Correctness of operation, e.g. memory ordering
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/65—Details of virtual memory and virtual address translation
- G06F2212/657—Virtual address space management
Description
本發明之實施例大體上係關於記憶體管理。更具體言之,本發明之實施例可提供用於一階層式記憶體系統中之記憶體管理之一或多種技術。
電腦系統通常用於數種組態中以提供多種計算功能。被分派開發電腦系統及系統組件之任務之設計工程師通常考慮處理速度、系統靈活性、電力消耗及大小約束。電腦系統大體上包含複數個記憶體裝置(例如,一雙列直插記憶體模組(DIMM)可含有8個、16個或更多個記憶體裝置,一堆疊NAND快閃封裝可含有2個、4個或8個NAND晶粒)及可用以儲存資料(例如,程式及使用者資料)且可存取諸如處理器或周邊裝置之其他系統組件之複數個記憶體類型(即,可具有不同效能及/或電力特性之記憶體裝置)。此等記憶體裝置可包含揮發性及非揮發性記憶體裝置。
通常,藉由一記憶體管理系統管理一計算系統之記憶體位址空間。在某些計算系統中,記憶體管理系統可將記憶體位址空間之部分動態地分配至藉由處理器執行之程式且可將記憶體位址空間之一分離部分分配至由此一程式使用之資料。相反地,當處理器不再執行程式時,記憶體管理系統可自程式解除分配記憶體位址空間之部分。記憶
體管理系統可包含用以將由處理器使用之虛擬記憶體位址映射至實體記憶體位址空間之表。此等表可包含一主記憶體轉譯表(MMXT)及一轉譯後備緩衝器(TLB)。通常TLB含有用於使用頻率大於MMXT中之記憶體位址之記憶體位址之記憶體映射。在MMXT及/或TLB中搜尋一記憶體映射可耗費時間,從而導致延遲資料擷取。
記憶體系統通常配置有一記憶體階層。例如,可在暫存器、快取區(例如,層級1、層級2、層級3)、主記憶體(例如,RAM)、磁碟儲存器等等中發現特定記憶體。如可了解,一些記憶體系統包含具有不同操作特性(例如,以不同速度操作)之記憶體類型。然而,記憶體管理系統大體上不區分記憶體系統中之記憶體類型(例如,主記憶體)。
因此,此等記憶體管理系統可以相同方式處置所有類型的記憶體。進一步言之,記憶體系統中之一些記憶體裝置可存取(例如,自一些記憶體裝置讀取及/或寫入至一些記憶體裝置)的次數大於記憶體系統中之其他記憶體裝置。因而,一記憶體管理系統可能難以識別(例如,判定)記憶體系統內以一特定速度操作之記憶體裝置。同樣地,一記憶體管理系統可能難以識別存取次數大於其他記憶體裝置之記憶體裝置。
因此,本發明之實施例可針對上文陳述之問題之一或多者。
10‧‧‧基於處理器之系統
12‧‧‧處理器
13‧‧‧快取區
14‧‧‧階層式記憶體系統
16‧‧‧系統匯流排
18‧‧‧記憶體管理系統
20‧‧‧記憶體裝置/記憶體_0
22‧‧‧記憶體裝置/記憶體_1
24‧‧‧記憶體裝置/記憶體_N
26‧‧‧資料匯流排PA_0
28‧‧‧資料匯流排PA_1
30‧‧‧資料匯流排PA_N
32‧‧‧虛擬記憶體位址
34‧‧‧實體記憶體位址
36‧‧‧頁錯誤
38‧‧‧轉譯(XLAT)轉譯裝置
40‧‧‧轉譯後備緩衝器(TLB)
42‧‧‧表
44‧‧‧列
46‧‧‧虛擬記憶體位址欄
48‧‧‧實體記憶體位址欄
50‧‧‧最近最少使用(LRU)欄
52‧‧‧裝置識別(TYPE)欄
54‧‧‧轉譯表(XT)
56‧‧‧控制單元
58‧‧‧列
60‧‧‧虛擬記憶體位址欄
62‧‧‧實體記憶體位址欄
64‧‧‧最近最少使用(LRU)欄
66‧‧‧裝置識別(TYPE)欄
68‧‧‧方法
70‧‧‧步驟
72‧‧‧步驟
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90‧‧‧流程圖
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圖1圖解說明根據本發明之實施例之一基於處理器之系統之一方塊圖;圖2圖解說明根據本發明之實施例之一記憶體管理系統之一方塊圖;圖3圖解說明根據本發明之實施例之一轉譯後備緩衝器之一方塊圖;圖4圖解說明根據本發明之實施例之一轉譯裝置之一方塊圖;
圖5圖解說明根據本發明之實施例之用於在一記憶體管理系統接收一虛擬記憶體位址時存取一實體記憶體位址之一方法之一流程圖;及圖6圖解說明根據本發明之實施例之用於管理一計算系統之實體記憶體位址空間之一方法之一流程圖。
一些隨後論述之實施例可促進更多功能性之記憶體系統,諸如使用多個不同類型的記憶體裝置之記憶體系統及動態地重新配置儲存於該等不同類型的記憶體裝置上之資料之記憶體系統。如下文詳細地描述,一記憶體管理系統可包含使一實體記憶體位址與一記憶體裝置類型相關之一表。例如,一記憶體管理系統可包含具有多個虛擬記憶體位址之一表。各虛擬記憶體位址可對應於一實體記憶體位址且對應於識別一對應記憶體裝置類型之資料。實體記憶體位址可用以在發生表命中時存取記憶體裝置。因而,下列論述描述根據本技術之實施例之裝置及方法。
現在參考該等圖式且最初參考圖1,圖解說明描繪一基於處理器之系統(整體由參考數字10標示)之一方塊圖。系統10可為多種類型之任一者,諸如電腦、傳呼機、蜂巢式電話、個人記事簿、控制電路等等。在一典型基於處理器之裝置中,諸如微處理器之一或多個處理器12控制系統10中之系統功能及請求之處理。如應了解,處理器12可包含用於將組件耦合至處理器12之一嵌入式北橋或南橋(未展示)。或者,系統10可包含耦合在處理器12與系統10之各種組件之間之分離橋。如圖解說明,處理器12可包含快取區13(例如,CPU快取區)以減小處理器12存取記憶體所花費的平均時間。
各種裝置可取決於系統10執行之功能而耦合至處理器12。例如,一使用者介面可耦合至處理器12。使用者介面可包含(例如)按
鈕、開關、一鍵盤、一光筆、一滑鼠、一顯示器及/或一語音辨識系統。顯示器可包含(例如)一觸控顯示器、一LCD顯示器、一CRT、LED及/或一音訊顯示器。一或多個通信埠亦可耦合至處理器12。通信埠可經調適以耦合至一或多個周邊裝置(諸如一數據機、一印表機、一電腦)或耦合至一網路(諸如(例如)一區域網路、遠端區域網路、內部網路或網際網路)。
因為處理器12通常藉由實施軟體程式控制系統10之運行,所以記憶體可操作地耦合至處理器12以儲存並促進各種程式之執行。因此,一階層式記憶體系統14係經由一系統匯流排16可操作地耦合至處理器12。階層式記憶體系統14包含一記憶體管理系統18及任何數目個記憶體裝置。例如,階層式記憶體系統14可包含(例如,一第一類型之)一記憶體_0 20、(例如,一第二類型之)一記憶體_1 22及由(例如,一第n類型之)記憶體_N 24表示之任何額外的記憶體裝置。
記憶體管理系統18可執行多種記憶體管理功能。例如,記憶體管理系統18可管理虛擬記憶體位址至實體記憶體位址轉譯、記憶體重新分配、記憶體組織、記憶體使用等等。如圖解說明,記憶體管理系統18係藉由各自資料匯流排PA_0 26、PA_1 28及PA_N 30可操作地耦合至記憶體裝置20、22及24。如應了解,PA_N 30可表示對應於記憶體裝置記憶體_N 24之數個資料匯流排。
記憶體裝置20、22及24之一或多者可為揮發性記憶體,其可包含動態隨機存取記憶體(DRAM)及/或靜態隨機存取記憶體(SRAM)。揮發性記憶體可包含數個記憶體模組,諸如單列直插記憶體模組(SIMM)、雙列直插記憶體模組(DIMM)及/或混合記憶體立方體(HMC)。如應了解,揮發性記憶體可簡稱為「系統記憶體」。揮發性記憶體通常相當大使得其可儲存經動態載入之應用程式及資料。
進一步言之,記憶體裝置20、22及24之一或多者可為非揮發性
記憶體,其可包含諸如EPROM之唯讀記憶體(ROM)、快閃記憶體(例如,NOR及/或NAND)及/或結合揮發性記憶體使用之相變記憶體(PCM)。ROM之大小通常經選擇足夠大以儲存任何必要的作業系統、應用程式及固定資料。此外,非揮發性記憶體可包含一高容量記憶體,諸如一磁帶機或磁碟機記憶體。因此,記憶體裝置20、22及24無須為區塊儲存裝置。
因而,階層式記憶體系統14通用於容許許多類型的記憶體裝置20、22及24可操作地耦合至處理器12。因此,記憶體管理系統18可適於階層式記憶體系統14以最佳化記憶體裝置20、22及24之效能。圖2至圖4中圖解說明經調適用於階層式記憶體系統14之記憶體管理系統18之一些實例。具體言之,圖2圖解說明具有一轉譯(XLAT)轉譯裝置及一轉譯後備緩衝器之一記憶體管理系統18,且圖3及圖4分別進一步圖解說明轉譯後備緩衝器及XLAT轉譯裝置。圖5及圖6圖解說明記憶體管理系統18可用來管理記憶體裝置20、22及24之方法。
現在參考圖2,圖解說明記憶體管理系統18之一方塊圖。在操作期間,記憶體管理系統18(例如,自處理器12)接收一虛擬記憶體位址32。記憶體管理系統18識別映射至虛擬記憶體位址32且用以存取記憶體裝置20、22及24之一者之一實體記憶體位址34。若記憶體管理系統18不能識別映射至虛擬記憶體位址32之實體記憶體位址34,則記憶體管理系統18產出(例如,產生)可傳輸至處理器12之一頁錯誤36。
為識別映射至虛擬記憶體位址32之實體記憶體位址34,記憶體管理系統18使用一XLAT轉譯裝置38及一轉譯後備緩衝器(TLB)40。XLAT轉譯裝置38及TLB 40可各自儲存將虛擬記憶體位址映射至實體記憶體位址之一各自表。雖然單獨圖解說明XLAT轉譯裝置38及TLB 40,但是在某些實施例中,XLAT轉譯裝置38及TLB 40可併入單個裝置內。如應了解,XLAT轉譯裝置38及TLB 40可含有非重疊資料。例
如,XLAT轉譯裝置38可含有用於虛擬記憶體位址之一第一部分之表項目,而TLB 40含有用於虛擬記憶體位址之一第二部分之表項目。
通常,TLB 40含有用於存取頻率大於儲存於XLAT轉譯裝置38中之虛擬記憶體位址之虛擬記憶體位址之表項目。在某些實施例中,對虛擬記憶體位址32之一搜尋可同時發生在XLAT轉譯裝置38及TLB 40中。在其他實施例中,在XLAT轉譯裝置38中發生對虛擬記憶體位址32之一搜尋之前可於TLB 40中發生該搜尋。然而,在識別(例如,定位)包含虛擬記憶體位址32之一表項目之後,XLAT轉譯裝置38及TLB 40二者皆停止搜尋虛擬記憶體位址32。
在本實施例中,XLAT轉譯裝置38及TLB 40可各自儲存與存取一特定虛擬記憶體位址及/或實體記憶體位址之頻率有關的資料。進一步言之,XLAT轉譯裝置38及TLB 40可各自儲存識別對應於實體記憶體位址之一記憶體裝置類型之資料。如下文詳細地解釋,使用此額外資料,記憶體管理系統18可最佳化記憶體使用及/或最佳化儲存於XLAT轉譯裝置38及TLB 40中之表映射資料。
因此,圖3圖解說明可儲存與存取一特定虛擬記憶體位址及/或實體記憶體位址之頻率有關的資料且可儲存識別對應於該特定實體記憶體位址之一記憶體裝置類型之資料之TLB 40之一方塊圖。在某些實施例中,TLB 40可為一內容可定址記憶體(CAM)裝置或n路關聯記憶體裝置。具體言之,TLB 40儲存具有列44及欄(46至52)之一表42。在本實施例中,各列44與一分離表項目有關。因而,各列44包含一虛擬記憶體位址欄46、一實體記憶體位址欄48、一最近最少使用(LRU)欄50及一裝置識別(TYPE)欄52。
虛擬記憶體位址欄46包含TLB 40中含有之所有虛擬記憶體位址之一清單。進一步言之,實體記憶體位址欄48包含各列44中對應於各自列44之虛擬記憶體位址欄46中之虛擬記憶體位址之一實體記憶體位
址。LRU欄50包含與存取一各自實體記憶體位址之頻率有關的資料(例如,存取或使用資料)。例如,LRU欄50可包含表示已存取其對應虛擬記憶體位址及/或實體記憶體位址之總次數之一值。因而,LRU欄50可用以識別是否應自表42移除表項目。例如,可自表42移除存取頻率最小(例如,在LRU欄50中儲存有最低值)之列44。
TYPE欄52包含各列44中識別對應於各自列44之實體記憶體位址欄48中之實體記憶體位址之一裝置類型之裝置識別資料。(例如,當發生表命中時)使用實體記憶體位址存取裝置。例如,裝置識別資料可為對應於一裝置類型之一值。如應了解,記憶體管理系統18可包含對應於各裝置之資料。例如,記憶體管理系統18可包含諸如以下各者之資料:各裝置之一名稱、各裝置之一操作速度、指派至各裝置之一匯流排、各裝置相對於其他實體裝置之相對速度之一指示、各裝置之一耐久性等等。在操作期間,實體位址可用以直接存取記憶體裝置20、22及24,藉此快速地存取儲存於記憶體裝置20、22及24上之資料。
參考圖4,圖解說明XLAT轉譯裝置38之一方塊圖。XLAT轉譯裝置38包含一轉譯表(XT)54,該轉譯表(XT)54可儲存與存取一特定虛擬記憶體位址及/或實體記憶體位址之頻率有關之資料且可儲存識別對應於各實體記憶體位址之記憶體裝置之一類型之資料。進一步言之,XLAT轉譯裝置38包含用於控制XLAT轉譯裝置38之各種操作之一控制單元56(例如,一混合記憶體立方體之一邏輯晶粒)。具體言之,XT 54儲存具有列58及欄(60至66)之一表。在本實施例中,各列58與一分離表項目有關。因而,各列58包含一虛擬記憶體位址欄60、一實體記憶體位址欄62、一LRU欄64及一TYPE欄66。
虛擬記憶體位址欄60包含XT 54中含有之所有虛擬記憶體位址之一清單。進一步言之,實體記憶體位址欄62包含各列58中對應於各自
列58之虛擬記憶體位址欄60中之虛擬記憶體位址之一實體記憶體位址。LRU欄64包含與存取一各自實體記憶體位址之頻率有關之資料(例如,存取或使用資料)。例如,LRU欄64可包含表示已存取其各自虛擬記憶體位址及/或實體記憶體位址之總次數之一值。因而,LRU欄64可(藉由轉譯裝置38之控制單元56)用以識別是否應將表項目自XT 54移動至TLB 40。例如,至少在一些條件中,可將以最高頻率存取(例如,在LRU欄64中儲存有最高值)之列58自XT 54移動至TLB 40。
TYPE欄66包含各列58中識別對應於各自列58之實體記憶體位址欄62中之實體記憶體位址之一裝置類型之識別資料。該裝置係(例如,在發生表命中時)使用實體記憶體位址加以存取。例如,裝置識別資料可為對應於一裝置類型之一值。在操作期間,實體記憶體位址可用以直接存取記憶體裝置20、22及24,藉此快速地存取儲存於記憶體裝置20、22及24上之資料。
XLAT轉譯裝置38可為多種不同裝置之任一者,諸如一混合記憶體立方體(HMC)或諸如美國公開案第2010/0138575號中所揭示者之一型樣辨識裝置。此外,硬體(例如,處理器)及/或軟體可用以執行XT 54之一搜尋。如應了解,尤其在儲存於主記憶體中之情況下,延長對XT 54之存取可導致一顯著效能損失(例如,在轉譯裝置38本身用作主記憶體之情況下,若具體實施於一HMC裝置中,則情況可能如此)。因此,除記憶體單元之外,某些轉譯裝置38亦可包含硬體及/或軟體邏輯。例如,XT 54可儲存於一高效能記憶體陣列(HPMA)(例如,HMC)或一輔助式搜尋記憶體裝置(諸如先前提及之型樣辨識裝置)上。此等裝置可經組態以搜尋XT 54內之虛擬記憶體位址(例如,執行一表查詢(table walk))。應注意,TLB 40亦可儲存於一HPMA或一輔助式搜尋記憶體裝置上。在某些實施例中,TLB 40及XT 54可儲存於相同裝置上。藉由使用一HPMA或一輔助式搜尋記憶體裝置,可達成
改良之效能。在某些實施例中,控制單元56可用以執行多種功能。例如,控制單元56可控制頁表查詢、TLB更新、LRU計算、LRU更新、頁移動之直接記憶體存取、動態地重新配置指派至該等裝置之資料、動態地改變虛擬記憶體位址至實體記憶體位址之映射等等。
控制單元56可包含軟體及/或硬體以輔助記憶體管理系統18之功能。因而,圖5圖解說明用於在記憶體管理系統18接收到一虛擬記憶體位址時存取一實體記憶體位址之一方法68之一流程圖。在方塊70處,記憶體管理系統18接收一虛擬記憶體位址。接著,在方塊72處,記憶體管理系統18搜尋TLB 40中之虛擬記憶體位址(例如,執行查找)。接著,在方塊74處,判定記憶體管理系統18是否已識別(例如,發現)TLB 40中之虛擬記憶體位址。若存在一TLB「未命中」,則在方塊76處,記憶體管理系統18搜尋XT 54中之虛擬記憶體位址(例如,執行一查找或一表查詢)。接著,在方塊78處,判定管理記憶體系統18是否已識別XT 54中之虛擬記憶體位址。若存在一XT「未命中」,則在方塊80處,記憶體管理系統18產生發送至處理器12之一頁錯誤36。
若存在一XT「命中」,則在方塊82處,記憶體管理系統將XT表項目移動至TLB 40。進一步言之,在方塊82處,記憶體管理系統18將最少使用之TLB 40項目移動至XT 54。接著,在方塊84處,記憶體管理系統18將虛擬記憶體位址轉譯為一實體記憶體位址。這發生在方塊82之後,或回應於經由方塊74發生之一TLB「命中」而發生。如應了解,將虛擬記憶體位址轉譯為實體記憶體位址可包含存取與虛擬記憶體位址有關之項目中之所有資料。例如,記憶體管理系統18可自用於存取記憶體裝置之表項目擷取TYPE欄資料。在方塊86處,更新(例如,修改)所存取表項目之LRU資料。例如,可使儲存於LRU欄中之值增加1。接著,在方塊88處,存取實體記憶體位址。
現在參考圖6,圖解說明用於管理一計算系統之一記憶體位址空
間之一方法之一流程圖90。在方塊92處,記憶體管理系統18可使用LRU資料以對表項目進行排序,諸如基於存取一表項目之一虛擬記憶體位址及/或一實體記憶體位址之次數而對該表項目進行排序。接著,在方塊94處,記憶體管理系統18可識別使用量大於其他表項目之表項目及/或記憶體管理系統18可識別使用量小於其他表項目之表項目。接著,在方塊96處,記憶體管理系統18可比較被分配至所識別項目之記憶體裝置之類型與記憶體裝置之可用類型。例如,記憶體管理系統18可識別使用量較大(例如,較高存取速率)之表項目是否被分配至優於使用量較小之表項目之記憶體類型(例如,較快記憶體、改良之耐久性)。在方塊98處,記憶體管理系統18可識別是否存在存取實體記憶體位址之次數與對應於實體記憶體位址之記憶體裝置之一類型之間之一失配。
若不存在一失配,則方法可返回至方塊92。然而,若存在存取實體記憶體位址之次數與對應於實體記憶體位址之記憶體裝置之類型之間之一失配,則記憶體管理系統18可經由方塊100識別是否可執行一記憶體交換。在某些實施例中,一記憶體交換可包含使儲存於一第一類型之記憶體中之一第一資料集合與儲存於一第二類型之記憶體中之一第二資料集合互換。例如,記憶體管理系統18可將儲存於一第一類型之記憶體中之一第一資料集合移動至一第二類型之記憶體,且將儲存於該第二類型之記憶體中之一第二資料集合移動至該第一類型之記憶體。此外,可同時發生移動第一資料集合及第二資料集合。例如,某些類型的記憶體可支援同時發生於兩個方向上之資料移動,諸如DRAM DIMM及HMC以及DRAM DIMM及PCM。若無法執行一記憶體交換,則記憶體管理系統18可經由方塊102識別是否存在可用於移動失配資料之任何記憶體。若不存在任何可用的記憶體,則方法可返回至方塊100。
若存在可用記憶體,則記憶體管理系統18可經由方塊104將資料自所識別項目之記憶體移動至可用記憶體。例如,記憶體管理系統18可使對應於所識別表項目之資料移動至一不同類型的記憶體裝置以移除存取實體記憶體位址之次數與對應於實體記憶體位址之記憶體類型之間的失配。返回至方塊100,若記憶體管理系統18能夠執行一記憶體交換,則記憶體管理系統18可經由方塊106在記憶體裝置之間交換資料。在方塊104或方塊106之後,記憶體管理系統18更新TLB 40及/或XT 54表項目。例如,記憶體管理系統18可使用一虛擬記憶體位址與一實體記憶體位址之間之一經修訂映射、經修訂裝置資料及/或經更新LRU資料來更新TLB 40及/或XT 54。
雖然方塊92至108被描述為藉由記憶體管理系統18執行,但是應注意,記憶體管理系統18之任何部分(例如,硬體及/或軟體)可執行所描述之項。例如,可藉由控制單元56執行方塊92至108之任一者。在某些實施例中,記憶體管理系統18及/或控制單元56可經組態以基於一記憶體類型之持久性或速度動態地改變虛擬記憶體位址至實體記憶體位址之映射。使用本文中描述之技術,記憶體管理系統18可最大化系統10之效能及/或最小化軟體額外耗用。
雖然本發明可具有各種修改及替代形式,但是已在圖式中藉由實例展示且在本文中詳細描述特定實施例。然而,應瞭解,本發明並不旨在限於所揭示之特定形式。實情係,本發明涵蓋落於如藉由下列隨附申請專利範圍定義之本發明之精神及範疇內之所有修改、等效物及替代。
18‧‧‧記憶體管理系統
32‧‧‧虛擬記憶體位址
34‧‧‧實體記憶體位址
36‧‧‧頁錯誤
38‧‧‧轉譯(XLAT)轉譯裝置
40‧‧‧轉譯後備緩衝器(TLB)
Claims (28)
- 一種記憶體管理系統,其包括:一表,其經組態以將一虛擬記憶體位址相關於一實體記憶體位址、相關於存取該實體記憶體位址之頻率之有關的資料且相關於識別包括該實體記憶體位址之一記憶體裝置之一類型之資料;及一控制單元,其經組態以至少部分基於該表而控制該記憶體裝置之操作。
- 如請求項1之記憶體管理系統,其中該表儲存於一轉譯後備緩衝器中。
- 如請求項1之記憶體管理系統,其中該表經組態以將該虛擬記憶體位址相關於與存取該虛擬記憶體位址之頻率有關的資料。
- 如請求項1之記憶體管理系統,其中該表包括儲存於一轉譯裝置中之一記憶體轉譯表。
- 如請求項1之記憶體管理系統,其中該記憶體管理系統經組態以至少基於與存取該實體記憶體位址之頻率有關的該資料而在一記憶體轉譯表與一轉譯後備緩衝器之間移動該虛擬記憶體位址、該實體記憶體位址、存取該實體記憶體位址之頻率之有關的該資料及識別一記憶體裝置之一類型之該資料。
- 一種記憶體管理系統,其包括:一轉譯裝置,其經組態以儲存一第一記憶體轉譯表,其中該第一記憶體轉譯表經組態以映射第一複數個虛擬記憶體位址至第一複數個實體記憶體位址;一轉譯後備緩衝器(TLB),其經組態以儲存一第二記憶體轉譯表,其中該第二記憶體轉譯表經組態以映射第二複數個虛擬記 憶體位址至第二複數個實體記憶體位址,其中該第一記憶體轉譯表及該第二記憶體轉譯表並未重疊;及一控制單元,其經組態以至少部分基於該第一記憶體轉譯表及該第二記憶體轉譯表而控制一記憶體系統之操作,該記憶體系統包括該第一複數個實體記憶體位址或該第二複數個實體記憶體位址中之至少一實體記憶體位址。
- 如請求項6之記憶體管理系統,其中該控制單元經組態以搜尋該第一記憶體轉譯表以識別一第一虛擬記憶體位址。
- 如請求項7之記憶體管理系統,其中該控制單元經組態以獨立於該記憶體管理系統外部之一處理裝置而搜尋該第一記憶體轉譯表。
- 如請求項6之記憶體管理系統,其中該轉譯裝置包括一高效能記憶體陣列。
- 如請求項9之記憶體管理系統,其中該高效能記憶體陣列包括一混合記憶體立方體。
- 如請求項10之記憶體管理系統,其中該混合記憶體立方體經組態以執行該第一記憶體轉譯表之一表查詢。
- 如請求項6之記憶體管理系統,其中該轉譯裝置經組態以將主記憶體提供至一電腦系統。
- 如請求項6之記憶體管理系統,其中該轉譯裝置包括一輔助式搜尋記憶體裝置。
- 如請求項6之記憶體管理系統,其中該TLB包括一內容可定址記憶體。
- 如請求項6之記憶體管理系統,其中該TLB包括一n路關聯記憶體裝置。
- 如請求項6之記憶體管理系統,其中該TLB及該轉譯裝置係併入 一單個裝置內。
- 如請求項6之記憶體管理系統,其中該TLB係併入一第一裝置內且該轉譯裝置係併入一第二裝置內。
- 如請求項6之記憶體管理系統,其中該控制單元經組態以至少部分基於存取該虛擬記憶體位址之頻率之有關的資料而自該第一記憶體轉譯表移動將一虛擬記憶體位址相關於一實體記憶體位址之一表項目自該第一記憶體轉譯表移至該第二記憶體轉譯表。
- 如請求項6之記憶體管理系統,其中該控制單元經組態以同時搜尋該第一記憶體轉譯表及該第二記憶體轉譯表。
- 如請求項6之記憶體管理系統,其中該控制單元經組態以在該第一記憶體轉譯表之前搜尋該第二記憶體轉譯表。
- 如請求項6之記憶體管理系統,其中該控制單元經組態以在該第一記憶體轉譯表或該第二記憶體轉譯表中發現包含一虛擬記憶體位址之一表項目之後停止該第一記憶體轉譯表或該第二記憶體轉譯表中之一搜尋。
- 如請求項6之記憶體管理系統,其中該控制單元經組態以更新該TLB。
- 如請求項6之記憶體管理系統,其中該控制單元經組態以更新該第一記憶體轉譯表或該第二記憶體轉譯表中之最近最少使用(LRU)資料。
- 如請求項8之記憶體管理系統,其中該控制單元經組態以至少部分基於存取該第一實體記憶體位址之頻率之有關的資料、該第一記憶體類型及該第二記憶體類型之有關的資料而將一第一類型之一第一實體記憶體位址中之一第一資料集合移至一第二類型之一第二實體記憶體位址。
- 如請求項6之記憶體管理系統,其中該控制單元經組態以至少部 分基於一第一實體記憶體位址之一記憶體類型、一第二實體記憶體位址之一記憶體類型及存取該第一實體記憶體位址之頻率之有關的資料而動態地改變一第一虛擬記憶體位址之該第一記憶體轉譯表及該第二記憶體轉譯表中自該第一實體記憶體位址至該第二實體記憶體位址之映射。
- 一種電腦系統,其包括:一處理器;及一記憶體管理系統,其包括一轉譯裝置,其中該轉譯裝置包括一控制單元,該控制單元經組態以至少部分基於對應於一第一實體記憶體位址之一第一記憶體類型、對應於一第二實體記憶體位址之一第二記憶體類型及存取一虛擬記憶體位址之頻率之有關的資料而動態地改變該虛擬記憶體位址自該第一實體記憶體位址至該第二實體記憶體位址之映射。
- 如請求項26之系統,其中該記憶體管理系統經組態以基於該第二記憶體類型之一耐久性動態地改變該虛擬記憶體位址至該第二實體記憶體位址之該映射。
- 如請求項26之系統,其中該記憶體管理系統經組態以基於該記憶體類型之一速度動態地改變該虛擬記憶體位址至該第二實體記憶體位址之該映射。
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KR20150036165A (ko) | 2015-04-07 |
EP2875432A1 (en) | 2015-05-27 |
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US20180357177A1 (en) | 2018-12-13 |
CN104487953B (zh) | 2018-04-17 |
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JP2015522886A (ja) | 2015-08-06 |
US9524248B2 (en) | 2016-12-20 |
KR102144491B1 (ko) | 2020-08-18 |
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