TWI512931B - Barrier film formation method and IC chip package - Google Patents

Barrier film formation method and IC chip package Download PDF

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TWI512931B
TWI512931B TW101107648A TW101107648A TWI512931B TW I512931 B TWI512931 B TW I512931B TW 101107648 A TW101107648 A TW 101107648A TW 101107648 A TW101107648 A TW 101107648A TW I512931 B TWI512931 B TW I512931B
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film
barrier film
hole
forming
wafers
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TW201304108A (en
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Michio Ishikawa
Satoru Toyoda
Masanobu Hatanaka
Hirohiko Murakami
Hagane Irikura
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Ulvac Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

阻障膜之形成方法及IC晶片封裝Method for forming barrier film and IC chip package

本發明係關於阻障膜之形成方法及IC晶片封裝,特別是關於利用蒸鍍聚合法而形成阻障膜之方法及具有該阻障膜之IC晶片封裝。The present invention relates to a method for forming a barrier film and an IC chip package, and more particularly to a method for forming a barrier film by an evaporation polymerization method and an IC chip package having the barrier film.

以往,於半導體裝置(IC晶片)之領域中,係使用有一種鋼線結合(wire bonding)的技術,其係在於矽晶圓上製作出裝置之後,用來將裝置與裝置作電連接之技術。然而,隨著將裝置微細化,所連接的鋼線之節距會跟著變窄,而產生連接工程成為困難的問題,此外,因鋼線所致之訊號延遲也成為嚴重的問題。同時,裝置之微細化亦漸漸接近極限,並漸漸到達大容量、高速動作的極限。In the past, in the field of semiconductor devices (IC chips), there is a technique of wire bonding, which is a technique for electrically connecting a device to a device after fabricating a device on a germanium wafer. . However, as the device is miniaturized, the pitch of the connected steel wires is narrowed, and the connection work becomes a difficult problem. In addition, the signal delay due to the steel wire becomes a serious problem. At the same time, the miniaturization of the device is gradually approaching the limit, and gradually reaches the limit of large-capacity, high-speed operation.

因而逐漸開發一種作為該解決法的技術,其係將裝置作重疊、接著,並挖洞,而利用埋入該洞中之由Cu、Al所構成之配線膜來進行連接。例如,於快閃記憶體之領域中,係將重疊有多數片記憶體之大容量快閃記憶體加以局部製品化。將此等技術予以統稱而稱為TSV或是3維安裝。於如前述般之記憶體系中,係有將多數片相同的裝置重疊而爭取容量者,或將記憶體與邏輯電路之類的不同種類之裝置重疊而縮短配線,而以高速動作為目的者等,其組合係因應目的而自由地選擇。Therefore, a technique for this solution has been gradually developed in which the devices are overlapped, and then burrowed, and the wiring film made of Cu or Al buried in the hole is connected. For example, in the field of flash memory, a large-capacity flash memory in which a plurality of pieces of memory are superimposed is partially productized. These technologies are collectively referred to as TSV or 3D installation. In the memory system as described above, a device in which a plurality of identical devices are stacked to obtain a capacity, or a memory device and a different device such as a logic circuit are overlapped to shorten wiring, and a high-speed operation is performed. The combination is freely chosen for the purpose.

於TSV技術中,係可粗略劃分地區分為先通孔工程和 後通孔工程,該先通孔工程,係於IC晶片(或矽晶圓)彼此接著前,開設洞而埋入作為配線膜之Cu膜等;該後通孔工程,係於接著後開設洞而形成Cu膜等。In the TSV technology, the system can be roughly divided into first through hole projects and After the through hole project, the first through hole project is performed before the IC chips (or the germanium wafers) are connected to each other, and a hole is formed to embed a Cu film as a wiring film; the through hole project is followed by opening a hole. A Cu film or the like is formed.

於上述後通孔工程中,係亦含有接著劑並開設洞而將Cu埋入,因此,製程之最高溫度,係取決於接著劑之耐熱性。雖亦因接著劑的種類而異,但一般而言,係以200℃以下較為理想。In the above-mentioned through-hole engineering, the adhesive is also contained and a hole is opened to embed Cu. Therefore, the maximum temperature of the process depends on the heat resistance of the adhesive. Although it varies depending on the type of the adhesive, it is generally preferably 200 ° C or less.

另一方面,該洞的形狀,係為2~20μm左右,且深度50~200μm左右。因此,長寬比(A/R)係達到10~100左右。在這樣的A/R之洞內進行均一地成膜,是以往所使用的濺鍍法所無法達成的,故有以CVD法而進行的必要。On the other hand, the shape of the hole is 2~20μm, and the depth is about 50~200μm. Therefore, the aspect ratio (A/R) is about 10 to 100. Uniform film formation in such a hole of A/R is not possible by the conventional sputtering method, and therefore it is required to be carried out by the CVD method.

此外,至今於半導體裝置製作工程中所使用的阻障膜,係以藉由CVD法所形成之Ti、TiN、Ta及TaN膜為主流(例如,參照專利文獻1),其成膜溫度為高達300℃以上,在利用有以低溫下之實施作為目的的TSV技術之工程中係無法使用。亦即,謀求開發一種利用TSV技術的工程用之新的阻障膜。再者,以往,配線膜係形成在SiO2 膜上,因此,阻障膜係可為導電體。但是,於利用TSV技術之工程中,由於基底係以矽為導體(半導體),因此就阻障膜而言,係亦被要求絕緣性。因而針對材料性,也必須要新穎開發。In addition, the barrier films used in the semiconductor device fabrication process are mainly Ti, TiN, Ta, and TaN films formed by the CVD method (for example, refer to Patent Document 1), and the film formation temperature is as high as possible. At 300 ° C or higher, it cannot be used in a project using a TSV technology which is intended to be carried out at a low temperature. That is, it is seeking to develop a new barrier film for engineering using TSV technology. Further, conventionally, the wiring film is formed on the SiO 2 film, and therefore, the barrier film can be a conductor. However, in the engineering using the TSV technology, since the base is made of a conductor (semiconductor), the barrier film is also required to have insulation properties. Therefore, for material properties, it must also be developed.

一般,依據眾所周知的方法,將Cu膜作為配線膜,藉由CVD法而形成於上述阻障膜之上(例如,參照專利文 獻2)。Generally, a Cu film is formed as a wiring film by a CVD method on the above barrier film according to a well-known method (for example, refer to the patent document) Offer 2).

另外,如上所述般,於先前技術中,一般,以藉由濺鍍法或CVD法而形成金屬或金屬氮化物之膜,作為Cu或Al等之配線膜的阻障膜。特別是若A/R提高(例如,5以上),則必須使用CVD法。因而,由於使用有機金屬材料或者是金屬之氯化物或氟化物作為阻障膜原料,故一般而言,其成膜溫度係為300℃以上。於有機金屬材料之情況,係為了將有機物分解而去除,必須要由高溫所致之熱能。此外,於金屬之氯化物或氟化物之情況,雖一般反應溫度係為低,但為了將氯或氟從膜中去除,而必須要高溫。又,於先前技術中,為了防止由金屬等所構成的阻障膜表面之氧化,而必須要在阻障膜形成後,在真空中連續地將Al或Cu等予以成膜。Further, as described above, in the prior art, a film of a metal or a metal nitride is generally formed by a sputtering method or a CVD method, and is used as a barrier film of a wiring film of Cu or Al. In particular, if the A/R is increased (for example, 5 or more), the CVD method must be used. Therefore, since an organic metal material or a metal chloride or fluoride is used as a barrier film material, the film formation temperature is generally 300 ° C or higher. In the case of an organometallic material, in order to decompose and remove the organic matter, heat energy due to high temperature is required. Further, in the case of a metal chloride or a fluoride, although the reaction temperature is generally low, in order to remove chlorine or fluorine from the film, high temperature is required. Further, in the prior art, in order to prevent oxidation of the surface of the barrier film made of metal or the like, it is necessary to continuously form Al or Cu or the like in a vacuum after the formation of the barrier film.

[先前技術文獻][Previous Technical Literature] [專利文獻][Patent Literature]

[專利文獻1]國際公開第2010/007991號手冊[Patent Document 1] International Publication No. 2010/007991

[專利文獻2]日本特開2009-081431號公報[Patent Document 2] Japanese Patent Laid-Open Publication No. 2009-081431

本發明之課題係在於解決上述之先前技術的問題點,而提供一種藉由利用所謂蒸鍍聚合法,而形成在低溫下絕緣特性、阻障特性、孔內之均一成膜特性優異的阻障膜之方法,及具備有該阻障膜之IC晶片封裝;該蒸鍍聚合 法,係在真空中將2種之單體同時或者是分別進行蒸鍍,使其在基板上反應,其後因應需要而進行加熱,並藉由聚合反應而得到所期望的膜。An object of the present invention is to solve the above problems of the prior art, and to provide a barrier which is excellent in insulating properties, barrier properties, and uniform film forming properties in a hole by a so-called vapor deposition polymerization method. Film method, and IC chip package having the barrier film; the vapor deposition polymerization In the method, two kinds of monomers are simultaneously vapor-deposited in a vacuum to be reacted on a substrate, and then heated as needed, and a desired film is obtained by a polymerization reaction.

關於本發明之阻障膜之形成方法的第1形成方法之發明,係將複數片形成有IC晶片的矽晶圓作堆積、接合,並藉由TSV技術,而於該被接合的矽晶圓上開設用以將IC晶片彼此電連接之洞,之後,在將複數片IC晶片作串連並在該洞中形成導電體膜之前,於該洞中形成阻障膜之方法,其特徵為:使2種以上之單體在真空中蒸發,並藉由蒸鍍聚合法,而在該洞中形成由聚醯亞胺所構成之阻障膜。The invention of the first method for forming a barrier film of the present invention is to deposit and bond a plurality of germanium wafers on which an IC wafer is formed, and to bond the germanium wafer by TSV technology. A method for electrically connecting the IC chips to each other, and then forming a barrier film in the hole before the plurality of IC chips are connected in series and forming a conductor film in the hole is characterized by: Two or more kinds of monomers are evaporated in a vacuum, and a barrier film composed of polyimine is formed in the hole by an evaporation polymerization method.

於上述第1形成方法之發明中,使該單體同時或者是分別蒸發而蒸鍍。In the invention of the first aspect of the invention, the monomers are vaporized simultaneously or separately.

於上述第1形成方法之發明中,該單體,係由芳香族二胺與四羧酸二酐所構成者。In the invention of the first formation method, the monomer is composed of an aromatic diamine and a tetracarboxylic dianhydride.

關於本發明之阻障膜之形成方法的第2形成方法之發明,係將複數片形成有IC晶片的矽晶圓作堆積、接合,並藉由TSV技術,而於該被接合的矽晶圓上開設用以將IC晶片彼此電連接之洞,之後,在將複數片IC晶片作串連並在該洞中形成導電體膜之前,於該洞中形成阻障膜之方法,其特徵為:使2種以上之單體在真空中蒸發,並藉由蒸鍍聚合法,而在該洞中形成由聚合物所構成之阻障 膜。The invention of the second method for forming a barrier film of the present invention is to deposit and bond a plurality of wafers on which an IC wafer is formed, and to bond the germanium wafer by TSV technology. A method for electrically connecting the IC chips to each other, and then forming a barrier film in the hole before the plurality of IC chips are connected in series and forming a conductor film in the hole is characterized by: Two or more kinds of monomers are evaporated in a vacuum, and a barrier formed of a polymer is formed in the hole by an evaporation polymerization method. membrane.

於上述第2形成方法之發明中,使該單體同時或者是分別蒸發而蒸鍍。In the invention of the second formation method described above, the monomers are vaporized simultaneously or separately.

於上述第2形成方法之發明中,該聚合物為聚醯亞胺。In the invention of the second formation method described above, the polymer is a polyimine.

於上述第2形成方法之發明中,該單體,係由芳香族二胺與四羧酸二酐所構成者。In the invention of the second formation method, the monomer is composed of an aromatic diamine and a tetracarboxylic dianhydride.

關於本發明之IC晶片封裝的第1 IC晶片封裝之發明,係具有將分別形成有IC晶片的複數片矽晶圓之各矽晶圓作堆積、接合的矽晶圓層積物之IC晶片封裝,其特徵為:於該矽晶圓層積物上,係於接合後設置藉由TSV技術所開設的洞,於該洞中,係形成有使用2種以上之單體並加以蒸鍍聚合而成之由聚醯亞胺所構成的阻障膜,接著於該阻障膜上形成有導電體膜。The invention of the first IC chip package of the IC chip package of the present invention is an IC chip package having a germanium wafer laminate in which a plurality of wafers of a plurality of wafers each having an IC wafer are formed and stacked. It is characterized in that a hole opened by the TSV technology is provided on the tantalum wafer laminate, and two or more kinds of monomers are formed and vapor-deposited in the hole. A barrier film composed of polyimine is formed, and then a conductor film is formed on the barrier film.

於上述第1 IC晶片封裝之發明中,該單體,係由芳香族二胺與四羧酸二酐所構成者。In the invention of the first IC chip package, the monomer is composed of an aromatic diamine and a tetracarboxylic dianhydride.

關於本發明之IC晶片封裝的第2 IC晶片封裝之發明,係具有將分別形成有IC晶片的複數片矽晶圓之各矽晶圓作堆積、接合的矽晶圓層積物之IC晶片封裝,其特徵為:於該矽晶圓層積物上,係於接合後設置藉由TSV技術所開設的洞,於該洞中,係形成有由蒸鍍聚合而成之聚合物所構成的阻障膜,接著於該阻障膜上形成有導電體膜。The invention of the second IC chip package of the IC chip package of the present invention is an IC chip package having a germanium wafer laminate in which a plurality of wafers of a plurality of wafers each having an IC wafer are formed and stacked. The feature is that a hole formed by the TSV technology is disposed on the germanium wafer laminate, and a hole formed by vapor deposition polymerization is formed in the hole. A barrier film is then formed on the barrier film with a conductive film.

於上述第2 IC晶片封裝之發明中,該聚合物為聚醯 亞胺。In the invention of the second IC chip package, the polymer is a polyfluorene Imine.

於上述第2 IC晶片封裝之發明中,該單體,係芳香族二胺與四羧酸二酐之蒸鍍聚合物。In the invention of the second IC chip package, the monomer is a vapor deposition polymer of an aromatic diamine and a tetracarboxylic dianhydride.

依據本發明而達成下述效果:可於適用TSV技術而開設的洞內,藉由蒸鍍聚合法而能在250℃以下成膜,並且即使A/R為10以上也充分展現電鍍能力(throwing power),而形成能作為阻障膜而充分使用的阻障膜。According to the present invention, it is possible to form a film at 250 ° C or lower by a vapor deposition polymerization method in a hole opened by a TSV technique, and to sufficiently exhibit plating ability even when A/R is 10 or more (throwing) Power), forming a barrier film that can be fully used as a barrier film.

此外,依據本發明而達成下述效果:具備有上述阻障膜之IC晶片封裝,係不會有訊號延遲的問題產生之疑慮,此外,大容量、高速動作亦為可能。Further, according to the present invention, the IC chip package including the barrier film described above has the problem that the signal delay does not occur, and large-capacity and high-speed operation is also possible.

以下,針對本發明之阻障膜之形成方法的實施形態及IC晶片封裝之實施形態進行說明,並於其後,針對各構成要件進行詳細地說明。Hereinafter, an embodiment of a method for forming a barrier film of the present invention and an embodiment of an IC chip package will be described, and each constituent element will be described in detail later.

依據本發明之阻障膜之形成方法的實施形態,該形成方法,係將於矽晶圓表面上形成有IC晶片(IC裝置)的複數片矽晶圓,以使未形成有IC晶片的矽晶圓之背面側與形成有IC晶片的其他矽晶圓之表面側接觸的方式作堆積,並使用由例如矽氧烷樹脂或環氧樹脂等所選出之接著劑而接合,且藉由3維安裝工程(TSV技術、工程),而於該被接合的矽晶圓層積物上,開設用以將IC晶片彼此電 連接的洞,之後,於將串連複數片IC晶片之由Cu、Al、W或Ni等所構成的導電體膜形成於洞內或洞的周邊之前,在洞內或其周邊形成阻障膜之方法,其係使2種以上之單體,較理想為使芳香族二胺與四羧酸二酐,在真空中蒸發,並例如使各單體同時蒸發或者是將時間錯開而分別蒸發,並在洞內或其周邊蒸鍍聚合,而形成以較理想為由聚醯亞胺等之聚合物所構成之阻障膜而成。於本說明書中,稱為「洞內」之情況,係設為包含洞內與其周邊者。此時,於洞的周邊所形成的膜,係因應作為目標的裝置而進行蝕刻去除。According to an embodiment of the method for forming a barrier film of the present invention, the formation method is to form a plurality of wafers of an IC wafer (IC device) on a surface of a germanium wafer so that an IC wafer is not formed. The back side of the wafer is deposited in contact with the surface side of the other germanium wafer on which the IC wafer is formed, and bonded using an adhesive selected from, for example, a decane resin or an epoxy resin, and is bonded by 3D. Installation engineering (TSV technology, engineering), and on the bonded germanium wafer laminate, to open the IC wafers to each other a hole to be connected, and then a barrier film is formed in or around the hole before forming a conductor film made of Cu, Al, W, or Ni in a plurality of IC chips in series in a hole or a periphery thereof The method comprises two or more monomers, preferably an aromatic diamine and a tetracarboxylic dianhydride, which are evaporated in a vacuum, and e.g., each monomer is simultaneously evaporated or the time is shifted and evaporated separately. Further, it is formed by vapor deposition polymerization in or around the hole to form a barrier film composed of a polymer such as polyimide or the like. In the present specification, the case of "inside the hole" is set to include the inside of the hole and its surroundings. At this time, the film formed around the hole is etched and removed in response to the target device.

此外,依據本發明之IC晶片封裝的實施形態,該IC晶片封裝,係具有將分別形成有IC晶片的複數片矽晶圓之各矽晶圓,以使未形成有IC晶片的矽晶圓之背面側與形成有IC晶片的其他矽晶圓的表面側接觸的方式作堆積,並藉由由例如矽氧烷樹脂或環氧樹脂等所選出之接著劑而接合的矽晶圓層積物,且於該矽晶圓層積物上,係在接合後設置藉由TSV技術所開設的洞,於洞內或其周邊,係形成有使用2種以上之單體,較理想為將芳香族二胺與四羧酸二酐蒸鍍聚合而成之由聚醯亞胺等之聚合物所構成的阻障膜,接著於該阻障膜上,係形成有由Cu、Al、W或Ni等所構成之導電體膜而成。In addition, according to the embodiment of the IC chip package of the present invention, the IC chip package has respective wafers of a plurality of wafers on which IC chips are respectively formed, so that the silicon wafers on which the IC wafers are not formed are formed. The back side is deposited in such a manner as to be in contact with the surface side of the other tantalum wafer on which the IC wafer is formed, and the tantalum wafer laminate is bonded by an adhesive selected from, for example, a siloxane resin or an epoxy resin. On the enamel wafer laminate, a hole opened by TSV technology is provided after bonding, and two or more kinds of monomers are formed in or around the hole, and it is preferable to use an aromatic two. a barrier film made of a polymer such as polytheneimide obtained by vapor-depositing an amine and a tetracarboxylic dianhydride, and then formed on the barrier film by Cu, Al, W or Ni. It is made up of a conductive film.

於先前技術中,係如上所述般,藉由濺鍍法或CVD法而形成金屬或金屬氮化物,作為配線膜之阻障膜。特別是若A/R提高(例如,5以上),則必須使用CVD法。因 而,其成膜溫度,係必須要由300℃以上之高溫所致的熱能,此外,為了將來自所使用的原料之氯或氟從膜中去除而必須要高溫。再者,於先前技術中,為了防止含有金屬的阻障膜之表面的氧化,而必須於阻障膜形成後,在真空中連續地形成配線膜。In the prior art, as described above, a metal or a metal nitride is formed by a sputtering method or a CVD method as a barrier film for a wiring film. In particular, if the A/R is increased (for example, 5 or more), the CVD method must be used. because Further, the film forming temperature is required to be caused by heat of 300 ° C or higher, and in addition, high temperature is required in order to remove chlorine or fluorine from the raw material used from the film. Further, in the prior art, in order to prevent oxidation of the surface of the metal-containing barrier film, it is necessary to continuously form a wiring film in a vacuum after the barrier film is formed.

但,依據上述之本發明,由於阻障膜係由有機物所構成之聚合物膜,因此成膜溫度亦較低,且亦能夠在形成聚合物膜之後,將所得到之矽晶圓暫時取出於大氣中,再進行接下來的工程。However, according to the present invention as described above, since the barrier film is a polymer film composed of an organic material, the film formation temperature is also low, and the obtained silicon wafer can be temporarily taken out after the formation of the polymer film. In the atmosphere, the next project will be carried out.

此外,本發明之情況,當退火處理為必需的情況時,係亦可於退火後,進行Al、Cu等之成膜。Further, in the case of the present invention, when annealing treatment is necessary, it is also possible to form a film of Al, Cu or the like after annealing.

再者,為了提昇Al或Cu膜等對於阻障膜之密著性,能夠在聚醯亞胺成膜前或成膜中,或是於Al或Cu等之成膜前(退火後),添加所期望之量的下述矽烷偶合劑,例如,於成膜中添加的情況下,係相對於聚醯亞胺1mol添加0.01~0.1mol左右,此外,於成膜前添加的情況下,係微量添加如10分子層程度。Further, in order to improve the adhesion of the Al or Cu film to the barrier film, it may be added before or during film formation of the polyimide or before or after the film formation of Al or Cu (after annealing). The amount of the following decane coupling agent to be added is, for example, about 0.01 to 0.1 mol based on 1 mol of the polyimine, and is added in a small amount to the polyimine. Add a degree such as 10 molecular layers.

就構成可依據本發明而形成之阻障膜的聚合物而言,係可列舉例如:聚醯亞胺、聚醯胺、聚甲亞胺、聚脲或此等之任意的混合物等,較理想係可列舉聚醯亞胺。The polymer constituting the barrier film which can be formed according to the present invention may, for example, be a polyimine, a polyamine, a polymethylenimine, a polyurea or a mixture of any of these, and the like. A polyimine can be cited.

就作為可形成上述聚醯亞胺之其中一者的單體之芳香族二胺而言,係可使用由例如:4,4’-二苯基醚、1,4-二胺苯、1,3-二胺苯、2,4-二胺基甲苯、4,4’-二胺基二苯甲烷、3,4’-二胺基二苯基醚、3,3’-二甲基-4,4’-二胺基聯 苯、2,2’-二甲基-4,4’-二胺基聯苯、2,2’-雙(三氟甲基)-4,4’-二胺基聯苯、3,7-二胺基-二甲基二苯并噻吩-5,5-二氧化物、4,4’-二胺基二苯基酮(benzophenone)、3’,3’-二胺基二苯基酮、4,4’-雙(4-胺基苯基)硫化物、4,4’-二胺基二苯碸、4,4’-二胺基苯甲醯苯胺、1,n-雙(4-胺基苯氧基)烷、1,3-雙(4-胺基苯氧基)-2,2-二甲基丙烷、1,2-雙[2-(4-胺基苯氧基)乙氧基]乙烷、9,9-雙(4-胺基苯基)茀、5(6)-胺基-1-(4-胺基甲基)-3,3,3-三甲基茚滿、1,4-雙(4-胺基苯氧基)苯、1,3-雙(4-胺基苯氧基)苯、1,3-雙(3-胺基苯氧基)苯、4,4’-雙(4-胺基苯氧基)聯苯、4,4’-雙(3-胺基苯氧基)聯苯、2,2-雙(4-胺基苯氧基苯基)丙烷、雙[4-(4-胺基苯氧基)苯基]碸、雙[4-(3-胺基苯氧基)苯基]碸、2,2-雙[4-(4-胺基苯氧基)苯基]六氟丙烷、3,3’-二羧酸-4,4’-二胺基二苯甲烷、4,6-二羥基-1,3-二苯胺、3,3’-羥基-4,4’-二胺基聯苯、3,3’,4,4’-四胺基聯苯、1-胺基-3-胺基甲基-3,5,5-三甲基環己烷、及1,3-雙(3-胺基丙基)-1,1,3,3-四甲基二矽氧烷等所選出之至少1種。As the aromatic diamine which is a monomer which can form one of the above polyimines, for example, 4,4'-diphenyl ether, 1,4-diamine benzene, 1, can be used. 3-diamine benzene, 2,4-diaminotoluene, 4,4'-diaminodiphenylmethane, 3,4'-diaminodiphenyl ether, 3,3'-dimethyl-4 , 4'-diamine linkage Benzene, 2,2'-dimethyl-4,4'-diaminobiphenyl, 2,2'-bis(trifluoromethyl)-4,4'-diaminobiphenyl, 3,7- Diamino-dimethyldibenzothiophene-5,5-dioxide, 4,4'-diaminodiphenyl benzophenone, 3',3'-diaminodiphenyl ketone, 4,4'-bis(4-aminophenyl) sulfide, 4,4'-diaminodiphenyl hydrazine, 4,4'-diaminobenzimidamide, 1,n-bis(4- Aminophenoxy)alkane, 1,3-bis(4-aminophenoxy)-2,2-dimethylpropane, 1,2-bis[2-(4-aminophenoxy)B Oxy]ethane, 9,9-bis(4-aminophenyl)anthracene, 5(6)-amino-1-(4-aminomethyl)-3,3,3-trimethylhydrazine Full, 1,4-bis(4-aminophenoxy)benzene, 1,3-bis(4-aminophenoxy)benzene, 1,3-bis(3-aminophenoxy)benzene, 4,4'-bis(4-aminophenoxy)biphenyl, 4,4'-bis(3-aminophenoxy)biphenyl, 2,2-bis(4-aminophenoxybenzene) Propane, bis[4-(4-aminophenoxy)phenyl]anthracene, bis[4-(3-aminophenoxy)phenyl]anthracene, 2,2-bis[4-(4 -aminophenoxy)phenyl]hexafluoropropane, 3,3'-dicarboxylic acid-4,4'-diaminodiphenylmethane, 4,6-dihydroxy-1,3-diphenylamine, 3 , 3'-hydroxy-4,4'-diamino Benzene, 3,3',4,4'-tetraaminobiphenyl, 1-amino-3-aminomethyl-3,5,5-trimethylcyclohexane, and 1,3-double ( At least one selected from the group consisting of 3-aminopropyl)-1,1,3,3-tetramethyldioxane.

此外,就作為可形成聚醯亞胺之另一種的單體之四羧酸二酐而言,係可使用由例如:苯均四酸二酐、氧代二鄰苯二甲酸二酐、聯苯-3,4,3’,4’-四羧酸二酐、二苯基酮-3,4,3’,4’-四羧酸二酐、二苯碸-3,4,3’,4’-四羧酸二酐、4,4’-(2,2-六氟異丙烯)二鄰苯二甲酸二酐、m(p)-三苯-3,4,3’,4’-四羧酸二酐、環丁烷1,2,3,4-四羧酸二酐、及1-羧甲基-2,3,5-環戊烷三羧酸-2,6:3,5-二酐等所選出之至少 1種。Further, as the tetracarboxylic dianhydride which is another monomer which can form a polyimine, for example, pyromellitic dianhydride, oxydiphthalic dianhydride, biphenyl can be used. -3,4,3',4'-tetracarboxylic dianhydride, diphenyl ketone-3,4,3',4'-tetracarboxylic dianhydride, diphenyl hydrazine-3,4,3',4 '-tetracarboxylic dianhydride, 4,4'-(2,2-hexafluoroisopropene) diphthalic dianhydride, m(p)-triphenyl-3,4,3',4'-four Carboxylic dianhydride, cyclobutane 1,2,3,4-tetracarboxylic dianhydride, and 1-carboxymethyl-2,3,5-cyclopentanetricarboxylic acid-2,6:3,5- The dianhydride and the like are selected at least 1 species.

於上述本發明之蒸鍍聚合的情況,係與一般之藉由溶液聚合法(例如使用二甲基甲醯胺等作為溶劑)來進行溶液聚合而得到聚醯胺酸(polyamide acid)溶液,接著去除溶劑,並進行脫水閉環而得到聚醯亞胺膜的方法之情況相同,只要由可在上述所例示的溶液聚合法中所一般使用之芳香族二胺及四羧酸二酐中適當選擇而使用,同樣地可得到經蒸鍍聚合而成之聚醯亞胺膜。In the case of the vapor deposition polymerization of the present invention described above, a solution polymerization method (for example, using dimethylformamide or the like as a solvent) is carried out to obtain a polyamic acid solution, followed by a solution of a polyamic acid solution. The method of removing the solvent and performing dehydration ring closure to obtain a polyimide film is the same as long as it is appropriately selected from the aromatic diamine and the tetracarboxylic dianhydride which can be generally used in the solution polymerization method exemplified above. Similarly, a polyimine film obtained by vapor deposition polymerization can be obtained.

作為上述之矽烷偶合劑,係已知有於分子內同時具有與有機材料進行反應鍵結之官能基,及與無機材料進行反應鍵結之官能基的有機矽化合物,且具有次式之結構者等。As the above-described decane coupling agent, an organic ruthenium compound having a functional group reactively bonded to an organic material and a functional group bonded to an inorganic material in a molecule, and having a structure of a secondary formula is known. Wait.

Z-R-Si-(X)2 ZR-Si-(X) 2

上述式中,Z係與有機材料進行反應鍵結之官能基,且為例如:乙烯基、環氧基、胺基、甲基丙烯酸基(methacryl)、或硫醇基等,而X係與無機材料進行反應之官能基或鹵素原子,且為例如由甲氧基及乙氧基等所選出之烷氧基、乙醯氧基、苯氧基、或氯原子等。In the above formula, Z is a functional group reactively bonded to an organic material, and is, for example, a vinyl group, an epoxy group, an amine group, a methacryl group, or a thiol group, and the X system and the inorganic group. The functional group or halogen atom in which the material is reacted, and is, for example, an alkoxy group selected from a methoxy group, an ethoxy group or the like, an ethoxy group, a phenoxy group, or a chlorine atom.

如上所述,為了提昇由Al膜或Cu膜等所構成之配線膜對於阻障膜之密著性,亦可依據已知的方法,以特定的順序且添加特定量的矽烷偶合劑,係可列舉如下所述者。As described above, in order to improve the adhesion of the wiring film composed of the Al film or the Cu film to the barrier film, a specific amount of the decane coupling agent may be added in a specific order according to a known method. Listed below.

例如:除了3-胺基丙基三甲氧矽烷、3-胺基丙基三乙 氧矽烷、3-(2-胺基乙基)胺基丙基三甲氧矽烷、3-(2-胺基乙基)胺基丙基三甲氧矽烷、3-苯基胺基丙基三甲氧矽烷、1,2-乙烷二胺(ethanediamine)、N-{3-(三甲氧基矽烷基)丙基}-、N-{(乙烯基苯基)甲基}衍生物.鹽酸鹽40%甲醇溶液、3-縮水甘油氧丙基三甲氧矽烷、3-縮水甘油氧丙基甲基二甲氧矽烷、3-縮水甘油氧丙基甲基二乙氧矽烷、2-(3,4-環氧環己基)乙基三甲氧矽烷、乙烯基三乙醯氧矽烷、乙烯基三甲氧矽烷、乙烯基三乙氧矽烷、丙烯基三甲氧矽烷、3-甲基丙烯醯氧丙基三甲氧矽烷、3-甲基丙烯醯氧丙基甲基二甲氧矽烷、3-硫醇丙基三甲氧矽烷、3-硫醇丙基甲基二甲氧矽烷、3-硫醇丙基三乙氧矽烷、胺基矽烷(甲醇溶液)、胺基矽烷混合物、及胺基矽烷(IPA溶液)之外,可使用由作為烷基烷氧矽烷之甲基三甲氧矽烷、二甲基二甲氧矽烷、三甲基甲氧矽烷甲氧基、甲基三乙氧矽烷乙氧基、甲基三苯氧矽烷、乙基三甲氧矽烷、n-丙基三甲氧矽烷、二異丙基二甲氧矽烷、異丁基三甲氧矽烷、二異丁基二甲氧矽烷、異丁基三乙氧矽烷、n-己基三甲氧矽烷、n-己基三乙氧矽烷、環己基甲基二甲氧矽烷、n-辛基三乙氧矽烷、n-癸基三甲氧矽烷、及苯基三甲氧矽烷,作為烷氯矽烷之甲基三氯矽烷、二甲基二氯矽烷、三甲基氯矽烷、及n-辛基二甲基氯矽烷、四乙氧矽烷及1,1,1,3,3,3-六甲基二矽胺烷,以及作為寡聚物之甲基甲氧基矽氧烷、甲基甲氧基矽氧烷、二甲基-苯基甲氧基矽氧烷、二乙基-苯基甲氧基矽氧烷、及烷基烷氧矽氧烷等所選出之至少1種。For example: except 3-aminopropyltrimethoxydecane, 3-aminopropyltriethyl Oxy decane, 3-(2-aminoethyl)aminopropyltrimethoxy decane, 3-(2-aminoethyl)aminopropyltrimethoxy decane, 3-phenylaminopropyltrimethoxy decane 1,2-ethanediamine, N-{3-(trimethoxydecyl)propyl}-, N-{(vinylphenyl)methyl} derivative. Hydrochloride 40% Methanol solution, 3-glycidoxypropyltrimethoxysilane, 3-glycidoxypropylmethyldimethoxydecane, 3-glycidoxypropylmethyldiethoxydecane, 2-(3,4-ring Oxycyclohexyl)ethyltrimethoxy decane, vinyltriethoxy decane, vinyl trimethoxy decane, vinyl triethoxy decane, propylene trimethoxy decane, 3-methyl propylene oxypropyl trimethoxy decane, 3-methacryloyloxypropylmethyldimethoxydecane, 3-thiolpropyltrimethoxyoxane, 3-thiolpropylmethyldimethoxydecane, 3-thiolpropyltriethoxydecane, In addition to amino decane (methanol solution), amino decane mixture, and amino decane (IPA solution), methyl trimethoxy decane, dimethyl dimethoxy decane, and trimethyl methoxide can be used. Methoxy methoxy methoxy, methyl triethoxy Alkenyloxy, methyltriphenyloxane, ethyltrimethoxydecane, n-propyltrimethoxydecane, diisopropyldimethoxydecane, isobutyltrimethoxydecane, diisobutyldimethoxydecane , isobutyl triethoxy decane, n-hexyl trimethoxy decane, n-hexyl triethoxy decane, cyclohexyl methyl dimethoxy decane, n-octyl triethoxy decane, n-decyl trimethoxy decane, And phenyltrimethoxy decane, as methyl chlorodecane, dimethyl dichloro decane, trimethyl chloro decane, and n-octyl dimethyl chloro decane, tetraethoxy decane and 1, 1 , 1,3,3,3-hexamethyldioxane, and methyl methoxy siloxane as an oligomer, methyl methoxy decane, dimethyl-phenyl methoxy At least one selected from the group consisting of decane, diethyl-phenylmethoxy methoxy oxane, and alkyl alkoxy oxane.

上述矽烷偶合劑,係只要藉由眾所周知的方法(例如,日本特開2006-231134號公報),而於聚醯亞胺成膜前或成膜中,或於Al或Cu等之成膜前(退火後),添加所期望之量即可。The above decane coupling agent is prepared by a well-known method (for example, JP-A-2006-231134) before or during film formation of a polyimide or before film formation of Al or Cu or the like ( After annealing, the desired amount may be added.

其次,針對用以實施本發明之阻障膜之形成方法的成膜裝置,參照將一模式性構造例作展示的第1圖進行說明。Next, a film forming apparatus for carrying out the method for forming a barrier film of the present invention will be described with reference to a first drawing which shows a schematic structural example.

第1圖所示之成膜裝置1,係具有可載置被處理基板S之真空槽11,且該真空槽11,係具備有用以使真空槽內減壓的排氣系統12。於真空槽11內,係配置有第一原料單體(A)用之鎢舟皿13a及第二原料單體(B)用之鎢舟皿13b,且於鎢舟皿13a及鎢舟皿13b之上部,係分別設置有閘門14a及14b。被處理基板S,係被載置並固定於托架15上,並將其處理表面,以使與第一及第二原料單體(A及B)相對向的方式,設置於真空槽11的上方。此外,雖未予以圖示,但鎢舟皿13a及13b,係具備有用來使固體或液體之原料單體產生蒸氣的加熱手段。The film forming apparatus 1 shown in Fig. 1 has a vacuum chamber 11 on which a substrate S to be processed is placed, and the vacuum chamber 11 is provided with an exhaust system 12 for decompressing the inside of the vacuum chamber. In the vacuum chamber 11, a tungsten boat 13a for the first raw material monomer (A) and a tungsten boat 13b for the second raw material monomer (B) are disposed, and the tungsten boat 13a and the tungsten boat 13b are disposed. Upper portions are provided with shutters 14a and 14b, respectively. The substrate S to be processed is placed and fixed on the carrier 15, and the surface is treated to be disposed in the vacuum chamber 11 so as to face the first and second raw material monomers (A and B). Above. Further, although not shown, the tungsten boat 13a and 13b are provided with heating means for generating a vapor of a raw material of a solid or a liquid.

另外,在第一及第二原料單體(A及B)於室溫下為固體的情況下,雖予以未圖示,但以於鎢舟皿13a及13b上分別安裝有用來將單體之蒸發量調整成相同的狹縫板者較為理想。Further, when the first and second raw material monomers (A and B) are solid at room temperature, although not shown, the tungsten boat 13a and 13b are respectively provided with a monomer for mounting. It is preferable that the evaporation amount is adjusted to the same slit plate.

在使用上述之成膜裝置1而形成阻障膜的情況下,例如,首先,使用矽氧烷樹脂或環氧樹脂等之接著劑,來將於表面形成有第1半導體元件區域(IC晶片)的第1矽晶圓 之表面側,與於表面形成有第2半導體元件區域(IC晶片)的第2矽晶圓之背面側作接合。藉由TSV技術,並以乾蝕刻來在特定的製程條件下,對於如此所得之矽晶圓層積物,開設將形成於第2矽晶圓上的第2半導體元件區域與形成於第1矽晶圓上的第1半導體元件區域作電連接的洞。使用開設有洞的矽晶圓層積物,作為本發明之被處理基板S。In the case where the barrier film is formed by using the above-described film forming apparatus 1, for example, first, a first semiconductor element region (IC wafer) is formed on the surface by using an adhesive such as a decane resin or an epoxy resin. First wafer The front side is joined to the back side of the second silicon wafer on which the second semiconductor element region (IC wafer) is formed. The second semiconductor element region to be formed on the second germanium wafer is formed on the second germanium wafer by the TSV technology and dry etching to form the second semiconductor device layer formed on the second germanium wafer under specific process conditions. A hole in the first semiconductor element region on the wafer is electrically connected. A tantalum wafer laminate having a hole is used as the substrate S to be processed of the present invention.

針對由該TSV技術所進行之蝕刻,參照將由具有第1矽晶圓及第2矽晶圓之矽晶圓層積物所構成之IC晶片封裝之一模式性構造例作展示的第2圖進行說明。For the etching by the TSV technology, reference is made to FIG. 2 showing a schematic structure example of an IC chip package including a germanium wafer laminate having a first germanium wafer and a second germanium wafer. Description.

第2圖所示之IC晶片封裝2,係將第1矽晶圓21之表面側與第2矽晶圓22之背面側,透過由矽氧烷樹脂或環氧樹脂等所構成之接著劑層23,而作層積者。於第1矽晶圓21之表層的一部分,係藉由眾所周知的方法而形成有第1半導體元件區域(IC晶片)21a,此外,於第2矽晶圓22之表層的一部分,係藉由眾所周知的方法而形成有第2半導體元件區域(IC晶片)22a。此外,於第1矽晶圓21與接著劑層23之間,係設置有絕緣層24,且於第2矽晶圓22與接著劑層23之間,係設置有絕緣層25。藉由TSV技術,並在特定之乾蝕刻條件下,對於矽晶圓層積物,開設將形成於第2矽晶圓22上的第2 IC晶片22a與形成於第1矽晶圓21上的第1 IC晶片21a作電連接的洞。於如此所得之洞中及其周邊,如上所述般,使用2種以上之單體,較理想為芳香族二胺與四羧酸二酐,並藉由 蒸鍍聚合而形成由聚醯亞胺等之聚合物所構成之阻障膜26。然後,將該阻障膜26之洞(孔)的底部進行蝕刻去除,其後於阻障膜26及所露出的第1半導體元件區域21a之上,形成由Cu、Al、W或Ni等所構成之導電體膜27。如此一來便得到本發明之IC晶片封裝2。The IC chip package 2 shown in FIG. 2 passes through the surface layer side of the first silicon wafer 21 and the back surface side of the second silicon wafer 22 through an adhesive layer made of a siloxane resin or an epoxy resin. 23, and as a strategist. A part of the surface layer of the first wafer 21 is formed by a well-known method in which a first semiconductor element region (IC wafer) 21a is formed, and a part of the surface layer of the second wafer 22 is known. The second semiconductor element region (IC wafer) 22a is formed by the method. Further, an insulating layer 24 is provided between the first silicon wafer 21 and the adhesive layer 23, and an insulating layer 25 is provided between the second germanium wafer 22 and the adhesive layer 23. The second IC wafer 22a to be formed on the second germanium wafer 22 and the first germanium wafer 21 are formed for the germanium wafer laminate by the TSV technology and under specific dry etching conditions. The first IC chip 21a is a hole for electrical connection. In the hole thus obtained and its periphery, as described above, two or more kinds of monomers are used, and more preferably an aromatic diamine and a tetracarboxylic dianhydride are used. The barrier film 26 composed of a polymer such as polyimide or the like is formed by vapor deposition polymerization. Then, the bottom of the hole (hole) of the barrier film 26 is removed by etching, and then formed on the barrier film 26 and the exposed first semiconductor element region 21a by Cu, Al, W, or Ni. The conductor film 27 is formed. Thus, the IC chip package 2 of the present invention is obtained.

上述乾蝕刻,係例如,隔著於第2矽晶圓22上所設置的SiN硬遮罩(例如,厚度0.5μm)而進行。亦即,依序對第2 IC晶片22a、第2矽晶圓22、絕緣層25、接著劑層23、及絕緣層24進行蝕刻,且蝕刻至第1 IC晶片21a之上為止,而開設上述連接洞。The dry etching is performed, for example, via a SiN hard mask (for example, a thickness of 0.5 μm) provided on the second silicon wafer 22. In other words, the second IC wafer 22a, the second silicon wafer 22, the insulating layer 25, the adhesive layer 23, and the insulating layer 24 are sequentially etched and etched onto the first IC wafer 21a. Connect the hole.

上述遮罩之蝕刻工程,係例如,將真空槽內之壓力設定為0.67Pa,且在180/20/10sccm之流量下讓Ar/C4 F8 /O2 氣體流動,並作為來自天線用高頻電源之供給電力而施加1200W,接著作為來自偏壓用高頻電源之供給電力而施加400W,來進行之。The etching process of the above mask is, for example, setting the pressure in the vacuum chamber to 0.67 Pa, and allowing Ar/C 4 F 8 /O 2 gas to flow at a flow rate of 180/20/10 sccm, and using it as a high antenna. 1200 W was applied to the power supply of the frequency power supply, and 400 W was applied to the power supply from the high-frequency power supply for bias voltage.

第2矽晶圓22(例如,厚度10μm)之蝕刻工程,係例如,將真空槽內之壓力設定為6.65Pa,且在150/55/0sccm之流量下讓SF6 /O2 /HBr氣體流動,並作為來自天線用高頻電源之供給電力而施加1000W,接著作為來自偏壓用高頻電源之供給電力而施加50W,來進行之。The etching process of the second wafer 22 (for example, a thickness of 10 μm) is, for example, setting the pressure in the vacuum chamber to 6.65 Pa, and allowing the SF 6 /O 2 /HBr gas to flow at a flow rate of 150/55/0 sccm. In addition, 1000 W was applied as power supply from the high-frequency power source for the antenna, and 50 W was applied as the power supplied from the high-frequency power source for bias voltage.

由SiO2 所構成之絕緣層(例如,厚度0.5μm)之蝕刻工程,係例如,將真空槽內之壓力設定為2Pa,且在180/20/10sccm之流量下讓Ar/C4 F8 /O2 氣體流動,並作為來自天線用高頻電源之供給電力而施加1200W,接著作為 來自偏壓用高頻電源之供給電力而施加400W,來進行之。An etching process of an insulating layer (for example, a thickness of 0.5 μm) composed of SiO 2 is, for example, setting the pressure in the vacuum chamber to 2 Pa, and letting Ar/C 4 F 8 / at a flow rate of 180/20/10 sccm / The O 2 gas flows and is applied as 1200 W from the supply power of the high-frequency power source for the antenna, and is applied by applying 400 W to the power supplied from the bias high-frequency power source.

上述接著劑層23之蝕刻工程,係例如,將真空槽內之壓力設定為1.5Pa,且在30/200/85sccm之流量下讓SF6 /O2 /N2 氣體流動,並作為來自天線用高頻電源之供給電力而施加2000W,接著作為來自偏壓用高頻電源之供給電力而施加300W,來進行之。The etching process of the above-mentioned adhesive layer 23 is, for example, setting the pressure in the vacuum chamber to 1.5 Pa, and allowing the SF 6 /O 2 /N 2 gas to flow at a flow rate of 30/200/85 sccm, and serving as an antenna. 2000 W was applied to the power supply of the high-frequency power source, and 300 W was applied to the power supplied from the high-frequency power source for bias voltage.

由上述SiO2 所構成之絕緣層,係只要使用例如TEOS作為原料氣體,並在眾所周知的製程條件(例如,參照日本特開2001-345315號公報)下形成即可。By the insulating layer formed of SiO 2, for example, as long as the TEOS-based gas as a raw material, and process conditions it is well known (e.g., see Japanese Laid-Open Patent Publication No. 2001-345315) can be formed next.

將如此所得之被處理基板S,載置於托架15上並加以固定。此外,分別將第一原料單體A(例如,苯均四酸二酐等之四羧酸二酐)及第二原料單體B(例如,4,4’-二苯基醚等之芳香族二胺),填充於第1圖所示的成膜裝置1之真空槽11內的蒸發用鎢舟皿13a及13b,並將被載置並固定有上述被處理基板S的托架15,設置於真空槽11內的上方。The substrate S thus obtained is placed on the holder 15 and fixed. Further, the first raw material monomer A (for example, tetracarboxylic dianhydride such as pyromellitic dianhydride) and the second raw material monomer B (for example, aromatics such as 4,4'-diphenyl ether) The diamine) is filled in the tungsten boat 13a and 13b for evaporation in the vacuum chamber 11 of the film forming apparatus 1 shown in Fig. 1, and the bracket 15 on which the substrate S to be processed is placed and fixed is provided. Above the inside of the vacuum chamber 11.

其次,在將真空槽11內進行排氣至特定的壓力(例如,1E-4Pa)之後,將各鎢舟皿13a及13b,加熱至能使各單體A及B產生蒸氣之特定的溫度,並將各閘門14a及14b打開,以使第一原料單體與第二原料單體的蒸氣,各等莫耳地同時飛散,或者是將閘門14a及14h分別交替地打開,以使各自的蒸氣,各等莫耳地錯開時間而飛散,而在被處理基板S上進行蒸鍍聚合,而形成特定膜厚之聚醯 胺酸(polyamide acid)膜。於兩原料在室溫下皆為固體的情況下,雖未予以圖示,但以將用來使蒸發量相同的狹縫板,安裝於鎢舟皿13a及13b上,而成各等莫耳地進行蒸發者較為理想。在被處理基板S上,原料單體A與B,會在以分子狀摻混的瞬間進行反應,而生成聚醯胺酸(polyamide acid)。然後,在特定的溫度(例如,250℃以下),特定的時間之間,在N2 環境等之惰性環境中,進行退火處理。如此一來,便可將聚醯胺酸(polyamide acid)醯亞胺化,並得到作為目標之由聚醯亞胺膜所構成的阻障膜。Next, after evacuating the inside of the vacuum chamber 11 to a specific pressure (for example, 1E-4Pa), each of the tungsten boats 13a and 13b is heated to a specific temperature at which each of the monomers A and B can generate steam. And opening the gates 14a and 14b so that the vapors of the first raw material monomer and the second raw material monomer are simultaneously scattered at the same time, or the gates 14a and 14h are alternately opened to respectively make the respective vapors. Each of them is scattered in a random manner, and is vapor-deposited on the substrate S to be processed to form a polyimide acid film having a specific film thickness. In the case where both raw materials are solid at room temperature, although not shown, the slit plates for the same evaporation amount are attached to the tungsten boat 13a and 13b to form each of the moire. The evaporation of the ground is ideal. On the substrate S to be processed, the raw material monomers A and B are reacted at the moment of molecular doping to form a polyamide acid. Then, annealing is performed at a specific temperature (for example, 250 ° C or lower), between specific times, in an inert environment such as an N 2 atmosphere. In this way, the polyamic acid ruthenium can be imidized, and the target barrier film composed of the polyimide film can be obtained.

若將如此所得之被處理基板S,搬入其他的CVD裝置中,在眾所周知的製程條件(例如,日本特開2009-130288號公報)下,形成作為配線膜之特定厚度的Cu膜或Al膜等,便可得到本發明之IC晶片封裝。形成有在250℃以下的成膜溫度下,絕緣特性、阻障特性、孔內之均一成膜特性優異的阻障膜。When the substrate S to be processed is carried into another CVD apparatus, a Cu film or an Al film having a specific thickness as a wiring film is formed under a known process condition (for example, JP-A-2009-130288). The IC chip package of the present invention can be obtained. A barrier film having excellent insulating properties, barrier properties, and uniform film forming properties in the pores at a film forming temperature of 250 ° C or lower is formed.

[實施例1][Example 1]

將作為阻障膜而形成聚醯亞胺膜的情況之實施例作展示。於本實施例中,使用第1圖所示之成膜裝置,分別將作為第一原料單體(A)之苯均四酸二酐及作為第二原料單體(B)之4,4’-二苯基醚,填充至蒸發用鎢舟皿13a及13b中,將固定於托架15上之矽晶圓S搬入真空槽11內,並進行排氣至1E-4Pa為止,此外,將鎢舟皿13a及13b加熱至特定的溫度,並將閘門14a及14b打開,以使苯均四 酸二酐與4,4’-二苯基醚之蒸氣,各等莫耳地同時飛散,而形成厚度300nm之聚醯胺酸(polyamide acid)膜。由於兩原料在室溫下皆為固體,因此雖未予以圖示,但將用來使蒸發量相同的狹縫板,安裝於鎢舟皿13a及13b上而進行。在矽晶圓S上,苯均四酸二酐與4,4’-二苯基醚,會在以分子狀摻混的瞬間進行反應,而生成聚醯胺酸(polyamide acid)。之後,在150℃下6小時之間,在N2 環境中,進行了退火處理。An example of a case where a polyimide film is formed as a barrier film is shown. In the present embodiment, using the film forming apparatus shown in Fig. 1, the pyromellitic dianhydride as the first raw material monomer (A) and the 4, 4' as the second raw material monomer (B), respectively. - Diphenyl ether, which is filled in the tungsten boat 13a and 13b for evaporation, and the silicon wafer S fixed on the carrier 15 is carried into the vacuum chamber 11, and is exhausted to 1E-4Pa, and further, tungsten is used. The boats 13a and 13b are heated to a specific temperature, and the gates 14a and 14b are opened, so that the vapors of the pyromellitic dianhydride and the 4,4'-diphenyl ether are simultaneously scattered and formed at the same time. A polyamic acid film having a thickness of 300 nm. Since both raw materials are solid at room temperature, although not shown, the slit plates for the same evaporation amount are attached to the tungsten boat 13a and 13b. On the tantalum wafer S, pyromellitic dianhydride and 4,4'-diphenyl ether are reacted at the instant of molecular doping to form polyamic acid. Thereafter, an annealing treatment was performed in an N 2 atmosphere between 6 hours at 150 °C.

由此可知,80%以上為進行醯亞胺化者。將該矽晶圓S,搬入其他的Cu-CVD裝置中,在眾所周知的製程條件下,形成厚度30nm之Cu膜。將形成有Cu膜的矽晶圓S取出,藉由SEM來觀察其剖面,而測量出矽晶圓S上之聚醯亞胺於各部位的膜厚。Cu膜,係為了確認密著性而形成者。將於各部位所測量出的聚醯亞胺膜之膜厚,展示於以下之表1中。From this, it can be seen that 80% or more of them are those which undergo imidization. The tantalum wafer S was transferred into another Cu-CVD apparatus, and a Cu film having a thickness of 30 nm was formed under well-known process conditions. The tantalum wafer S on which the Cu film was formed was taken out, and the cross section thereof was observed by SEM, and the film thickness of the polyimine on the tantalum wafer S at each portion was measured. The Cu film is formed to confirm adhesion. The film thickness of the polyimide film to be measured at each site is shown in Table 1 below.

於本實施例中所使用的矽晶圓S,係具有洞直徑5μm、深度50μm及70μm之孔圖案者。矽晶圓S上之膜厚測量部位,係如第3圖所示,為矽晶圓S之上表面A、孔內之側壁上部B、孔內之側壁中部C、孔內之側壁下部D、孔內之下部E。The tantalum wafer S used in the present embodiment has a hole pattern having a hole diameter of 5 μm, a depth of 50 μm, and a thickness of 70 μm. The film thickness measurement portion on the wafer S is as shown in FIG. 3, which is the surface A above the wafer S, the upper portion B of the sidewall in the hole, the middle portion C of the sidewall in the hole, and the lower portion D of the sidewall in the hole. Lower part E inside the hole.

根據表1可得知,在洞直徑5μm下,無論深度為50μm及70μm中任一部位,均能形成十分均勻的聚醯亞胺膜。此外,於上述觀察中可知,由於Cu膜並未剝離,因此亦可得到充分的密著性。According to Table 1, it can be seen that a very uniform polyimide film can be formed at any of the depths of 50 μm and 70 μm at a hole diameter of 5 μm. Further, in the above observation, it is understood that since the Cu film is not peeled off, sufficient adhesion can be obtained.

接著,一邊改變上述聚醯亞胺膜的膜厚,一邊在矽晶圓上之未有孔圖案的部位,形成0.5mm之Al膜,並於該Al膜與矽晶圓之間,施加電壓,而測量出V-I特性。將聚醯亞胺膜厚(nm)和實際電壓施加3V時之電流密度(洩漏電流密度(A/cm2 ))之關係,展示於第4圖中。Next, while changing the film thickness of the polyimide film, a 0.5 mm portion is formed on the surface of the germanium wafer having no hole pattern. The Al film was applied with a voltage between the Al film and the germanium wafer to measure the VI characteristics. The relationship between the film thickness (nm) of the polyimide film and the current density (leakage current density (A/cm 2 )) when the actual voltage is applied to 3 V is shown in Fig. 4.

根據第4圖可知,洩漏電流,雖隨著聚醯亞胺膜厚的增加而減少,但若膜厚變薄則變高。洩漏電流為高者,雖在實用上為較不理想的特性,但依據在膜厚200nm下得到10-7 A/cm2 、300nm下10-8 A/cm2 左右之值,可以說只要配合目的而調整膜厚,便可得到能充分供以實用之值。As can be seen from Fig. 4, the leakage current decreases as the thickness of the polyimide film increases, but becomes higher as the film thickness becomes thinner. Although the leakage current is high, although it is a less desirable property in practical use, it can be said that it is only 10 -7 A/cm 2 at a film thickness of 200 nm and a value of 10 -8 A/cm 2 at 300 nm. For the purpose of adjusting the film thickness, it is possible to obtain a practical value.

[實施例2][Embodiment 2]

對於依據實施例1所記載之方法而進行蒸鍍聚合所形成的膜,測量出紅外線吸收(IR)光譜。An infrared absorption (IR) spectrum was measured for the film formed by vapor deposition polymerization according to the method described in Example 1.

接著,測量出在100℃、150℃下IR光譜之經時變化,以求得蒸鍍膜之聚醯胺酸(polyamide acid)及聚醯亞胺之生成率。將其結果展示於第5圖中。Next, the change in the IR spectrum at 100 ° C and 150 ° C was measured to determine the formation ratio of polyamic acid and polyimine in the deposited film. The results are shown in Figure 5.

於第5圖中,橫軸係表示經過時間(hr),縱軸係表示醯胺化率(%)及醯亞胺化率(%)。分別將1650cm-1 、1380cm-1 之吸收的最大值作為100%,依據在各時間之吸收的深度之測量而求出。根據第5圖可知,在100℃下之剛蒸鍍後的膜,係70%左右成為聚醯胺酸(polyamide acid),並藉由加熱而進行醯胺化者。可知:若溫度提昇到150℃,則隨著時間的經過,聚醯胺酸(polyamide acid)會脫水,而變化成聚醯亞胺。於6小時之後,80%左右會變化成聚醯亞胺。In Fig. 5, the horizontal axis represents the elapsed time (hr), and the vertical axis represents the amidation ratio (%) and the oxime imidization ratio (%). Respectively, the maximum value of absorption 1650cm -1 -1, 1380 cm 100%, based on the measurement of the absorption depth of each of the determined time. As can be seen from Fig. 5, the film immediately after vapor deposition at 100 ° C is about 100% polyacrylic acid, and is subjected to amide amination by heating. It can be seen that if the temperature is raised to 150 ° C, over time, the polyamide acid will dehydrate and change to polyimine. After 6 hours, about 80% will change into polyimine.

[實施例3][Example 3]

依據實施例1所記載之方法進行蒸鍍聚合,而形成了聚醯亞胺膜。但,調節閘門14a及14b的開關,以使苯均四酸二酐與4,4’-二苯基醚之蒸氣,各等莫耳地錯開時間各自飛散,而於矽晶圓S上形成了特定厚度的聚醯亞胺膜。The vapor deposition polymerization was carried out in accordance with the method described in Example 1, to form a polyimide film. However, the switches of the gates 14a and 14b are adjusted so that the vapors of the pyromellitic dianhydride and the 4,4'-diphenyl ether are scattered at each time, and are formed on the silicon wafer S. Polyimine film of a specific thickness.

其結果,在洞直徑5μm下,無論深度為50μm及70μm中任一部位,均能與表1所示的結果略相等地形成均勻的Cu膜,且Cu膜亦無剝離。此外,與實施例1之情況相同地測量出V-I特性時,洩漏電流與聚醯亞胺膜之膜 厚的關係,係與第4圖之情況相同,只要配合目的而調整膜厚,便可得到能充分供以實用之值。As a result, a uniform Cu film was formed in a portion having a depth of 5 μm and a depth of 50 μm and 70 μm, which was slightly equal to the results shown in Table 1, and the Cu film was not peeled off. Further, when the V-I characteristic was measured as in the case of Example 1, the leakage current and the film of the polyimide film were measured. The thick relationship is the same as in the case of Fig. 4, and as long as the film thickness is adjusted in accordance with the purpose, a practical value can be obtained.

[產業上之可利用性][Industrial availability]

依據本發明,係提供一種藉由TSV技術,而於所接合的矽晶圓上,開設用以將IC晶片彼此電連接的洞,之後,於洞中形成阻障膜的方法,其係使2種以上之單體,在真空中蒸發,並藉由蒸鍍聚合法而可在250℃以下之成膜溫度下,於洞的表面形成阻障膜,並且,即使A/R為10以上也充分展現電鍍能力,而能充分使用的阻障膜及具有該阻障膜之IC晶片封裝,因此,能在利用TSV工程之半導體裝置領域中加以利用。According to the present invention, there is provided a method for forming a hole for electrically connecting IC chips to each other on a bonded germanium wafer by a TSV technology, and then forming a barrier film in the hole, which is The above-mentioned monomers are evaporated in a vacuum, and a barrier film can be formed on the surface of the hole at a film forming temperature of 250 ° C or lower by a vapor deposition polymerization method, and the A/R is sufficient even if it is 10 or more. The barrier film which exhibits the plating ability and can be fully used, and the IC chip package having the barrier film can be utilized in the field of semiconductor devices using TSV engineering.

1‧‧‧成膜裝置1‧‧‧ film forming device

S‧‧‧被處理基板(晶圓)S‧‧‧Processed substrate (wafer)

11‧‧‧真空槽11‧‧‧vacuum tank

12‧‧‧排氣系統12‧‧‧Exhaust system

13a、13b‧‧‧(蒸發用)鎢舟皿13a, 13b‧‧‧ (evaporation) tungsten boat

14a、14b‧‧‧閘門14a, 14b‧‧ ‧ gate

15‧‧‧托架15‧‧‧ bracket

A‧‧‧第一原料單體A‧‧‧First raw material monomer

B‧‧‧第二原料單體B‧‧‧Second raw material monomer

2‧‧‧IC晶片封裝2‧‧‧IC chip package

21‧‧‧第1矽晶圓21‧‧‧1st wafer

21a‧‧‧第1半導體元件區域(IC晶片)21a‧‧‧1st semiconductor device area (IC chip)

22‧‧‧第2矽晶圓22‧‧‧2nd wafer

22a‧‧‧第2半導體元件區域(IC晶片)22a‧‧‧2nd semiconductor device area (IC chip)

23‧‧‧接著劑層23‧‧‧ adhesive layer

24、25‧‧‧絕緣層24, 25‧‧‧Insulation

26‧‧‧阻障膜26‧‧‧Block film

27‧‧‧導電體膜27‧‧‧Electrical film

[第1圖]係模式性展示用以實施本發明之阻障膜之形成方法的成膜裝置之一構造例的概略圖。[Fig. 1] A schematic view showing a structural example of a film forming apparatus for carrying out the method for forming a barrier film of the present invention.

[第2圖]係展示IC晶片封裝之一模式性構造例的剖面圖。[Fig. 2] is a cross-sectional view showing a schematic structural example of an IC chip package.

[第3圖]係用以說明對實施例1中所得之聚醯亞胺的膜厚作測量之部位的矽晶圓之模式剖面圖。[Fig. 3] is a schematic cross-sectional view of a tantalum wafer for explaining a portion where the film thickness of the polyimide obtained in Example 1 is measured.

[第4圖]係展示於實施例1中所得之聚醯亞胺膜之膜厚(nm)和電壓施加時之電流密度(洩漏電流密度(A/cm2 ))之關係的圖表。[Fig. 4] is a graph showing the relationship between the film thickness (nm) of the polyimide film obtained in Example 1 and the current density (leakage current density (A/cm 2 )) at the time of voltage application.

[第5圖]係展示於實施例2中,根據對於蒸鍍聚合膜 所測量出之紅外線吸收(IR)光譜之經時變化所評價出之蒸鍍膜的聚醯胺酸(polyamide acid)及聚醯亞胺之生成率間的關係之圖表,橫軸係表示經過時間(hr),縱軸係表示醯胺化率(%)及醯亞胺化率(%)。[Fig. 5] is shown in Example 2, according to the film for vapor deposition A graph showing the relationship between the production rate of polyamic acid and polyimine of the vapor deposited film, as measured by the change in the infrared absorption (IR) spectrum, and the horizontal axis indicates the elapsed time ( Hr), the vertical axis represents the amide amination rate (%) and the oxime imidization rate (%).

Claims (11)

一種阻障膜之形成方法,其係將複數片形成有IC晶片的矽晶圓作堆積、接合,並藉由TSV技術,而於被接合的該矽晶圓上開設用以將IC晶片彼此電連接之洞,之後,在將複數片IC晶片作連接之該洞中形成導電體膜之前,於該洞中形成阻障膜之方法,其特徵為:使2種以上之單體在真空中蒸發,並藉由蒸鍍聚合法,而在該洞中形成由聚醯亞胺所構成之阻障膜,在前述聚醯亞胺成膜中乃至成膜後,添加矽烷偶合劑。 A method for forming a barrier film by stacking and bonding a plurality of germanium wafers on which IC chips are formed, and by using TSV technology, opening the bonded silicon wafers to electrically separate IC chips from each other A method of forming a barrier film in a hole before forming a conductor film in a hole in which a plurality of IC wafers are connected, characterized in that two or more monomers are evaporated in a vacuum Further, a barrier film made of polyimine is formed in the hole by a vapor deposition polymerization method, and a decane coupling agent is added after the formation of the polyimide or the film. 如申請專利範圍第1項所記載之阻障膜之形成方法,其中,在前述聚醯亞胺成膜中,將前述矽烷偶合劑相對於聚醯亞胺1mol而添加0.01~0.1mol。 The method for forming a barrier film according to the first aspect of the invention, wherein the decane coupling agent is added in an amount of 0.01 to 0.1 mol per mol of the polyimine. 如申請專利範圍第1項所記載之阻障膜之形成方法,其中,在前述聚醯亞胺成膜後,於形成前述導電體膜前,將前述矽烷偶合劑添加10分子層。 The method for forming a barrier film according to the first aspect of the invention, wherein after the formation of the polyimide film, the decane coupling agent is added to 10 molecules before the formation of the conductor film. 一種阻障膜之形成方法,其係將複數片形成有IC晶片的矽晶圓作堆積、接合,並藉由TSV技術,而於被接合的該矽晶圓上開設用以將IC晶片彼此電連接之洞,之後,在將複數片IC晶片作連接之該洞中形成導電體膜之前,於該洞中形成阻障膜之方法,其特徵為:使2種以上之單體在真空中蒸發,並藉由蒸鍍聚合法,而在該洞中形成由聚合物所構成之阻障膜,在前述阻障膜成膜中乃至成膜後,添加矽烷偶合劑。 A method for forming a barrier film by stacking and bonding a plurality of germanium wafers on which IC chips are formed, and by using TSV technology, opening the bonded silicon wafers to electrically separate IC chips from each other A method of forming a barrier film in a hole before forming a conductor film in a hole in which a plurality of IC wafers are connected, characterized in that two or more monomers are evaporated in a vacuum Further, a barrier film made of a polymer is formed in the hole by a vapor deposition polymerization method, and a decane coupling agent is added to the film formation of the barrier film or even after film formation. 如申請專利範圍第4項所記載之阻障膜之形成方法,其中,在前述阻障膜成膜中,將前述矽烷偶合劑相對於聚醯亞胺1mol而添加0.01~0.1mol。 The method for forming a barrier film according to the fourth aspect of the invention, wherein, in the film formation of the barrier film, the decane coupling agent is added in an amount of 0.01 to 0.1 mol per mol of the polyimide. 如申請專利範圍第4項所記載之阻障膜之形成方法,其中,在前述阻障膜成膜後,於形成前述導電體膜前,將前述矽烷偶合劑添加10分子層。 The method for forming a barrier film according to the fourth aspect of the invention, wherein after the barrier film is formed, the decane coupling agent is added to 10 molecules before the formation of the conductor film. 如申請專利範圍第4~6項中之任一項所記載之阻障膜之形成方法,其中,該單體,係由芳香族二胺與四羧酸二酐所構成者。 The method for forming a barrier film according to any one of claims 4 to 6, wherein the monomer is composed of an aromatic diamine and a tetracarboxylic dianhydride. 一種IC晶片封裝,其係具有將分別形成有IC晶片的複數片矽晶圓之各矽晶圓作堆積、接合的矽晶圓層積物之IC晶片封裝,其特徵為:於該矽晶圓層積物上,係於接合後設置藉由TSV技術所開設的洞,於該洞中,係形成有使用2種以上之單體並加以蒸鍍聚合而成之由被添加有矽烷偶合劑之聚醯亞胺所構成的阻障膜,接著於該阻障膜上形成有導電體膜。 An IC chip package having an IC chip package for stacking and bonding germanium wafer laminates of a plurality of wafers on which a plurality of IC wafers are formed, respectively, characterized by: In the layered product, a hole opened by a TSV technique is provided after the bonding, and in the hole, a monomer obtained by using two or more kinds of monomers and vapor-deposited is formed by adding a decane coupling agent. A barrier film composed of polyimide, followed by a conductor film formed on the barrier film. 如申請專利範圍第8項所記載之IC晶片封裝,其中,前述聚醯亞胺中之前述矽烷偶合劑,係相對於聚醯亞胺1mol而為0.01~0.1mol。 The IC chip package according to claim 8, wherein the decane coupling agent in the polyimine is 0.01 to 0.1 mol based on 1 mol of the polyimine. 一種IC晶片封裝,其係具有將分別形成有IC晶片的複數片矽晶圓之各矽晶圓作堆積、接合的矽晶圓層積物之IC晶片封裝,其特徵為:於該矽晶圓層積物上,係在接合後設置藉由TSV技術 所開設的洞,於該洞中,係形成有由蒸鍍聚合而成之聚合物所構成的被添加有矽烷偶合劑之阻障膜,接著於該阻障膜上形成有導電體膜。 An IC chip package having an IC chip package for stacking and bonding germanium wafer laminates of a plurality of wafers on which a plurality of IC wafers are formed, respectively, characterized by: On the stratification, it is set by the TSV technology after bonding In the hole formed, a barrier film containing a decane coupling agent composed of a polymer obtained by vapor deposition polymerization is formed, and then a conductor film is formed on the barrier film. 如申請專利範圍第10項所記載之IC晶片封裝,其中,前述阻障膜中之前述矽烷偶合劑,係相對於前述聚合物1mol而為0.01~0.1mol。The IC chip package according to claim 10, wherein the decane coupling agent in the barrier film is 0.01 to 0.1 mol based on 1 mol of the polymer.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000003910A (en) * 1998-06-16 2000-01-07 Ulvac Corp Formation of low specific inductive capacity insulating film and interlayer insulating film
JP2001011176A (en) * 1999-06-25 2001-01-16 Matsushita Electric Works Ltd Method for formation of polyimide film and polyimide film
JP2006012895A (en) * 2004-06-22 2006-01-12 Canon Inc Semiconductor device and its manufacturing method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
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JP2006141821A (en) * 2004-11-22 2006-06-08 Ulvac Japan Ltd Corrosion protection method
KR20060076856A (en) * 2004-12-29 2006-07-05 매그나칩 반도체 유한회사 Method for forming metal line of semiconductor device
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JP5391905B2 (en) * 2009-07-31 2014-01-15 宇部興産株式会社 Polyimide film and method for producing polyimide film

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000003910A (en) * 1998-06-16 2000-01-07 Ulvac Corp Formation of low specific inductive capacity insulating film and interlayer insulating film
JP2001011176A (en) * 1999-06-25 2001-01-16 Matsushita Electric Works Ltd Method for formation of polyimide film and polyimide film
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