TWI512834B - Anti punch-through leakage current metal-oxide-semiconductor transistor and manufacturing method thereof - Google Patents

Description

Metal oxide semi-electric crystal with anti-breakdown leakage current and manufacturing method thereof

The invention provides a gold-oxide semi-electrode with anti-breakdown leakage current and a manufacturing method thereof, in particular to a gold-oxygen semi-electrode for resisting breakdown current in an integrated circuit process and a manufacturing method thereof.

Please refer to the first figure (a), which is a circuit unit frequently used in the power management integrated circuit, which mainly consists of a set of P-type MOS array 11 and a set of N-type oxy-half. A transistor array (NMOS array) 12 is constructed, but in order to save circuit area and reduce source/drain on-resistance, the designer will replace the P-type MOS array 11 Another set of N-type MOS arrays 13 as shown in the first figure (b). The above-mentioned N-type MOS arrays 12 and 13 are completed by lateral diffusion MOS (LDMOS), and thus, the N-type MOS array. The P-type substrate (P-BODY) 131 in the (NMOS array) 13 will be in a high-voltage operating environment, and it is easy to cause a breakdown-through leakage current. How to improve these shortcomings is the main purpose of the development of this case.

SUMMARY OF THE INVENTION The object of the present invention is to provide a metal oxide semi-electrode that resists breakdown current and a method for fabricating the same, which are applied to an integrated circuit process for improving the lack of anti-breakdown leakage current.

The invention provides a method for manufacturing a metal oxide semi-electrode for resisting leakage current, comprising the steps of: providing a second type substrate; forming a high voltage deep first type well region in the second type substrate; A first type of lightly doped region is formed in the high voltage deep first type well region to complete the drain structure, and the first type dopant concentration of the first type lightly doped region is greater than the high voltage deep first type well region a type of dopant concentration; forming a mask structure having a dopant implant opening in the second type substrate; using the dopant implant opening for the first type dopant implantation, and in the high voltage deep first type well region Forming a breakdown-resistant leakage current structure, and then implanting a second type dopant by using a dopant implant opening to form a second type substrate, the depth of the breakdown-resistant current leakage structure is greater than that of the second type substrate, and the breakdown-resistant current leakage structure The first type dopant concentration is greater than the first type dopant concentration of the high voltage deep first type well region, and the second type substrate and the second type substrate have a high voltage deep first type well region and a breakdown breakdown current structure. isolation. A gate structure is formed over the second type substrate, wherein the first end of the gate structure extends above the second type substrate, and the second end of the gate structure extends above the first type lightly doped region.

In a preferred embodiment of the present invention, the second type substrate is a P-type germanium substrate having an isolation structure, and the high voltage deep first type well region is a high voltage N type deep well region, and the first type is lightly doped. The impurity region is an N-type lightly doped region.

In a preferred embodiment of the invention, the process of forming the high voltage deep first well region further includes a thermal process for driving the first type dopant to diffuse into a deeper region.

In a preferred embodiment of the invention, the process of forming the anti-breakdown leakage current structure further includes a thermal process to drive the first type of dopant into the deeper region.

In a preferred embodiment of the invention, the energy of the first type of dopant implanted by the formation of the anti-breakdown leakage current structure is greater than the energy of the second type of dopant implanted by the second type of substrate.

In a preferred embodiment of the present invention, the first type heavily doped region is formed on the second type substrate to complete the source structure contact region, and the first type is formed in the first type lightly doped region. The heavily doped region is used to complete the drain structure contact region, and the second type heavily doped region is formed in the second type substrate to complete the ground contact region.

In a preferred embodiment of the invention, the anti-breakdown leakage current structure has a greater depth than the second type of substrate and is located farther from the bottom of the second type of substrate than to the bottom of the high voltage deep first type well region.

In a preferred embodiment of the invention, the anti-breakdown leakage current structure has a depth greater than the second type of substrate and is located equidistant from the bottom of the second type of substrate and the bottom of the high voltage deep first type well region.

In a preferred embodiment of the present invention, the substrate is an N-type germanium substrate having an isolation structure, and the high-voltage deep first well region is a high-voltage P-type deep well region, and the first type is lightly doped. It is a P-type lightly doped region.

The present invention also provides a metal oxide semi-electrode for resisting leakage current, comprising: a second type substrate having a grounding region; and a first type of lightly doped region formed in the second type substrate for completing the defect The second structure is formed on one side of the first type lightly doped region to complete the source structure and the base structure; the gate structure is formed on the second type substrate, wherein the gate structure is first The end extends to the second type of substrate, the second end of the gate structure extends above the first type of lightly doped region; and the anti-breakdown leakage current structure is formed between the second type of substrate and the grounded region, the depth of which is greater than Type II matrix.

In a preferred embodiment of the present invention, the high voltage deep first type well region is further formed between the ground region of the second type substrate and the first type lightly doped region and the second type substrate, and is used for The second type substrate and the second type substrate are isolated.

In a preferred embodiment of the present invention, the anti-breakdown leakage current structure has a depth greater than that of the second type of substrate, and is located farther from the bottom of the second type of substrate and near the bottom of the high voltage deep first type well region.

In a preferred embodiment of the invention, the anti-breakdown leakage current structure has a depth greater than the second type of substrate and is located equidistant from the bottom of the second type of substrate and the bottom of the high voltage deep first type well region.

In a preferred embodiment of the present invention, the second type substrate and the second type substrate are separated by a high voltage deep first type well region.

In a preferred embodiment of the present invention, the second type substrate is a P-type germanium substrate having an isolation structure, and the high voltage deep first type well region is a high voltage N type deep well region, and the first type is lightly doped. The zone is an N-type lightly doped zone, and the second type of base system is a P-type matrix.

In a preferred embodiment of the invention, the P-type substrate has a plurality of N-type heavily doped regions for completing a plurality of source structure contact regions.

In a preferred embodiment of the invention, the P-type substrate has a P-type heavily doped region for isolating the N-type heavily doped regions.

In a preferred embodiment of the present invention, the N-type lightly doped region has a plurality of N-type heavily doped regions for completing a plurality of gate structure contact regions.

In a preferred embodiment of the present invention, the second type substrate further includes a plurality of MOS transistors, thereby forming a MOS matrix.

In a preferred embodiment of the present invention, the second type substrate is an N-type germanium substrate having an isolation structure, and the high voltage deep first type well region is a high voltage P type deep well region, and the first type is lightly doped. The zone is a P-type lightly doped zone.

Please refer to the second figure (a), (b), (c), (d), (e), (f), which is the process developed in this case to improve the formation of anti-breakdown leakage current structure in order to improve the lack of conventional means. Step Diagram First, the second figure (a) shows the formation of a high voltage deep first type well region in a specific region of the second type germanium substrate by using the first mask lithography and the first dopant implantation process. For example, if the first type is an N type, the second type is a P type; if the first type is a P type, the second type is an N type. In this embodiment, a high voltage deep N-well region (HVDNW) 20 is formed in a specific region of the P-type germanium substrate 2 in which the isolation structure 25 has been formed, so that the N-type doping can be performed. The quality (first type dopant) is deeper. After the dopant implantation process is completed, a thermal process can also be used to drive the N-type dopant into a deeper area of the Drive In. The isolation structure 25 can be completed by a common field oxide or Shallow Trench Isolation (STI). In addition, the high-voltage deep N-type well region 20 also utilizes a surrounding P-type well region ( P-well 28 is used to isolate from other components.

A second reticle lithography and a second dopant implantation process are then utilized to form a first type of lightly doped region in a particular region of the second type of substrate. In this embodiment, two N-type lightly doped regions 21 as shown in the second figure (b) are formed in the high voltage deep N-type well region 20 on the P-type germanium substrate 2, that is, a so-called N-drift region. (N-drift region) to complete the bungee structure. The doping concentration of the N-type lightly doped region 21 is greater than the doping concentration of the high voltage deep N-type well region 20.

A third mask lithography process is then utilized to form a mask structure 22 having a dopant implant opening 220 as shown in FIG. 2(c) in the P-type germanium substrate 2. In this embodiment, the dopant implant opening 220 is located between the two N-type lightly doped regions 21 such that the P-type germanium substrate 2 is exposed by the mask structure 22 between the two N-type lightly doped regions 21, and The following two dopant implantation processes are performed using the dopant implant opening 220.

As shown in the second figure (d), the third dopant implantation process is performed by using the dopant implantation opening 220 for implanting the N-type dopant in the high-voltage deep N-type well region 20 to form a breakdown-resistant leakage current. Structure 23, using a higher energy than the subsequent fourth dopant implantation process to perform the third dopant implantation process, so the position of the anti-breakdown leakage current structure 23 in the high voltage deep N-type well region 20 is later than the subsequent P-type The base (P-BODY) 24 is deeper in the high voltage deep N-type well region 20, and the N-type dopant concentration of the anti-breakdown leakage current structure 23 will be greater than the high voltage deep N-type well region 20. For example, the implantation potential of the high-voltage deep N-type well region 20 is about 2500 keV, the dopant concentration is about 1.2E12 cm ^-2 , and the implantation energy of the first-type lightly doped region is about 150 keV. About 2.9E12 cm ^-2 , the third dopant is implanted to form a breakdown ^- resistant leakage current structure 23 with an implantation energy of about 1300 keV and a dopant concentration of about 2.0E12 cm ^-2 . As for the formation of the fourth dopant of the P-type substrate 24 The implantation process has an implantation energy of about 180 keV and a dopant concentration of about 2.5E13 cm ^-2 . In order to make the N-type dopant (first-type dopant) deeper, the process of forming the anti-breakdown leakage current structure 23 further includes a thermal process to drive the N-type dopant into the deeper region.

As shown in the second figure (e), the fourth dopant implantation process is performed using the dopant implantation opening 220 for implanting the second type dopant to form the second type substrate. In this embodiment, a P-type dopant (P-BODY) 24 is formed by implanting a P-type dopant by a fourth dopant implantation process, and is located above the anti-breakdown leakage current structure 23 and near the surface of the P-type germanium substrate 2, The P-type substrate 24 is mainly used to complete the matrix and source structures. The anti-breakdown leakage current structure 23 has a greater depth than the P-type substrate 24 and is located farther from the bottom of the P-type substrate 24 and near the bottom of the high voltage deep N-type well region 20. In another embodiment, the anti-breakdown leakage current structure 23 is located equidistant from the bottom of the P-type substrate 24 and the bottom of the high voltage deep N-well region 20.

The two side-diffused metal-oxide-semi-transistor structures back-to-back as shown in the second figure (f) can be completed through subsequent processes. In this embodiment, two N-type heavily doped regions 241, 242 are formed on the P-type substrate (P-BODY) 24 to complete the contact region of the source structure, and the P-type heavily doped region 240 is used. The N-type heavily doped regions 241, 242 are isolated. As for the P-type substrate 24 and the isolation structure 25, a gate structure 26 is formed, which is located above the P-type substrate 2, wherein the first end of the gate structure 26 extends above the P-type substrate 24, and the second end of the gate structure 26 Extending over the N-type lightly doped region 21, the N-type lightly doped region 21 and the P-type substrate 24 are separated. The N-type heavily doped regions 211 and 212 in the N-type lightly doped region 21 are contact regions of the drain structure. As for the P-type heavily doped regions 291 and 292 in the P-type germanium substrate 2, the contact regions for the ground region 29 are used, and finally the N-type gold oxide half as shown in the first figure (b) can be completed. The transistor array 13. Due to the anti-breakdown leakage current structure 23 disclosed in the present case, the lateral diffusion MOS transistor has a better ability to resist breakdown current, but still maintains the same 汲 extreme breakdown voltage value (Drain Side Breakdown Voltage (BVD for short).

The anti-breakdown leakage current structure 23 can perform the dopant implantation process by using the opening defined by the same mask as the P-type substrate 24, thereby not increasing the number of masks in the process, and forming a breakdown-resistant leakage current structure. The order of the dopant implantation process for forming the P-type substrate 24 can be reversed without affecting the formation result, but both are suitable for performing the drive infiltration process using a thermal process to avoid the attack. The leakage current structure 23 and the formation of the P-type substrate 24 produce a change in dopant concentration concentration due to a thermal process.

In summary, after the technology of the present invention is improved, the lack of breakdown leakage current in the conventional means can be effectively eliminated. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

11. . . P-type gold oxide semi-transistor array

12. . . N-type gold oxide semi-transistor array

13. . . N-type gold oxide semi-transistor array

131. . . P type substrate

2. . . P-type germanium substrate

20. . . High voltage deep N type well area

twenty one. . . N-type lightly doped area

220. . . Doping implant opening

twenty two. . . Cover structure

twenty three. . . Anti-breakdown leakage current structure

twenty four. . . P type substrate

25. . . Isolation structure

241, 242. . . N-type heavily doped region

26. . . Gate structure

211, 212. . . N-type heavily doped region

291, 292. . . P-type heavily doped region

29. . . Grounding area

28. . . P type well area

The first figure (a) is a schematic diagram of a circuit unit that is often used in a power management integrated circuit.

The first figure (b) is a schematic diagram of another circuit unit that is often used in a power management integrated circuit.

The second figure (a), (b), (c), (d), (e), (f), which is a schematic diagram of the process steps for the formation of the anti-breakdown leakage current structure in order to improve the lack of conventional means. And a schematic diagram of the construction of the completed components.

2. . . P-type germanium substrate

20. . . High voltage deep N type well area

twenty one. . . N-type lightly doped area

220. . . Doping implant opening

twenty three. . . Anti-breakdown leakage current structure

twenty four. . . P type substrate

25. . . Isolation structure

240. . . P-type heavily doped region

241, 242. . . N-type heavily doped region

26. . . Gate structure

211, 212. . . N-type heavily doped region

291, 292. . . P-type heavily doped region

28. . . P type well area

29. . . Grounding area

Claims (20)

A method for manufacturing a breakdown current leakage MOS transistor comprises the steps of: providing a second type substrate; forming a high voltage deep first type well region in the second type substrate; and forming the second type substrate in the second type substrate Forming a first type lightly doped region in the high voltage deep first well region for completing a drain structure, wherein the first type dopant concentration of the first type lightly doped region is greater than the high voltage deep a first type of dopant concentration in the first well region; forming a mask structure having a dopant implant opening on the second type substrate; using the dopant implant opening to perform the first type dopant implantation Forming a breakdown current leakage current structure in the high voltage deep first well region, and the first type dopant concentration of the anti-breakdown leakage current structure is greater than the first type dopant concentration of the high voltage deep first type well region Forming a second type of dopant by using the dopant implant opening to form a second type substrate for completing a source structure and a base structure, the depth of the breakdown breakdown current structure being greater than the second a base body having the high voltage depth between the second type substrate and the second type substrate a type of well region and an anti-breakdown leakage current structure are isolated; and a gate structure is formed. Above the second type substrate, a first end extends above the second type substrate, and a second end extends to the first A type of lightly doped area above. The method for manufacturing a breakdown metal leakage nano-electrode according to claim 1, wherein the substrate is a P-type germanium substrate having an isolation structure, and the high voltage deep first well region is In a high voltage N-type deep well region, the first type lightly doped region is an N-type lightly doped region. The method for manufacturing a metal oxide semi-transistor for resisting breakdown current according to claim 1, wherein the forming of the high-voltage deep first-type well region further comprises a thermal process for the first type of doping The quality drive spreads to deeper areas. The method for manufacturing a metal oxide semi-transistor for resisting breakdown current according to claim 1, wherein the step of forming the anti-breakdown leakage current structure further comprises a thermal process for driving the first type dopant to diffuse into Deeper area. The method for manufacturing a breakdown metal leakage nano-electrode according to claim 1, wherein the energy of the first type dopant implanted by forming the anti-breakdown leakage current structure is greater than the formation of the second type substrate The energy of the second type of dopant implanted. The method for fabricating a breakdown metal leakage transistor according to claim 1, wherein a first type heavily doped region is formed on the second type substrate to complete a source structure contact region. Forming a first type heavily doped region in the first type of lightly doped region to complete the drain structure contact region, and forming a second type heavily doped region in the substrate to complete a ground contact region. The method for manufacturing a breakdown metal leakage transistor according to claim 1, wherein the anti-breakdown leakage current structure has a depth greater than the second type substrate and is located farther from the bottom of the second type substrate. And close to the bottom of the high voltage deep first well zone. The method for manufacturing a breakdown current leakage resistant metal oxy-halide transistor according to claim 1, wherein the anti-breakdown leakage current structure has a depth greater than the second type substrate, and is located at a bottom of the second type substrate The equidistance of the bottom of the high voltage deep first well zone. The method for manufacturing a breakdown metal leakage transistor according to claim 1, wherein the substrate is an N-type germanium substrate having an isolation structure, and the high voltage deep first well region is In a high voltage P-type deep well region, the first type lightly doped region is a P-type lightly doped region. A metal oxide semi-transistor resistant to breakdown current, comprising: a second type substrate having a grounding region; a high voltage deep first type well region formed in the second type substrate; a lightly doped region formed in the high voltage deep first well region for completing a drain structure; a second type substrate formed in the high voltage deep first well region and separated a side of the first type of lightly doped region for completing a source structure and a substrate structure; a gate structure formed over the second type substrate, wherein a first end extends above the second type substrate a second end extending above the first type lightly doped region; and a breakdown breakdown current structure formed in the high voltage deep first well region and located in the second type substrate and the ground region The depth is greater than the second type of matrix. The MOS leakage transistor of claim 10, wherein the high voltage deep first well region is formed on the ground region of the second type substrate and the first type is lightly doped. And between the second type substrate and the second type substrate and the second type substrate. The voltaic-peroxide transistor for resisting breakdown current according to claim 11, wherein the anti-breakdown leakage current structure has a depth greater than the second type substrate, and the anti-resistance The distance between the breakdown leakage current structure and the bottom of the second type of substrate is greater than the distance between the anti-breakdown leakage current structure and the high voltage deep first type well region. The MOS leakage transistor of claim 11, wherein the breakdown breakdown current structure has a depth greater than the second type substrate and is located at a bottom of the second type substrate and the high voltage Isometric distance at the bottom of the deep first well zone. The voltaic-peroxide transistor for resisting breakdown current according to claim 11, wherein the second type substrate and the second type substrate are separated by the high voltage deep first type well region. The voltaic-peroxide transistor for resisting breakdown current according to claim 11, wherein the second type substrate is a P-type 矽 substrate formed with an isolation structure, the high voltage deep first type well region For a high voltage N-type deep well region, the first type of lightly doped region is an N-type doped region, and the second type of base system is a P-type substrate. The voltaic-peroxide transistor for resisting breakdown current according to claim 15, wherein the P-type substrate has a plurality of N-type heavily doped regions for completing a plurality of source structure contact regions. The voltaic-period resistive breakdown current galvanic transistor according to claim 16, wherein the P-type substrate has a P-type heavily doped region for isolating the N-type heavily doped regions. The voltaic-peroxide transistor for resisting breakdown current as described in claim 15 wherein the N-type lightly doped region has a plurality of N-type heavily doped regions for completing A plurality of contact areas of the bungee structure. The MOS circuit according to claim 10, wherein the second type substrate further comprises a plurality of MOS transistors, thereby forming a MOS matrix. The voltaic-peroxide transistor for resisting breakdown current according to claim 10, wherein the second type substrate is an N-type 矽 substrate formed with an isolation structure, the high voltage deep first type well region For a high voltage P-type deep well region, the first type lightly doped region is a P-type lightly doped region.