TWI512618B - 萬用邏輯運算之方法及裝置 - Google Patents

萬用邏輯運算之方法及裝置 Download PDF

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Publication number
TWI512618B
TWI512618B TW103104892A TW103104892A TWI512618B TW I512618 B TWI512618 B TW I512618B TW 103104892 A TW103104892 A TW 103104892A TW 103104892 A TW103104892 A TW 103104892A TW I512618 B TWI512618 B TW I512618B
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TW
Taiwan
Prior art keywords
bit
value
source
instruction
immediate
Prior art date
Application number
TW103104892A
Other languages
English (en)
Chinese (zh)
Other versions
TW201432564A (zh
Inventor
Andrew T Forsyth
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW201432564A publication Critical patent/TW201432564A/zh
Application granted granted Critical
Publication of TWI512618B publication Critical patent/TWI512618B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
TW103104892A 2010-09-24 2011-09-23 萬用邏輯運算之方法及裝置 TWI512618B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/890,571 US8539206B2 (en) 2010-09-24 2010-09-24 Method and apparatus for universal logical operations utilizing value indexing

Publications (2)

Publication Number Publication Date
TW201432564A TW201432564A (zh) 2014-08-16
TWI512618B true TWI512618B (zh) 2015-12-11

Family

ID=45871870

Family Applications (2)

Application Number Title Priority Date Filing Date
TW103104892A TWI512618B (zh) 2010-09-24 2011-09-23 萬用邏輯運算之方法及裝置
TW100134372A TWI435266B (zh) 2010-09-24 2011-09-23 萬用邏輯運算之方法及裝置

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW100134372A TWI435266B (zh) 2010-09-24 2011-09-23 萬用邏輯運算之方法及裝置

Country Status (9)

Country Link
US (1) US8539206B2 (enExample)
JP (1) JP5607832B2 (enExample)
KR (1) KR101524450B1 (enExample)
CN (1) CN103109261B (enExample)
BR (1) BR112013006661A2 (enExample)
DE (1) DE112011103197T5 (enExample)
GB (1) GB2499532B (enExample)
TW (2) TWI512618B (enExample)
WO (1) WO2012040552A2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120124341A1 (en) * 2010-11-17 2012-05-17 Goodrich Allen B Methods and Apparatus for Performing Multiple Operand Logical Operations in a Single Instruction
US9128698B2 (en) * 2012-09-28 2015-09-08 Intel Corporation Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction
US20140095845A1 (en) * 2012-09-28 2014-04-03 Vinodh Gopal Apparatus and method for efficiently executing boolean functions
US9471310B2 (en) * 2012-11-26 2016-10-18 Nvidia Corporation Method, computer program product, and system for a multi-input bitwise logical operation
GB2523823B (en) * 2014-03-07 2021-06-16 Advanced Risc Mach Ltd Data processing apparatus and method for processing vector operands
US20160283242A1 (en) * 2014-12-23 2016-09-29 Intel Corporation Apparatus and method for vector horizontal logical instruction
US20160179521A1 (en) * 2014-12-23 2016-06-23 Intel Corporation Method and apparatus for expanding a mask to a vector of mask values
US10296489B2 (en) * 2014-12-27 2019-05-21 Intel Corporation Method and apparatus for performing a vector bit shuffle
US10296334B2 (en) * 2014-12-27 2019-05-21 Intel Corporation Method and apparatus for performing a vector bit gather
CA3093713C (en) 2018-04-20 2023-04-11 Google Llc Performing unary iteration and indexed operations

Citations (4)

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US5500947A (en) * 1988-06-27 1996-03-19 Digital Equipment Corporation Operand specifier processing by grouping similar specifier types together and providing a general routine for each
TW498275B (en) * 1999-05-24 2002-08-11 Toshiba Corp Processor unit
TWI233175B (en) * 2001-06-15 2005-05-21 Stc Unm Method for designing a digital integrated circuit chip, computer-readable storage medium, method for optimizing an application specific integrated circuit, method for optimizing a digital design, ASIC cell library for use in creation of custom integrated
US7464255B1 (en) * 2005-07-28 2008-12-09 Advanced Micro Devices, Inc. Using a shuffle unit to implement shift operations in a processor

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US4237532A (en) * 1977-09-02 1980-12-02 Sperry Corporation Table driven decision and control logic for digital computers
US5493687A (en) * 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5881307A (en) 1997-02-24 1999-03-09 Samsung Electronics Co., Ltd. Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor
JPH1185507A (ja) * 1997-09-05 1999-03-30 Mitsubishi Electric Corp 中央処理装置およびマイクロコンピュータシステム
US6721866B2 (en) 2001-12-21 2004-04-13 Intel Corporation Unaligned memory operands
US7014122B2 (en) * 2003-12-24 2006-03-21 International Business Machines Corporation Method and apparatus for performing bit-aligned permute
WO2008002177A1 (en) * 2006-06-30 2008-01-03 Intel Corporation Generating optimal instruction sequences for bitwise logical expressions
US20080021942A1 (en) * 2006-07-20 2008-01-24 On Demand Microelectronics Arrangements for evaluating boolean functions
US20080100628A1 (en) * 2006-10-31 2008-05-01 International Business Machines Corporation Single Precision Vector Permute Immediate with "Word" Vector Write Mask
CN101178644B (zh) * 2006-11-10 2012-01-25 上海海尔集成电路有限公司 一种基于复杂指令集计算机结构的微处理器架构
US7941641B1 (en) 2007-10-01 2011-05-10 Yong-Kyu Jung Retargetable instruction decoder for a computer processor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5500947A (en) * 1988-06-27 1996-03-19 Digital Equipment Corporation Operand specifier processing by grouping similar specifier types together and providing a general routine for each
TW498275B (en) * 1999-05-24 2002-08-11 Toshiba Corp Processor unit
TWI233175B (en) * 2001-06-15 2005-05-21 Stc Unm Method for designing a digital integrated circuit chip, computer-readable storage medium, method for optimizing an application specific integrated circuit, method for optimizing a digital design, ASIC cell library for use in creation of custom integrated
US7464255B1 (en) * 2005-07-28 2008-12-09 Advanced Micro Devices, Inc. Using a shuffle unit to implement shift operations in a processor

Also Published As

Publication number Publication date
GB201306690D0 (en) 2013-05-29
GB2499532B (en) 2020-04-01
BR112013006661A2 (pt) 2016-06-07
TWI435266B (zh) 2014-04-21
KR101524450B1 (ko) 2015-06-02
CN103109261A (zh) 2013-05-15
DE112011103197T5 (de) 2013-07-04
JP5607832B2 (ja) 2014-10-15
US8539206B2 (en) 2013-09-17
WO2012040552A2 (en) 2012-03-29
TW201232392A (en) 2012-08-01
CN103109261B (zh) 2016-03-09
TW201432564A (zh) 2014-08-16
WO2012040552A3 (en) 2012-05-18
GB2499532A (en) 2013-08-21
KR20130064797A (ko) 2013-06-18
JP2013543175A (ja) 2013-11-28
US20120079244A1 (en) 2012-03-29

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