TWI504153B - Phase - locked loop circuit and oscillation method - Google Patents

Description

Phase-locked loop circuit and oscillation method

The present invention relates to a phase locked loop circuit, a pulse signal converter, a pulse width controlled oscillator, and an oscillation method, particularly regarding a pulse width according to an input pulse signal. And the phase-locked loop circuit is controlled.

As the semiconductor process progresses, the transistor is made fine, and the transistor operates at a lower voltage and at a higher speed. The reduction in the power supply voltage in the analog circuit causes degradation of the voltage resolution of the signal. On the other hand, the transistor operating at high speed improves the resolution of the signal in the time direction. Now, it can be said that the temporal resolution represented by the voltage transition of 0 and 1 which has reached the digital voltage using the pulse width or the like has a resolution higher than the voltage resolution of the analog voltage. A new situation (see Non-Patent Document 1).

A conventional PLL will be described with reference to Figs. 15 and 16 . Fig. 15 is a view for explaining a thermometer code and a Soft Thermometer Code (STC). Fig. 16 is a block diagram showing an outline of a conventional PLL. As shown in FIG. 16(a), in the conventional analog PLL 101, a pulse outputted by a phase frequency Detector (PFD) 103 is converted into a VCO 111 by a charge pump 105 and capacitors 107 and 109. Control voltage. Specifically, the charge pump 105 converts the time information of the UP pulse signal and the DN pulse signal outputted by the PFD 103, which is input to the input of the PLL 101 and the frequency dividing circuit 113 as input, into a charge amount. The output frequency is controlled by the capacitors 107, 109 of the loop filter converting the amount of charge into an analog voltage and controlling the VCO 111. However, a small charge pump 105 and a large capacitor 107, 109 are required to be mismatched.

In the All-Digital PLL, the phase difference between the reference signal and the feedback signal is digitized by using a time-to-digital converter (TDC), and the reference signal is compared with a digital code. The phase difference of the feedback signal is digitized, and the analog signal is controlled by the digital code to control the oscillation frequency. However, it takes a lot of labor to suppress the quantization noise of the TDC.

On the other hand, as shown in FIG. 16(b), in a pulse width controlled PLL (PWPLL) 201 which controls the oscillation frequency by a pulse width, an oscillator whose oscillation frequency is proportional to the input pulse width is used. The PWCO (Pulse Width Controlled Oscillator) 211 replaces the VCO 111 (see Non-Patent Document 2). The signal output from the output of the PFD 203, which is input to the input of the input and frequency dividing circuit 213 of the PWPLL 201, to the input of the PWCO is smoothed by the RC filter (RC filter) and is not converted into an analog voltage, and the voltage is 0 or 1 digit. The value, time width, is treated as an analog with the analog value as a pulse with information.

In the PWPLL, since the pulse width is converted into a soft thermometer code, the frequency of the oscillator is controlled by the STC, so that it is not necessary to measure a large capacitor of an area.

As shown in Fig. 15(b), the STC only has a code of analogy value of 1 bit (or 2 bit) at the boundary between 0 and 1 of the thermometer code (Fig. 15(a)), and has a wide dynamic range and no quantization. Quantumization noise-free.

[Non-Patent Document 1]: RB Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C Ho, JL Wallberg, C. Fernando, KMR Staszewski, T. Jung, J. Koh, S John, IY Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, OE Eliezer, E. de-Obaldia, and PT Balsara, “All digital TX frequency synthesizer and descrete-time receiver for Bluetooth radio in 130-nm CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2278-2291, Dec. 2004.

[Non-Patent Document 2]: T. Nakura, K. Asada, "Low Pass Filter-less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter," IEICE Trans on Elec., March 2012.

However, in the conventional PWPLL, a frequency proportional to the phase difference between the reference input and the divider output is output, and is a Type-I PLL that retains the phase difference even in the locked state. This is problematic in some applications such as inter-chip communication.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a phase-locked loop circuit or the like which is novel in pulse width control which can reduce phase offset.

A first aspect of the present invention is a phase-locked loop circuit that is controlled according to a pulse width of an input pulse signal, comprising: a pulse width-controlled oscillator that oscillates according to a pulse width of an input signal; and the pulse from the pulse according to the input pulse signal a phase difference comparator for outputting a phase difference between an output signal of the width control oscillator and an UD pulse signal; a pulse width integrator for generating an integrated signal of the pulse signal based on the UP pulse signal and the DN pulse signal, the pulse width control The oscillator oscillates according to the pulse width of the integration signal, and also oscillates according to the pulse width of at least one of the UP pulse signal and the DN pulse signal.

A third aspect of the present invention is the phase locked loop circuit of the first aspect or the second aspect, wherein the pulse width integrator has a rising edge detecting circuit that responds to a rising edge of a signal input and outputs a pulse signal ( Rising edge detecting circuit) A circuit that is connected in a ring shape or a circuit that connects a falling edge of a signal input and outputs a falling edge detecting circuit of a pulse signal into a ring.

A fourth aspect of the present invention is the phase locked loop circuit of the third aspect, wherein the rising edge detecting circuit or the falling edge detecting circuit has a pulse width expander that amplifies a pulse width of an input signal.

A fifth aspect of the present invention is the phase locked loop circuit of the third aspect, further comprising: counting the number of times the foregoing two pulse signals are connected to the loop circuit by the rising edge detecting circuit, or the two pulses The signal passes through a count circuit that connects the aforementioned falling edge detecting circuit to the number of loop circuits.

A sixth aspect of the present invention is the phase-locked loop circuit of the third aspect, wherein the rising edge detecting circuit or the falling edge detecting circuit further includes a delay circuit for delaying each of the two pulse signals, the delay circuit The rising edge detecting circuit before the rising edge detecting circuit or the falling edge detecting circuit having the aforementioned rising edge detecting circuit or the falling edge detecting circuit reaches the rising edge detecting circuit or the foregoing The falling edge detection circuit shortens the delay time for the condition.

A seventh aspect of the present invention is the phase locked loop circuit of the first aspect or the second aspect, wherein the pulse width integrator is higher in a case where a pulse width of the UP pulse signal is longer than a pulse width of the DN pulse signal The pulse width of the sub-generated integrated signal is further reduced to generate a pulse width of the integrated signal, and when the pulse width of the UP pulse signal is shorter than the pulse width of the DN pulse signal, the pulse width of the integrated signal generated last time It is also increased to generate the pulse width of the aforementioned integrated signal.

An eighth aspect of the present invention is a pulse width controlled oscillator comprising a pulse width oscillating according to a pulse width of an input pulse signal In addition to the pulse widths of the two pulse signals of the UP pulse signal and the DN pulse signal, the pulse width control oscillator also oscillates according to the following: two pulse signals according to the UP pulse signal and the DN pulse signal The pulse width of the integrated signal generated by increasing or decreasing the pulse width by the difference in pulse width.

A ninth aspect of the present invention is an oscillation method, which is an oscillation method in a phase-locked loop circuit that controls a pulse according to a pulse width of an input pulse signal, and includes the following steps: except for the UP pulse signal and the DN pulse signal In addition to the pulse width of the two pulse signals, the pulse width of the integrated signal generated by increasing or decreasing the pulse width according to the difference in pulse width between the two pulse signals of the UP pulse signal and the DN pulse signal is also oscillated as follows.

In accordance with various aspects of the present invention, a novel pulse width controlled PLL circuit or the like can be provided. Further, since the pulse width control oscillator oscillates based on the pulse width of the integrated signal reflected by the information on which the UP pulse signal and the DN pulse signal are stored, the phase shift can be reduced.

Moreover, in accordance with the above aspect of the present invention, the PFD and PWCO are directly connected in the conventional PWPLL shown in FIG. 16(b), and P control and I control are performed on the PWCO by feedback, so that the pulse of the PLL circuit is made. PI control in width control is possible. Therefore, it is easier to further reduce the phase shift as compared with the pulse width control by only the conventional P control.

Further, according to the above aspect of the present invention, it is possible to specifically increase or decrease the pulse width of the integrated signal based on the UP pulse signal and the DN pulse signal. This makes it possible to control the pulse width of the integrated signal whose pulse width is increased by the DN pulse signal, for example, by reducing the pulse width by the UP pulse signal.

Here, when the pulse width integrator has a buffer chain formed by an inverter, the rise time or fall time of each inverter due to local inconsistency of the process (fall time) inconsistency, the pulse width is enlarged or reduced when the pulse is running in the buffer link, and the pulse disappears soon (for example, refer to T.Izuka, J.Jeong, T.Nakura, M.Ikeda, K.Asada, "All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Measurement Utilizaing Buffer Ring with Pulse Counter," in Proc. of IEEE ESSCIRC, pp. 182-185, Sep., 2010).

Therefore, according to the third aspect of the present invention, the pulse width is expressed not by one signal but by the time difference of the rising edges of the two pulse signals. Therefore, even if the pulse width of each pulse signal changes a little due to local inconsistency of the process, the information of the pulse width which the pulse width integrator should output is also held by the information of the time difference of the two pulse signals. As a result, it becomes easy to import the correct integral action.

Here, the rising edge or the falling edge is used as the detecting circuit, and there may be a circuit configuration for reducing the pulse width. In this case, there is a lapse of the pulse itself when the pulse signal is running on the buffer link.

Thus, in accordance with a fourth aspect of the present invention, a pulse width amplifier maintains a pulse width of two pulse signals propagating within a pulse width integrator. Therefore, the pulse width integrator may have a circuit in which the rise detecting circuit or the falling detecting circuit is connected in a ring shape. Even with this configuration, the pulse signal does not shrink and disappear, and the propagation of the pulse can be maintained.

Further, according to the fifth aspect of the present invention, among the two pulse signals of the loop, the pulse passing through the rise detecting circuit is the first pulse signal or the second pulse signal.

For example, by accelerating the first pulse signal of the loop according to the DN pulse signal and accelerating the second pulse signal according to the UP pulse signal, the propagation speeds of the two pulse signals can be independently controlled. At this time, if the pulse width of the UP pulse signal is longer than the pulse width of the DN pulse signal, the pulse width of the integrated signal output from the pulse width integrator becomes shorter, and conversely, becomes longer. Otherwise, if the pulse width of the UP pulse signal is longer than the pulse width of the DN pulse signal, the pulse width of the integrated signal output from the pulse width integrator becomes longer, and if it is shorter, it may be shorter.

Further, according to the sixth aspect of the present invention, it is possible to maintain the interval of two pulse signals of a certain number or more of the loops. According to this, it is possible to prevent a situation in which one of the two pulse signals catches up and the pulse disappears.

1‧‧‧PWPLL

3, 203‧‧‧PFD

5‧‧‧PWACC

11, 211‧‧‧PWCO

13‧‧‧dividing circuit

21‧‧‧Initialization Department

23‧‧‧Selector

25‧‧‧Rise detection circuit

27‧‧‧D-FF

31‧‧‧Rising Edge Detection Department

33, 37, 94‧‧ ‧ buffer department

35‧‧‧ Pulse width amplification

39‧‧‧D-FF

41‧‧‧Control Circuit Department

43‧‧‧Selector

45‧‧‧Inverter Department

47, 49, 53, 55‧‧‧ NAND gate

51, 73, 91, 95‧‧ ‧ inverter

71‧‧‧TSTC

75, 79, 83‧‧‧ transistors

77, 85, 98, 107, 109‧ ‧ capacitors

92‧‧‧Signal generation circuit

93‧‧‧Descent detection circuit

96, 97‧‧‧ switch

101, 201‧‧‧ PLL

103‧‧‧PFD

105‧‧‧Charge pump

111‧‧‧VCO

113, 213‧‧ ‧ frequency dividing circuit

Fig. 1 is a block diagram showing an outline of a PWPLL related to the present embodiment.

2 is a diagram showing an open loop transfer function of the PWPLL of FIG. 1.

3(a) and 3(b) are block diagrams showing an outline of a PWACC related to the present embodiment.

4 is a timing diagram showing the transfer of pulses in the PWACC of FIG.

FIG. 5 is a diagram showing a logic circuit of a variable delay NAND gate in the PWACC of FIG.

FIG. 6 is a timing chart showing cells in the PWACC of FIG.

Fig. 7 is a block diagram showing an outline of a PWCO related to the present embodiment.

Fig. 8 is a block diagram showing an outline of a TSTC.

9 is a timing diagram of the TSTC of FIG.

Fig. 10 is a view showing an example of generation of a soft thermometer code generated by TSTC.

Fig. 11 is a view showing transition of an output signal of PWACC from when the UP pulse signal and the DN pulse signal are not input.

Fig. 12 is a view showing simulation results in which the phase of the reference input and the feedback of the PWPLL according to the present embodiment coincide.

FIG. 13 is a diagram showing a transient response in a case where a reference frequency is switched to a stepped state.

Fig. 14 is a view showing a transient response of an output signal of the PWACC in the case of Fig. 13.

Figure 15 is a diagram illustrating a thermometer code and a soft thermometer code.

Fig. 16 is a block diagram showing an outline of a conventional PLL.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. Further, the form of the embodiment of the present invention is not limited to the following embodiments.

[Examples]

A phase-locked loop circuit (PWPLL) according to the present embodiment (an example of [phase-locked loop circuit] in the present claim) will be described with reference to Fig. 1 . Fig. 1 is a circuit diagram of a PWPLL 1 related to the present embodiment.

PWPLL1 includes: PFD3 (an example of [phase frequency comparator] in the case of the present application), and Pulse Width Accumulator (PWACC) 5 (an example of [pulse width integrator] in the present claim), and PWCO11 (an example of [pulse width control oscillator] in the present claim) and frequency dividing circuit 13.

In order to display the PLL circuit with a phase difference of zero (Type-II) at the time of locking, the PWPLL1 is also arranged in the time domain in addition to the Type-I PLL circuit shown in FIG. 16(b). (time domain) integral PWACC5 and PI control of PWCO11. The pulse width of the pulse output by PWACC5 is expressed as two input pulses (UP pulse signal (an example of [UP pulse signal] in the request case of this case) and DN pulse signal ([DN pulse signal] and [in the request case of the present case] A circuit of an integrated signal of an integral value of a difference in pulse width (an example of [integrated signal] in the case of the present invention) of the pulse signal converter]. The operation will be described later.

The PWCO 11 takes as input a total of three pulses of the UP pulse signal and the DN pulse signal of the proportional component and the output pulse of the PWACC 5 of the integral component. The oscillation frequency of the PWCO is proportional to the linear sum of the three pulse widths. This point is also described later.

The output from the PWCO 11 is input to the PFD 3 via a frequency dividing circuit 13 that divides the frequency into 1/N. The frequency divided is locked by the reference input to PFD3, so the output signal from PWCO11 will have a frequency N times the reference input.

The open loop gain of the PWPLL1 H _open (s) is as follows: [Formula 1]

Here, it is assumed that the gain of the proportional component pulse of PWCO11 and the gain of the integral component are K _PWCO-p [Hz/s] and K _PWCO-i [Hz/s], respectively, and the integral conversion gain of PWACC5 is K _ACC , set the reference frequency to f _ref [Hz]=1/T _ref [s].

Moreover, the damping factor is as follows:

As shown in FIG. 2, phase locking is achieved by having two poles at the origin, and the proportional component produces zero at the loop gain, and phase correction is stabilized. Give feedback.

Next, the PWACC 5 will be described with reference to Fig. 3 . FIG. 3 (a) is a schematic block diagram of PWACC5, FIG. 3 (b) is a block diagram schematic of rise detection circuit 25 _k is displayed.

PWACC5 comprising: initializing section 21 is sequentially connected; a selector (selector) 23; a plurality of rise detection circuit _{25 1, 25 2, ...,} 25 n-1, 25 n ([ requested item in this case rising edge detection circuit An example of this is hereinafter referred to as [rise detection circuit _25k ]. The same applies to other circuit units having a plurality of elements.) A delay flip flop (D-FF) 27. The signal input to the initialization unit 21 is output via the selector 23 and a plurality of rise detection circuits 25 ₁ , 25 ₂ , ..., 25 _n-1 , 25 _n and D-FF 27 . Further, the output of the rise detecting circuit 25 _n is also input to the selector 23, and the selector 23 and the plurality of rise detecting circuits 25 ₁ , 25 ₂ , ..., 25 _n-1 , 25 _n are connected in a ring shape. Further, an UP pulse signal and a DN pulse signal output from the PFD 3 are also input to the respective rise detecting circuits 25 _k .

PWACC5 is an integrator that integrates the pulse width in the time domain. Moreover, PWACC5 is internally held with the integral value as time information. In the PWACC 5, two short pulses (an example of [two pulse signals] in the present claim) are wound around the same loop structure, and the time difference T between the two pulses is maintained as the value of the time domain. The output of PWACC 5 is a repetition pulse of the time width T obtained by dividing the two pulses by D-FF 27.

Usually, when the pulse is on the buffer link formed by the inverter, the pulse width is enlarged or reduced due to the inconsistency of the rise time and the fall time of each inverter due to the local inconsistency of the process, and the pulse disappears soon. .

In PWACC5 In order to solve this problem, as shown in FIG 3 (a), the increase in the response signal and outputting single (one shot) short pulse rise detection circuit 25 _k are arranged in a ring shape. According to this, a structure in which the pulse is continuously enlarged without being enlarged or reduced in the ring. The two pulses are similarly wound around the same ring and are raised or lowered in the same state. Therefore, the velocity propagated in the loop is the same, and how the transistor has individual differences is also maintained between the two pulses.

In the PWACC 5, the two pulses held for this time difference are independently changed from the outside by the propagation speed of the respective pulses. According to this, the time difference between the two pulses is increased or decreased and the integration operation is performed.

The first pulse only propagates faster when the DN pulse signal is input. The second pulse propagates faster only when the UP pulse signal is input. Therefore, the output pulse width T is increased or decreased in proportion to the difference between the pulse widths of the UP pulse signal and the DN pulse signal. Specifically, T is reduced by the UP pulse signal and increased by the DN pulse signal.

Rise detection circuit ring 25 _k in FIG. 3 (b) shown, there are sequentially connected: a rising edge detecting section 31, the buffer (buffer) 33, and the pulse width of an enlarged portion 35 (in this case requested item [ An example of the pulse width amplifier is the buffer unit 37, the D-FF 39, the control circuit unit 41, and the selector 43. The output of the buffer unit 37 is also connected to the output of the rise detecting circuit _25k .

The rising edge detecting unit 31 has an inverter unit 45 and a NAND gate 47. The inverter unit 45 is constituted by an odd number of inverters connected in series by inputting the input to the rising edge detecting unit 31. The NAND gate 47 is connected to the output from the inverter unit 45, and the input is connected to the input to the rising edge detecting unit 31.

The buffer portion 33 having the output from the NAND gate 47 as an input, an even number of the serially connected NAND gates 49 _k. NAND gate 49 _k is connected to the one power input, the input connected to the output 47 of the other party or the other NAND gate 49 _k-1 from the NAND gate.

Amplifying the pulse width portion 35 51 _k having even number of inverters connected in series with the NAND gate 53. The pulse width amplifying section 35 takes an output from the NAND gate 49 as an input, and an even number of inverters _51k and NAND gates 53 are sequentially connected in series.

The buffer portion 37 having the output from the NAND gate 53 as an input, an even number of the serially connected NAND gates 55 _k. The NAND gate _55k is connected to the power supply as the input side, and the input side is connected to the output from the NAND gate 53 or other NAND gate _55k-1 .

The output from the D-FF 39 _n possessed by the rise detecting circuit 25 _n is fed back to the input of the D-FF 39 _n and is output as Q _n . Further, rise detection circuit 25 _n has a control circuit section 41 as an input to Q _n, and in order to increase detection circuit 25 _{n + 2} has a D-FF39 _{n +} Q _{n 2 + 2} output as input.

The selector 43 takes as input the three signals from the output of the control circuit unit 41, the UP pulse signal from the PFD 3, and the DN pulse signal. Further, the selector 43 to the NAND gates 47,49 _k, 53, and 55 _k FAST transmission enabling signal of the two pulse signals propagated accelerated.

4 is a timing chart of the rise detecting circuit.

The rising edge detecting unit 31 having the NAND gate as a constituent element outputs a short pulse to the rise of the input signal. The rising edge detecting portion 31 using the NAND gate is basically a shorter output pulse than the input pulse. Therefore, even if the connection is made into a ring, the pulse shrinks and disappears. Therefore, the pulse width amplifying portion 35 is inserted, thereby maintaining the propagation of the pulse.

The propagation speed of the pulse is determined by the delay time of the NAND gate (an example of [delay circuit] in the present claim). Therefore, in order to perform the integration operation, all the NAND gates are switched as shown in FIG. 5 by the FAST signal. That is to say, when the input (A, B) = (H, H) to the NAND gate becomes the output Y = L. Further, when the input (A, B) is a combination of other values, the output Y = H is obtained. If the FAST signal is H, the delay time becomes small.

Moreover, the two pulses of the loop are counted by D-FF39 (an example of [counting circuit] in the present claim). Accordingly, the difference followed by the rising detecting circuit 25 _k for the first pulse or the second pulse of a pulse. If the pulse that passes through is the first pulse, the FAST signal to the NAND gate is driven by the DN pulse signal. Otherwise, if it is the second pulse, the FAST signal is driven by the UP pulse signal.

Accordingly, as shown in FIG. 6, the propagation speeds of the two pulses around the loop are independently controlled by the UP pulse signal and the DN pulse signal. If When the pulse width of the UP pulse signal is longer than the pulse width of the DN pulse signal, the output pulse width of the PWACC 5 becomes shorter, and conversely, becomes longer.

In order to prevent the two pulses of the loop from being excessively close, the control circuit portion 41 controls the selector 43 so as not to accelerate the next pulse by the FAST signal until the pulse reaches the two segments before the pulse passes.

Next, a pulse width control oscillator (PWCO) 11 will be described with reference to FIG. Fig. 7 is a block diagram showing an outline of the PWCO 11.

PWCO11 having: inputted TSTC71 ₁ DN pulse signals from the PFD3 output; is inputted by the TSTC71 ₂ UP pulse signals PFD3 output; is inputted by the PWACC5 output from the integrator signals TSTC71 _3; odd number (2m are connected in series + One, m is a natural number) inverter 73 _k . The inverter 73 _{2m + 1} is input from the output PWCO11 output and to the inverter _731, inverter 73 _K is connected in a ring.

For 1 ≦ k ≦ m, the inverter 73 _k of the inverter are connected in sequence with a 73 _{k + 1} between the signal from TSTC71 ₁ is 1 is ON and the transistor 75 _k 77 _k grounded capacitor . Further, for m + 1 ≦ k ≦ 2m + 1, 73 _k in the inverter and the inverter is connected to the signal sequence from TSTC71 ₂ when 0 is 79 _k ON and the transistor between 73 _{k + 1} A capacitor 81 _k connected to the power source. Further for 1 ≦ k ≦ 2m + 1, 73 _k in the inverter of the inverter are connected in sequence with a 73 _{k + 1} between the signal from TSTC71 ₃ is 1 is ON and the transistor 83 _k grounded Capacitor 85 _k .

In PWCO11, the first input pulse is converted by a soft thermometer code (STC) proportional to its pulse width. The pulse width is represented by the number of bits of one. The mantissa is represented by the analog voltage value of the bit at the boundary of 1 and 0.

Next, the TSTC 71 will be described with reference to Figs. 8 and 9 . Fig. 8 is a block diagram showing an outline of a TSTC. Figure 9 is a timing diagram of the TSTC.

TSTC71 comprising: an inverter 91, circuits _{92 k (1 ≦ k ≦ N} ), the drop detection circuit (FED) 93 and a plurality of signal generation are connected in series. The inverter 91 takes an input to the TSTC 71 as an input and outputs it to the signal generating circuit 92 ₁ . Signal generating circuit 92 _k is the inverter output signal generating circuit 91 or the output 92 _k-1 as inputs, the output signal generation circuit 92 _{k + 1.} Further, the signal generating circuit of the transistors 92 _k 75 _k, 79 _k or 83 _k outputs a soft thermometer (soft thermometer) signal ST _k.

The signal generating circuit 92 has a buffer 94, an inverter 95, a switch 96, a switch 97, and a capacitor 98 that is grounded. Signal generating circuit 92 _k has an output buffer is a buffer 94 _k 94 _k-1 is used as an input of the output buffer 94 _{k + 1.} Moreover, the output of the buffer 94 _k is input to the inverter 95 _k . Inverter output switch 95 _k 96 _k 97 _k and the switch output signal ST _k via soft thermometer. Switch 96 is turned "ON" when the input to TSTC is H. The switch 97 is turned ON when the output of the FED 93 from which the input to the TSTC 71 is input is H. Capacitor 98 is connected between switch 96 and switch 97.

The pulse is input to the TSTC 71, the input is raised from 0 to 1, and the falling step is propagated to the buffer column of the N segment. By the delay time of the buffer, the input side k-segment of the buffer column becomes 0 in the falling edge of the input pulse, and the remaining (N-k) segments become 1.

In each section of the buffer, as shown in Fig. 8, a slow inverter 95 indicated by a symbol "s" is connected. Thus, by the capacitor 98 of the inverter output V _c rises slowly. V _c by the falling edge of the input pulse to output the STC is sampled (sampling) and the holding (hold). Thus, the first (k-1) segment of the output STC system is 1, and the (k+1) segment is 0, and the kth segment of the boundary becomes the intermediate analog voltage.

In the present embodiment, the capacitor 98 having a larger input pulse width is charged to 1, and more bits of the STC output are set to 1. In addition, the capacitor 98 used here is a small MOS capacitor (Metal-Oxide-Semiconductor capacitor) composed of only ten transistors.

The PWCO 11 inputs a total of three pulse signals of the UP pulse signal and the DN pulse signal from the PFD 3 and the output pulse signal of the PWACC 5 . In the PWCO 11, each signal is converted into three STCs by three TSTCs 71.

The pulse from PWACC5 is converted to a 6-bit STC. On the other hand, the UP pulse signal and the DN pulse signal are only very short pulses that the PFD3 emits in order to avoid the dead zone when the PWPLL 1 is locked, and thus are converted into a 3-bit STC.

As shown in FIG. 7, each STC node is connected to a transistor 75, 79 or 83 in which the load capacity of the ring oscillator constituted by the inverter 73 is variable.

As the pulse width of the DN pulse signal or the integrated signal output by PWACC5 increases, the number of bits of 1 of the STC increases. This part turns ON the NMOS transistor, increases the load capacity of the ring oscillator, and reduces the oscillation frequency. On the other hand, as the pulse width of the UP pulse signal increases, the PMOS transistor is turned off, the load capacity of the ring oscillator is reduced, and the oscillation frequency is increased.

Next, the simulation result of the PWPLL 1 relating to the present embodiment will be described. The circuit was designed in a 0.18mm process, and the transistor level was simulated by hspice. Let the reference frequency be f _ref =43.75 [MHz] and set the division ratio to N=32. A PLL with an output of 1.4 [GHz] is designed. 7.2 [mW] is consumed below the supply voltage of 1.8 [V].

First, the operation of PWACC5 will be described. Fig. 11 is a view showing a state in which the pulse width of the integrated signal output from the PWACC 5 is held when none of the UP pulse signal and the DN pulse signal is input. The output period of PWACC5 is 6.7 [ns]. Know that When the pulse is wound for 300 cycles (2 ms), the variation of the output pulse width is also 2 [ps] or less, and the pulse width can be accurately maintained.

Regarding the loop characteristics of the designed PWPLL1, the gain of _PWCO11 in the simulation is K _PWCO-p = 20 [MHz/ns], K _PWCO-i = 55 [MHz/ns], and the gain of PWACC5 is K _ACC = 0.044. The damping factor at this time is ζ=0.8 from the equation (3) and the loop bandwidth is 2.4 [MHz].

The waveform of the reference input clock of the simulated PWPLL 1 and the divided feedback clock is shown in FIG. The horizontal axis represents the elapsed time [μs], and the vertical axis represents the output voltage [V]. As expected, there is no phase offset and it is locked.

FIG. 13 shows the transient response of the output frequency when the output frequency is changed from 1.4 [GHz] to 1.45 [GHz] by switching the reference frequency to a step shape. The horizontal axis represents the elapsed time [μs], and the vertical axis represents the output frequency [GHz]. Fig. 14 is a view showing temporal changes of the output pulse width of the PWACC 5 at this time. The horizontal axis represents the elapsed time [μs], and the vertical axis represents the output pulse width [ns].

After the lock is disengaged, it is locked again with a reference lock period and around 40 cycles. It can be seen that a large overshoot is considered to cause saturation of the STC of the proportional component of the PWCO 11 due to a large phase change, which occurs due to a decrease in K _PWCO-p .

In the present embodiment, a Type-II PWPLL controlled by a pulse width without using a charge pump or an RC low-pass filter is described. Moreover, on the hspice simulation, a PWPLL that can form a stable zero offset by analog signal processing using the time domain of the pulse width controlled oscillator and the pulse width integrator is shown.

Further, in the present embodiment, the PWACC 5 has a plurality of rise detecting circuits 25 _k , but on the other hand, it may have a configuration of a plurality of fall detecting circuits (an example of the [falling edge detecting circuit] in the present claim).

1‧‧‧PWPLL

3‧‧‧PFD

5‧‧‧PWACC

11‧‧‧PWCO

13‧‧‧dividing circuit

Claims (9)

A phase locked loop circuit is controlled according to a pulse width of an input pulse signal, comprising: a pulse width controlled oscillator according to a pulse width oscillation of an input signal; and an output signal according to the input pulse signal and the pulse width controlled oscillator a phase difference comparator that outputs a phase pulse signal and a DN pulse signal; and a pulse width integrator that generates an integrated signal of the pulse signal according to the UP pulse signal and the DN pulse signal, the pulse width control oscillator is based on the integrated signal The pulse width oscillates and also oscillates according to the pulse width of at least one of the UP pulse signal and the DN pulse signal. For example, the phase-locked loop circuit of claim 1 further includes a delay circuit for delaying each of the two pulse signals. The phase-locked loop circuit of claim 1 or 2, wherein the pulse width integrator has: a circuit that connects the rising edge of the input signal and outputs the rising edge detection circuit of the pulse signal into a ring, or A falling edge detecting circuit that responds to the falling edge of the input signal and outputs a pulse signal is connected in a loop circuit. The phase-locked loop circuit of claim 3, wherein the rising edge detecting circuit or the falling edge detecting circuit has a pulse width amplifier that amplifies a pulse width of the input signal. The phase-locked loop circuit of claim 3, further comprising: counting the number of times the two pulse signals are connected to the looped circuit by the rising edge detecting circuit, or the two pulse signals passing the falling edge A counting circuit for detecting the number of times the circuit is connected to a loop. The phase-locked loop circuit of claim 3, wherein the rising edge detecting circuit or the falling edge detecting circuit further comprises a delay circuit for delaying each of the two pulse signals, wherein the delay circuit uses the two pulse signals The signal of either one of the signals reaches the rising edge detection circuit or the falling edge detection circuit before the rising edge detection circuit or the falling edge detection circuit having the delay circuit is k-conditional (k is a natural number) delay. The phase-locked loop circuit of claim 1 or 2, wherein the pulse width integrator is longer than the last generated integral when the pulse width of the UP pulse signal is longer than the pulse width of the DN pulse signal The pulse width of the signal is also reduced to generate a pulse width of the integrated signal. When the pulse width of the UP pulse signal is shorter than the pulse width of the DN pulse signal, the pulse width of the integrated signal generated last time is increased. The pulse width of the integrated signal is generated. A phase-locked loop circuit comprising a pulse width control oscillator oscillating according to a pulse width of an input pulse signal, the pulse width control oscillator being in addition to a pulse width of two pulse signals of an UP pulse signal and a DN pulse signal, Oscillation is performed as follows: the pulse width of the integrated signal generated by increasing or decreasing the pulse width based on the difference in pulse width between the two pulse signals of the UP pulse signal and the DN pulse signal. An oscillating method is an oscillating method in a phase-locked loop circuit of a pulse width control oscillator according to an input pulse signal, and includes the following steps: pulses of two pulse signals other than the UP pulse signal and the DN pulse signal In addition to the width, it also oscillates according to the pulse width of the integrated signal generated by increasing or decreasing the pulse width based on the difference in pulse width between the two pulse signals of the UP pulse signal and the DN pulse signal.