TWI503950B - Method for fabricating integrated circuit - Google Patents

Description

Manufacturing method of integrated circuit

The present invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating an integrated circuit having a microelectromechanical structure.

The development of Micro Electromechanical System (MEMS) technology has opened up a whole new field of technology and industry, which has been widely used in various microelectronic devices with both electronic and mechanical characteristics, such as pressure sensors and acceleration. Detector and micro microphone.

In addition, in order to reduce the manufacturing cost of MEMS, most of the current Complementary Metal Oxide Semiconductor (CMOS) processes are used to fabricate MEMS to integrate the process of MEMS and its driver circuits. In the process of the conventional CMOS integrated MEMS integrated circuit, a metal layer is usually used as a hard mask to perform an etching process of the dielectric layer of the interconnect structure to form a vibration on the substrate. MEMS.

However, if the metal layer as the hard mask is not cleaned in the subsequent process, it will easily generate an eddy current during the operation of the integrated circuit, thereby causing electrical interference to the MEMS.

In view of the above, an object of the present invention is to provide a method of manufacturing an integrated circuit to improve the performance of a microelectromechanical system.

The present invention provides a method of fabricating an integrated circuit by first providing a conductive substrate having a logic circuit region and a MEMS region, and then forming a first interconnect structure over the MEMS region of the conductive substrate. The first interconnect structure includes a plurality of first dielectric layers and a plurality of first conductive patterns alternately stacked above the MEMS region. Then, an interposer is formed on the first interconnect structure to cover the first conductive patterns. Then, a polysilicon mask layer is formed on the interposer. Wherein, the polysilicon mask layer is an interposer corresponding to the exposed portions of the first conductive patterns. Subsequently, the polysilicon mask layer is used as a mask to remove a portion of the interposer exposed by the polysilicon mask layer and a corresponding portion of the first dielectric layer, and a plurality of openings are formed in the first interconnect structure. Thereafter, a portion of the conductive substrate of the MEMS region is removed.

In an embodiment of the invention, the method further includes forming a plurality of shallow trench isolation (STI) on the conductive substrate.

In one embodiment of the invention, the above is a logic circuit region distributed over the conductive substrate.

In an embodiment of the invention, the shallow trench isolation structure is distributed in the logic circuit region and the MEMS region of the conductive substrate, and when the first dielectric layer is removed, the removal of the micro-electromechanical device is further included. Part of the shallow trench isolation structure in the system area.

In one embodiment of the invention, the method of forming the interposer described above includes first performing a high density chemical vapor deposition process to form a first interposer on the first interconnect structure. Next, a plasma enhanced chemical vapor deposition process is performed to form a second interposer on the first interposer.

In one embodiment of the invention, a plasma enhanced chemical vapor deposition process for forming the second interposer described above includes the use of Tetraethoxy silane (TEOS) as the precursor gas.

In one embodiment of the invention, a method of removing a portion of a MEMS region of a conductive substrate includes passing an etch gas into an opening of the first interconnect structure.

In an embodiment of the invention, the etching gas is sulfur hexafluoride.

In an embodiment of the invention, the polycrystalline germanium mask layer is removed during removal of a portion of the conductive substrate of the MEMS region.

In an embodiment of the invention, after forming the polysilicon mask layer and removing the interposer, the protective layer is further formed on the interposer to cover the polysilicon mask layer.

In one embodiment of the invention, the method of forming the protective layer includes forming an oxide layer on the interposer and then forming a nitride layer on the oxide layer.

In an embodiment of the invention, the material of the oxide layer is, for example, phosphor glass, and the material of the nitride layer is, for example, tantalum nitride.

In an embodiment of the invention, before removing the portion of the interposer, a portion of the protective layer is further removed to expose the polysilicon mask layer.

In an embodiment of the present invention, the method for fabricating the integrated circuit further includes sequentially forming a MOS device and a second interconnect structure in a logic circuit region of the conductive substrate, wherein the second interconnect structure includes sequential A plurality of second dielectric layers and a plurality of second conductive patterns are alternately stacked.

The invention adopts a polysilicon mask layer as a hard mask for subsequently etching the dielectric layer of the interconnect structure by using an etching selectivity ratio between the polysilicon and the oxide, and the polysilicon mask layer can be processed in the process. It is completely removed, so it can be prevented from remaining on the MEMS components, thus improving the performance of the MEMS.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The integrated circuit of the present invention is fabricated by a CMOS process. The following embodiment will be described by way of example of a MEMS integrated circuit in a CMOS circuit, but the present invention is not limited thereto. It will be appreciated by those skilled in the art that the present invention is also applicable to MEMS systems that do not have CMOS circuitry.

1A to 1G are schematic cross-sectional views showing an integrated circuit in a manufacturing process in an embodiment of the present invention. Referring to FIG. 1A, a conductive substrate 110 having a logic circuit region 112 and a MEMS region 114 is first provided, wherein the conductive substrate 110 may be a germanium substrate or a silicon on insulator (SOI) substrate. Next, at least one semiconductor component 120 is formed in the logic circuit region 112 of the conductive substrate 110. In the present embodiment, the semiconductor element 120 is, for example, a Complementary Metal Oxide Semiconductor (CMOS). In detail, when a plurality of semiconductor elements 120 are formed in the logic circuit region 112, the semiconductor elements 120 are separated from each other by a shallow trench isolation (STI) 111.

It is worth mentioning that in the MEMS region 114 of the conductive substrate 110, the shallow trench isolation structure 111 can also be selectively formed, as shown in FIG. 1A. Those skilled in the art can make their own decisions according to actual needs, and the present invention does not impose any restrictions thereon.

Referring to FIG. 1B, a first interconnect structure 130 and a second interconnect structure 140 are formed on the conductive substrate 110, wherein the first interconnect structure 130 is located in the MEMS region 114, and the second interconnect structure 140 is located in the logic. Circuit area. Specifically, the first interconnect structure 130 and the second interconnect structure 140 are simultaneously formed on the conductive substrate 110 in the same process, and the first interconnect structure 130 is sequentially stacked on the conductive substrate 110 in sequence. The plurality of first dielectric layers 132 and the plurality of first conductive patterns 134, and the first conductive patterns 134 located in the adjacent two layers are electrically connected to each other through the via plugs 136. The second interconnecting line 140 includes a plurality of second dielectric layers 142 and a plurality of second conductive patterns 144 alternately stacked on the conductive substrate 110, and the second conductive patterns 144 located in the adjacent two layers are through the via layers. The plugs 146 are electrically connected to each other. In addition, at least a portion of the second conductive pattern 144 is electrically connected to the semiconductor device 120 through the via plug 146.

Referring to FIG. 1C , an interposer 150 is formed on the first interconnect structure 130 and the second interconnect structure 140 to cover the first conductive pattern 134 and the second conductive pattern 144 . In this embodiment, the interposer 150 is formed by the first interposer 152 and the second interposer 154, and the first interposer 152 and the second interposer 154 are sequentially stacked on the first interconnect structure 130. And the second interconnect structure 140. Specifically, the step of forming the interposer 150 is, for example, first performing a High Density Plasma Chemical Vapor Deposition (HDPCVD) process for the first interconnect structure 130 and the second interconnect structure. A first interposer 152 is formed on 140. Then, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process is performed to form a second interposer 154 on the first interposer 152. In the present embodiment, the material of the second interposer 154 is, for example, ruthenium oxide, and in the deposition process, for example, tetraethoxy decane (TOES) is used as a precursor gas.

Referring to FIG. 1D, a polysilicon capping layer 160 is formed on the interposer 150 above the first interconnect structure 130, wherein the polysilicon capping layer 160 is an interposer 150 corresponding to the exposed portion of the first conductive pattern 134. Here, the interposer 150 is used, for example, to increase the degree of bonding between the polysilicon cap layer 160 and the first interconnect structure 130.

In particular, the present embodiment also forms a protective layer 170 over the interposer 150 to cover the polysilicon cap layer 160. The method for forming the protective layer 170 is, for example, first forming an oxide layer 172 on the interposer 150 to cover the polysilicon cap layer 160, and then forming a nitride layer 174 on the oxide layer 172. That is, the protective layer 170 of the present embodiment is formed by sequentially stacking the oxide layer 172 and the nitride layer 174, wherein the material of the oxide layer 172 is, for example, phosphosilicate glass (PSG), and The thickness is, for example, 0.5 μm. The material of the nitride layer 174 is, for example, tantalum nitride, and the thickness is, for example, 0.7 μm.

Referring to FIG. 1E, a portion of the protective layer 170 is removed to expose the polysilicon mask layer 160. Specifically, the method of removing a portion of the protective layer 170 is, for example, first forming a patterned photoresist layer (not shown) on the protective layer 170 to define a portion of the protective layer 170 to be removed, and patterning the photoresist. The layer exposes the polysilicon mask layer 160 as a protective layer 170 of the mask removal portion, after which the patterned photoresist layer is removed.

It should be noted that, in this embodiment, before removing a portion of the protective layer 170 above the MEMS region 114, a portion of the protective layer 170 and the interposer 150 above the logic circuit region 112 are removed to expose The second conductive pattern 144 is located at the uppermost layer, and the exposed second conductive patterns 144 are used as the connection pads for electrically connecting the semiconductor component 120 to the external circuit. For example, after exposing the second conductive patterns 144 as connection pads, the semiconductor device 120 on the logic circuit region 112 can be electrically connected to an external circuit for electrical measurement.

After removing a portion of the protective layer 170 above the MEMS region 114, since the polysilicon mask layer 160 has an etch selectivity ratio between the interposer layer 150 and the first dielectric layer 132, the polysilicon mask layer 160 can be followed. As a mask, a portion of the interposer 150 exposed by the polysilicon cap layer 160 and a portion of the first dielectric layer 132 underneath are removed, and a plurality of openings 138 are formed in the first interconnect structure 130, as shown in FIG. 1F. Show. Moreover, in the process of removing a portion of the first dielectric layer 132 to form the opening 138, the portion of the shallow trench isolation structure 111 between the first interconnect structure 130 and the conductive substrate 110 is removed at the same time. A portion of the conductive substrate 110 is exposed.

It is worth mentioning that the first interconnect structure 130 includes a plurality of first dielectric layers 132, that is, in the process of forming the openings 138, the thickness of the first dielectric layer 132 to be removed is much larger than that of the polysilicon. The thickness of the mask layer 160. Therefore, the polysilicon mask layer 160 may be simultaneously removed during the etching process of the first dielectric layer 132.

In other embodiments, the etching selectivity between the polysilicon mask layer 160 and the first dielectric layer 132 can also be adjusted, so that the polysilicon mask layer remains after the etching process of the first dielectric layer 132 is performed. 160.

Referring to FIG. 1G, a portion of the conductive substrate 110 of the MEMS region 114 is removed such that a portion of the first interconnect structure 130 is suspended over the conductive substrate 110 as a microelectromechanical device, which substantially completes the semiconductor component and micro The process of the integrated circuit of the electromechanical component. It should be noted that if the polysilicon mask layer 160 remains on a portion of the interposer 150 after the etching process of the first dielectric layer 132, the portion of the conductive substrate 110 of the MEMS region 114 may be removed. At the same time, the polysilicon mask layer 160 is removed.

Specifically, a portion of the first interconnect structure 130 of the present embodiment is suspended above the conductive substrate 110 in a cantilever manner as a microelectromechanical accelerometer, but the invention is not limited thereto.

In summary, the present invention first forms an interposer on the interconnect structure to cover the uppermost conductive pattern of the interconnect structure, and then forms a polysilicon cap layer on the interposer by polysilicon and oxidation. The etching selectivity between the materials is performed by using a polysilicon mask layer as a hard mask for subsequently etching the dielectric layer of the interconnect structure. Since the polysilicon mask layer can be completely removed during the process, it can be prevented from remaining on the MEMS element and affecting the performance of the MEMS element. It can be seen that the present invention can effectively improve the operational efficiency of the MEMS.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

110. . . Conductive substrate

111. . . Shallow trench isolation structure

112. . . Logic circuit area

114. . . MEMS area

120. . . Semiconductor component

130. . . First interconnect structure

132. . . First dielectric layer

134. . . First conductive pattern

136, 146. . . Interlayer plug

138. . . Opening

140. . . Second interconnect structure

142. . . Second dielectric layer

144. . . Second conductive pattern

150. . . Intermediary layer

152. . . First intermediation layer

154. . . Second interposer

160. . . Polycrystalline enamel mask

170. . . The protective layer

172. . . Oxide layer

174. . . Nitride layer

1A to 1G are schematic cross-sectional views showing an integrated circuit in a manufacturing process in an embodiment of the present invention.

110. . . Conductive substrate

111. . . Shallow trench isolation structure

112. . . Logic circuit area

114. . . MEMS area

120. . . Semiconductor component

130. . . First interconnect structure

132. . . First dielectric layer

134. . . First conductive pattern

136, 146. . . Interlayer plug

140. . . Second interconnect structure

142. . . Second dielectric layer

144. . . Second conductive pattern

150. . . Intermediary layer

152. . . First intermediation layer

154. . . Second interposer

160. . . Polycrystalline enamel mask

170. . . The protective layer

172. . . Oxide layer

174. . . Nitride layer

Claims (15)

A method of manufacturing an integrated circuit, comprising: providing a conductive substrate, wherein the conductive substrate has a logic circuit region and a MEMS region; forming a first interconnect structure on the MEMS region of the conductive substrate The first interconnect structure includes a plurality of first dielectric layers and a plurality of first conductive patterns, and the first dielectric layers and the first conductive patterns are alternately stacked on the MEMS region of the conductive substrate. Forming an interposer on the first interconnect structure to cover the first conductive patterns; forming a polysilicon mask layer on the interposer, wherein the polysilicon mask layer corresponds to the first conductive patterns Exposing a portion of the interposer; masking the polysilicon mask layer, removing a portion of the interposer exposed by the polysilicon mask layer and corresponding portions of the first dielectric layers, and at the first Forming a plurality of openings in the interconnect structure; and removing a portion of the conductive substrate of the MEMS region. The method for manufacturing an integrated circuit according to claim 1, further comprising forming a plurality of shallow trench isolation structures on the conductive substrate. The method of manufacturing an integrated circuit according to claim 2, wherein the shallow trench isolation structures are distributed in the logic circuit region. The method of manufacturing an integrated circuit according to claim 2, wherein the shallow trench isolation structures are distributed in the logic circuit region and the MEMS region. The method of manufacturing the integrated circuit of claim 4, wherein when removing a portion of the first dielectric layers, further comprising removing one of the shallow trench isolation structures distributed in the MEMS region Part. The method for manufacturing an integrated circuit according to claim 1, wherein the method for forming the interposer comprises: performing a high-density plasma chemical vapor deposition process to form a first interconnect structure a first interposer; and performing a plasma enhanced chemical vapor deposition process to form a second interposer on the first interposer. The method of manufacturing an integrated circuit according to claim 6, wherein in the plasma enhanced chemical vapor deposition process, tetraethoxy decane is introduced as a precursor gas. The method of manufacturing an integrated circuit according to claim 1, wherein the method of removing a portion of the conductive substrate of the MEMS region comprises passing an etching gas into the openings of the first interconnect structure Inside. The method of manufacturing an integrated circuit according to claim 1, wherein the etching gas comprises sulfur hexafluoride. The method of manufacturing an integrated circuit according to claim 1, further comprising removing the polysilicon mask layer when removing the conductive substrate from the portion of the MEMS region. The method of manufacturing an integrated circuit according to claim 1, wherein after forming the polysilicon mask layer and before removing the interposer, forming a protective layer on the interposer and covering The polysilicon mask layer. The method of manufacturing the integrated circuit of claim 11, wherein the method of forming the protective layer comprises: forming an oxide layer on the interposer to cover the polysilicon mask layer; and the oxide layer A nitride layer is formed thereon. The method for manufacturing an integrated circuit according to claim 11, wherein the material of the oxide layer comprises bismuth phosphorous glass, and the material of the nitride layer comprises tantalum nitride. The method of manufacturing an integrated circuit according to claim 11, wherein before removing the portion of the interposer, the portion of the protective layer is further removed to expose the polysilicon mask layer. The manufacturing method of the integrated circuit of claim 1, further comprising forming at least one semiconductor component and a second interconnecting structure in the logic circuit region of the conductive substrate, wherein the second interconnect The wire structure is electrically connected to the semiconductor component, and the second interconnect structure comprises a plurality of second dielectric layers and a plurality of second conductive patterns alternately stacked in sequence.