TWI503950B - Method for fabricating integrated circuit - Google Patents
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Description
本發明是有關於一種積體電路的製造方法,且特別是有關於一種具有微機電結構的積體電路製造方法。The present invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating an integrated circuit having a microelectromechanical structure.
微機電系統(Micro Electromechanical System,MEMS)技術的發展開闢了一個全新的技術領域和產業,其已被廣泛地應用於各種具有電子與機械雙重特性之微電子裝置中,例如壓力感應器、加速度感測器與微型麥克風等。The development of Micro Electromechanical System (MEMS) technology has opened up a whole new field of technology and industry, which has been widely used in various microelectronic devices with both electronic and mechanical characteristics, such as pressure sensors and acceleration. Detector and micro microphone.
此外,為降低微機電系統的製作成本,目前大多採用互補金氧半導體(Complementary Metal Oxide Semiconductor,CMOS)製程來製作微機電系統,以整合微機電系統與其驅動電路的製程。在習知CMOS整合微機電系統之積體電路的製程中,通常是使用金屬層作為硬罩幕(hard mask)來進行內連線結構之介電層的蝕刻製程,以形成可在基底上振動的微機電系統。In addition, in order to reduce the manufacturing cost of MEMS, most of the current Complementary Metal Oxide Semiconductor (CMOS) processes are used to fabricate MEMS to integrate the process of MEMS and its driver circuits. In the process of the conventional CMOS integrated MEMS integrated circuit, a metal layer is usually used as a hard mask to perform an etching process of the dielectric layer of the interconnect structure to form a vibration on the substrate. MEMS.
然而,作為硬罩幕的金屬層在後續製程中若未能清除乾淨,將容易在積體電路作動的過程中產生渦電流(eddy current),進而對微機電系統造成電性干擾。However, if the metal layer as the hard mask is not cleaned in the subsequent process, it will easily generate an eddy current during the operation of the integrated circuit, thereby causing electrical interference to the MEMS.
有鑑於此,本發明的目的就是在提供一種積體電路的製造方法,以提高微機電系統的效能。In view of the above, an object of the present invention is to provide a method of manufacturing an integrated circuit to improve the performance of a microelectromechanical system.
本發明提出一種積體電路的製造方法,其係先提供具有邏輯電路區與微機電系統區的導電基底,接著在導電基底的微機電系統區上方形成第一內連線結構。其中,此第一內連線結構包括依序交替堆疊在微機電系統區上方的多層第一介電層與多個第一導電圖案。再來,在第一內連線結構上形成一層中介層以覆蓋這些第一導電圖案。然後,在中介層上形成一層多晶矽罩幕層。其中,多晶矽罩幕層是對應至這些第一導電圖案而暴露出部分之中介層。接續,以多晶矽罩幕層為遮罩,移除多晶矽罩幕層所暴露出之部分中介層以及對應之部分第一介電層,而在第一內連線結構中形成多個開口。之後,移除微機電系統區的部分導電基底。The present invention provides a method of fabricating an integrated circuit by first providing a conductive substrate having a logic circuit region and a MEMS region, and then forming a first interconnect structure over the MEMS region of the conductive substrate. The first interconnect structure includes a plurality of first dielectric layers and a plurality of first conductive patterns alternately stacked above the MEMS region. Then, an interposer is formed on the first interconnect structure to cover the first conductive patterns. Then, a polysilicon mask layer is formed on the interposer. Wherein, the polysilicon mask layer is an interposer corresponding to the exposed portions of the first conductive patterns. Subsequently, the polysilicon mask layer is used as a mask to remove a portion of the interposer exposed by the polysilicon mask layer and a corresponding portion of the first dielectric layer, and a plurality of openings are formed in the first interconnect structure. Thereafter, a portion of the conductive substrate of the MEMS region is removed.
在本發明之一實施例中,更包括在導電基底上形成多個淺溝渠隔離結構(shallow trench isolation,STI)。In an embodiment of the invention, the method further includes forming a plurality of shallow trench isolation (STI) on the conductive substrate.
在本發明之一實施例中,上述之是分佈在導電基底的邏輯電路區。In one embodiment of the invention, the above is a logic circuit region distributed over the conductive substrate.
在本發明之一實施例中,上述之淺溝渠隔離結構是分佈在導電基底的邏輯電路區與微機電系統區,且在移除部分的第一介電層時,更包括移除位於微機電系統區內的部分淺溝渠隔離結構。In an embodiment of the invention, the shallow trench isolation structure is distributed in the logic circuit region and the MEMS region of the conductive substrate, and when the first dielectric layer is removed, the removal of the micro-electromechanical device is further included. Part of the shallow trench isolation structure in the system area.
在本發明之一實施例中,形成上述之中介層的方法包括先進行高密度化學氣相沈積製程,以於第一內連線結構上形成第一中介層。接著,進行電漿加強式化學氣相沈積製程,以於第一中介層上形成第二中介層。In one embodiment of the invention, the method of forming the interposer described above includes first performing a high density chemical vapor deposition process to form a first interposer on the first interconnect structure. Next, a plasma enhanced chemical vapor deposition process is performed to form a second interposer on the first interposer.
在本發明之一實施例中,在形成上述之第二中介層的電漿加強式化學氣相沈積製程中,包括使用四乙氧基矽烷(Tetraethoxy silane,TEOS)作為前驅氣體。In one embodiment of the invention, a plasma enhanced chemical vapor deposition process for forming the second interposer described above includes the use of Tetraethoxy silane (TEOS) as the precursor gas.
在本發明之一實施例中,移除上述導電基底之部分微機電系統區的方法包括將蝕刻氣體通入上述第一內連線結構的開口內。In one embodiment of the invention, a method of removing a portion of a MEMS region of a conductive substrate includes passing an etch gas into an opening of the first interconnect structure.
在本發明之一實施例中,上述之蝕刻氣體為六氟化硫。In an embodiment of the invention, the etching gas is sulfur hexafluoride.
在本發明之一實施例中,更包括在移除上述之微機電系統區的部分導電基底時,移除上述之多晶矽罩幕層。In an embodiment of the invention, the polycrystalline germanium mask layer is removed during removal of a portion of the conductive substrate of the MEMS region.
在本發明之一實施例中,於形成上述之多晶矽罩幕層之後以及移除部分之中介層之前,更包括在中介層上形成保護層覆蓋多晶矽罩幕層。In an embodiment of the invention, after forming the polysilicon mask layer and removing the interposer, the protective layer is further formed on the interposer to cover the polysilicon mask layer.
在本發明之一實施例中,形成上述之保護層的方法包括先在中介層上形成氧化層,接著再於氧化層上形成氮化層。In one embodiment of the invention, the method of forming the protective layer includes forming an oxide layer on the interposer and then forming a nitride layer on the oxide layer.
在本發明之一實施例中,上述之氧化層的材質例如是磷矽玻璃,氮化層的材質例如是氮化矽。In an embodiment of the invention, the material of the oxide layer is, for example, phosphor glass, and the material of the nitride layer is, for example, tantalum nitride.
在本發明之一實施例中,在移除部分之中介層前,更包括移除部分之保護層,以暴露出上述之多晶矽罩幕層。In an embodiment of the invention, before removing the portion of the interposer, a portion of the protective layer is further removed to expose the polysilicon mask layer.
在本發明之一實施例中,上述積體電路的製造方法更包括在導電基底之邏輯電路區依序形成金氧半導體元件與第二內連線結構,其中第二內連線結構包括依序交替堆疊的多層第二介電層以及多個第二導電圖案。In an embodiment of the present invention, the method for fabricating the integrated circuit further includes sequentially forming a MOS device and a second interconnect structure in a logic circuit region of the conductive substrate, wherein the second interconnect structure includes sequential A plurality of second dielectric layers and a plurality of second conductive patterns are alternately stacked.
本發明是藉由多晶矽與氧化物之間的蝕刻選擇比,利用多晶矽罩幕層作為後續蝕刻內連線結構之介電層的硬遮罩(hard mask),且因多晶矽罩幕層可在製程中完全被移除,所以可避免其殘留在微機電元件上,進而改善微機電系統的運作效能。The invention adopts a polysilicon mask layer as a hard mask for subsequently etching the dielectric layer of the interconnect structure by using an etching selectivity ratio between the polysilicon and the oxide, and the polysilicon mask layer can be processed in the process. It is completely removed, so it can be prevented from remaining on the MEMS components, thus improving the performance of the MEMS.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下。The above and other objects, features and advantages of the present invention will become more <RTIgt;
本發明之積體電路係採用CMOS製程製作而成,以下實施例將舉整合至CMOS電路中的微機電系統為例做說明,但本發明不限於此。熟習此技藝者應該知道,本發明也可應用於不具有CMOS電路的微機電系統中。The integrated circuit of the present invention is fabricated by a CMOS process. The following embodiment will be described by way of example of a MEMS integrated circuit in a CMOS circuit, but the present invention is not limited thereto. It will be appreciated by those skilled in the art that the present invention is also applicable to MEMS systems that do not have CMOS circuitry.
圖1A至圖1G繪示本發明之一實施例中積體電路於製造流程中的剖面示意圖。請參照圖1A,首先提供具有邏輯電路區112與微機電系統區114的導電基底110,其中導電基底110可以是矽基底或絕緣層上矽(silicon on insulator,SOI)基底。接著,於導電基底110之邏輯電路區112內形成至少一個半導體元件120。在本實施例中,半導體元件120例如是互補金氧半導體元件(Complementary Metal Oxide Semiconductor,CMOS)。詳細來說,當邏輯電路區112內形成有多個半導體元件120時,各半導體元件120係以淺溝渠隔離結構(shallow trench isolation,STI)111彼此相隔。1A to 1G are schematic cross-sectional views showing an integrated circuit in a manufacturing process in an embodiment of the present invention. Referring to FIG. 1A, a conductive substrate 110 having a logic circuit region 112 and a MEMS region 114 is first provided, wherein the conductive substrate 110 may be a germanium substrate or a silicon on insulator (SOI) substrate. Next, at least one semiconductor component 120 is formed in the logic circuit region 112 of the conductive substrate 110. In the present embodiment, the semiconductor element 120 is, for example, a Complementary Metal Oxide Semiconductor (CMOS). In detail, when a plurality of semiconductor elements 120 are formed in the logic circuit region 112, the semiconductor elements 120 are separated from each other by a shallow trench isolation (STI) 111.
值得一提的是,在導電基底110的微機電系統區114內,也可以選擇性地形成淺溝渠隔離結構111,如圖1A所示。熟習此技藝者可自行依實際需求決定,本發明不在此做任何限制。It is worth mentioning that in the MEMS region 114 of the conductive substrate 110, the shallow trench isolation structure 111 can also be selectively formed, as shown in FIG. 1A. Those skilled in the art can make their own decisions according to actual needs, and the present invention does not impose any restrictions thereon.
請參照圖1B,在導電基底110形成第一內連線結構130與第二內連線結構140,其中第一內連線結構130位於微機電系統區114,第二內連線結構140位於邏輯電路區。具體來說,第一內連線結構130與第二內連線結構140是在同一製程中同時形成於導電基底110上,且第一內連線結構130包括依序交替堆疊在導電基底110上的多層第一介電層132與多個第一導電圖案134,而位於相鄰兩層的第一導電圖案134是透過介層插塞136彼此電性連接。第二內連線140則包括依序交替堆疊在導電基底110上的多層第二介電層142與多個第二導電圖案144,且位於相鄰兩層的第二導電圖案144是透過介層插塞146彼此電性連接。此外,至少有一部份的第二導電圖案144是透過介層插塞146電性連接至半導體元件120。Referring to FIG. 1B, a first interconnect structure 130 and a second interconnect structure 140 are formed on the conductive substrate 110, wherein the first interconnect structure 130 is located in the MEMS region 114, and the second interconnect structure 140 is located in the logic. Circuit area. Specifically, the first interconnect structure 130 and the second interconnect structure 140 are simultaneously formed on the conductive substrate 110 in the same process, and the first interconnect structure 130 is sequentially stacked on the conductive substrate 110 in sequence. The plurality of first dielectric layers 132 and the plurality of first conductive patterns 134, and the first conductive patterns 134 located in the adjacent two layers are electrically connected to each other through the via plugs 136. The second interconnecting line 140 includes a plurality of second dielectric layers 142 and a plurality of second conductive patterns 144 alternately stacked on the conductive substrate 110, and the second conductive patterns 144 located in the adjacent two layers are through the via layers. The plugs 146 are electrically connected to each other. In addition, at least a portion of the second conductive pattern 144 is electrically connected to the semiconductor device 120 through the via plug 146.
請參照圖1C,在第一內連線結構130與第二內連線結構140上形成中介層150而覆蓋第一導電圖案134與第二導電圖案144。在本實施例中,中介層150例如是由第一中介層152與第二中介層154所構成,且第一中介層152與第二中介層154是依序堆疊於第一內連線結構130及第二內連線結構140上。具體來說,形成中介層150的步驟例如是先進行高密度電漿化學氣相沈積(High Density Plasma Chemical Vapor Deposition,HDPCVD)製程,以於第一內連線結構130與第二內連線結構140上形成第一中介層152。然後,進行電漿加強式化學氣相沈積(Plasma Enhanced Chemical Vapor Deposition,PECVD)製程,以於第一中介層152上形成第二中介層154。在本實施例中,第二中介層154的材質例如是氧化矽,且在沈積製程中其例如是以四乙氧基矽烷(TOES)作為前驅氣體。Referring to FIG. 1C , an interposer 150 is formed on the first interconnect structure 130 and the second interconnect structure 140 to cover the first conductive pattern 134 and the second conductive pattern 144 . In this embodiment, the interposer 150 is formed by the first interposer 152 and the second interposer 154, and the first interposer 152 and the second interposer 154 are sequentially stacked on the first interconnect structure 130. And the second interconnect structure 140. Specifically, the step of forming the interposer 150 is, for example, first performing a High Density Plasma Chemical Vapor Deposition (HDPCVD) process for the first interconnect structure 130 and the second interconnect structure. A first interposer 152 is formed on 140. Then, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process is performed to form a second interposer 154 on the first interposer 152. In the present embodiment, the material of the second interposer 154 is, for example, ruthenium oxide, and in the deposition process, for example, tetraethoxy decane (TOES) is used as a precursor gas.
接著請參照圖1D,在第一內連線結構130上方的中介層150上形成多晶矽罩幕層160,其中多晶矽罩幕層160是對應至第一導電圖案134而暴露出部分的中介層150。在此,中介層150例如是用以增加多晶矽罩幕層160與第一內連線結構130之間的接合度。Referring to FIG. 1D, a polysilicon capping layer 160 is formed on the interposer 150 above the first interconnect structure 130, wherein the polysilicon capping layer 160 is an interposer 150 corresponding to the exposed portion of the first conductive pattern 134. Here, the interposer 150 is used, for example, to increase the degree of bonding between the polysilicon cap layer 160 and the first interconnect structure 130.
特別的是,本實施例還在中介層150上形成保護層170而覆蓋住多晶矽罩幕層160。其中,保護層170的形成方法例如是先在中介層150上形成氧化物層172以覆蓋多晶矽罩幕層160,之後再於氧化物層172上形成氮化物層174。也就是說,本實施例之保護層170例如是由氧化物層172與氮化物層174依序堆疊而成,其中氧化物層172的材質例如是磷矽玻璃(phosphosilicate glass,PSG),且其厚度例如是0.5微米。氮化物層174的材質則例如是氮化矽,且厚度例如是0.7微米。In particular, the present embodiment also forms a protective layer 170 over the interposer 150 to cover the polysilicon cap layer 160. The method for forming the protective layer 170 is, for example, first forming an oxide layer 172 on the interposer 150 to cover the polysilicon cap layer 160, and then forming a nitride layer 174 on the oxide layer 172. That is, the protective layer 170 of the present embodiment is formed by sequentially stacking the oxide layer 172 and the nitride layer 174, wherein the material of the oxide layer 172 is, for example, phosphosilicate glass (PSG), and The thickness is, for example, 0.5 μm. The material of the nitride layer 174 is, for example, tantalum nitride, and the thickness is, for example, 0.7 μm.
請參照圖1E,移除部分的保護層170,以暴露出多晶矽罩幕層160。具體來說,移除部分保護層170的方法例如是先在保護層170上形成一層圖案化光阻層(圖未示)來定義出保護層170欲移除之部分,並以圖案化光阻層作為遮罩移除部分的保護層170而暴露出多晶矽罩幕層160,之後再將圖案化光阻層移除。Referring to FIG. 1E, a portion of the protective layer 170 is removed to expose the polysilicon mask layer 160. Specifically, the method of removing a portion of the protective layer 170 is, for example, first forming a patterned photoresist layer (not shown) on the protective layer 170 to define a portion of the protective layer 170 to be removed, and patterning the photoresist. The layer exposes the polysilicon mask layer 160 as a protective layer 170 of the mask removal portion, after which the patterned photoresist layer is removed.
值得一提的是,本實施例還可以在移除位於微機電系統區114上方之部分保護層170前,先移除位於邏輯電路區112上方的部分保護層170及中介層150,以暴露出部分位於最上層的第二導電圖案144,而這些暴露出之第二導電圖案144即是用以作為半導體元件120與外部電路電性連接的連接墊。舉例來說,將這些作為連接墊的第二導電圖案144暴露出之後,即可使邏輯電路區112上的半導體元件120電性連接至外部電路,以進行電性測量。It should be noted that, in this embodiment, before removing a portion of the protective layer 170 above the MEMS region 114, a portion of the protective layer 170 and the interposer 150 above the logic circuit region 112 are removed to expose The second conductive pattern 144 is located at the uppermost layer, and the exposed second conductive patterns 144 are used as the connection pads for electrically connecting the semiconductor component 120 to the external circuit. For example, after exposing the second conductive patterns 144 as connection pads, the semiconductor device 120 on the logic circuit region 112 can be electrically connected to an external circuit for electrical measurement.
在移除位於微機電系統區114上方之部分保護層170後,由於多晶矽罩幕層160與中介層150及第一介電層132之間具有蝕刻選擇比,因此可接著以多晶矽罩幕層160為遮罩,移除多晶矽罩幕層160所暴露出的部分中介層150以及下方的部分第一介電層132,而在第一內連線結構130內形成多個開口138,如圖1F所示。而且,本實施例在移除部分第一介電層132以形成開口138的製程中,更同時移除位於第一內連線結構130與導電基底110之間的部分淺溝渠隔離結構111,以暴露出部分的導電基底110。After removing a portion of the protective layer 170 above the MEMS region 114, since the polysilicon mask layer 160 has an etch selectivity ratio between the interposer layer 150 and the first dielectric layer 132, the polysilicon mask layer 160 can be followed. As a mask, a portion of the interposer 150 exposed by the polysilicon cap layer 160 and a portion of the first dielectric layer 132 underneath are removed, and a plurality of openings 138 are formed in the first interconnect structure 130, as shown in FIG. 1F. Show. Moreover, in the process of removing a portion of the first dielectric layer 132 to form the opening 138, the portion of the shallow trench isolation structure 111 between the first interconnect structure 130 and the conductive substrate 110 is removed at the same time. A portion of the conductive substrate 110 is exposed.
值得一提的是,第一內連線結構130包括多層第一介電層132,也就是說,在形成開口138的製程中,所需移除之第一介電層132的厚度遠大於多晶矽罩幕層160的厚度。因此,多晶矽罩幕層160可能在第一介電層132的蝕刻製程中同時被移除。It is worth mentioning that the first interconnect structure 130 includes a plurality of first dielectric layers 132, that is, in the process of forming the openings 138, the thickness of the first dielectric layer 132 to be removed is much larger than that of the polysilicon. The thickness of the mask layer 160. Therefore, the polysilicon mask layer 160 may be simultaneously removed during the etching process of the first dielectric layer 132.
在其他實施例中,也可以藉由調整多晶矽罩幕層160與第一介電層132之間的蝕刻選擇比,使得在進行第一介電層132的蝕刻製程之後仍留有多晶矽罩幕層160。In other embodiments, the etching selectivity between the polysilicon mask layer 160 and the first dielectric layer 132 can also be adjusted, so that the polysilicon mask layer remains after the etching process of the first dielectric layer 132 is performed. 160.
請參照圖1G,移除微機電系統區114的部分導電基底110,以使部分的第一內連線結構130懸在導電基底110上方而作為微機電元件,此即大致完成包含半導體元件及微機電元件的積體電路之製程。需要注意的是,若多晶矽罩幕層160在第一介電層132的蝕刻製程後仍留在部分的中介層150上,則可在移除微機電系統區114的部分導電基底110的過程中,同時移除多晶矽罩幕層160。Referring to FIG. 1G, a portion of the conductive substrate 110 of the MEMS region 114 is removed such that a portion of the first interconnect structure 130 is suspended over the conductive substrate 110 as a microelectromechanical device, which substantially completes the semiconductor component and micro The process of the integrated circuit of the electromechanical component. It should be noted that if the polysilicon mask layer 160 remains on a portion of the interposer 150 after the etching process of the first dielectric layer 132, the portion of the conductive substrate 110 of the MEMS region 114 may be removed. At the same time, the polysilicon mask layer 160 is removed.
具體來說,本實施例之部分第一內連線結構130例如是以懸臂樑的方式懸於導電基底110上方,以作為微機電加速計,但本發明並不限於此。Specifically, a portion of the first interconnect structure 130 of the present embodiment is suspended above the conductive substrate 110 in a cantilever manner as a microelectromechanical accelerometer, but the invention is not limited thereto.
綜上所述,本發明是先在內連線結構上形成一層中介層,以覆蓋內連線結構最上層的導電圖案,之後再於中介層上形成一層多晶矽罩幕層,藉由多晶矽與氧化物之間的蝕刻選擇比,利用多晶矽罩幕層作為後續蝕刻內連線結構之介電層的硬遮罩(hard mask)。由於多晶矽罩幕層可在製程中完全被移除,因此可避免其殘留在微機電元件上而影響微機電元件的效能。由此可知,本發明可有效地改善微機電系統的運作效能。In summary, the present invention first forms an interposer on the interconnect structure to cover the uppermost conductive pattern of the interconnect structure, and then forms a polysilicon cap layer on the interposer by polysilicon and oxidation. The etching selectivity between the materials is performed by using a polysilicon mask layer as a hard mask for subsequently etching the dielectric layer of the interconnect structure. Since the polysilicon mask layer can be completely removed during the process, it can be prevented from remaining on the MEMS element and affecting the performance of the MEMS element. It can be seen that the present invention can effectively improve the operational efficiency of the MEMS.
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
110...導電基底110. . . Conductive substrate
111...淺溝渠隔離結構111. . . Shallow trench isolation structure
112...邏輯電路區112. . . Logic circuit area
114...微機電系統區114. . . MEMS area
120...半導體元件120. . . Semiconductor component
130...第一內連線結構130. . . First interconnect structure
132...第一介電層132. . . First dielectric layer
134...第一導電圖案134. . . First conductive pattern
136、146...介層插塞136, 146. . . Interlayer plug
138...開口138. . . Opening
140...第二內連線結構140. . . Second interconnect structure
142...第二介電層142. . . Second dielectric layer
144...第二導電圖案144. . . Second conductive pattern
150...中介層150. . . Intermediary layer
152...第一中介層152. . . First intermediation layer
154...第二中介層154. . . Second interposer
160...多晶矽罩幕層160. . . Polycrystalline enamel mask
170...保護層170. . . The protective layer
172...氧化物層172. . . Oxide layer
174...氮化物層174. . . Nitride layer
圖1A至圖1G繪示本發明之一實施例中積體電路於製造流程中的剖面示意圖。1A to 1G are schematic cross-sectional views showing an integrated circuit in a manufacturing process in an embodiment of the present invention.
110...導電基底110. . . Conductive substrate
111...淺溝渠隔離結構111. . . Shallow trench isolation structure
112...邏輯電路區112. . . Logic circuit area
114...微機電系統區114. . . MEMS area
120...半導體元件120. . . Semiconductor component
130...第一內連線結構130. . . First interconnect structure
132...第一介電層132. . . First dielectric layer
134...第一導電圖案134. . . First conductive pattern
136、146...介層插塞136, 146. . . Interlayer plug
140...第二內連線結構140. . . Second interconnect structure
142...第二介電層142. . . Second dielectric layer
144...第二導電圖案144. . . Second conductive pattern
150...中介層150. . . Intermediary layer
152...第一中介層152. . . First intermediation layer
154...第二中介層154. . . Second interposer
160...多晶矽罩幕層160. . . Polycrystalline enamel mask
170...保護層170. . . The protective layer
172...氧化物層172. . . Oxide layer
174...氮化物層174. . . Nitride layer
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US20060105543A1 (en) * | 2004-11-12 | 2006-05-18 | Fu-Yuan Xiao | CMOS-MEMS process |
US20090090693A1 (en) * | 2007-10-05 | 2009-04-09 | Pixart Imaging Inc. | Method for fabricating micromachined structures |
US20090243004A1 (en) * | 2008-03-27 | 2009-10-01 | Bang-Chiang Lan | Integrated structure for MEMS device and semiconductor device and method of fabricating the same |
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US20060105543A1 (en) * | 2004-11-12 | 2006-05-18 | Fu-Yuan Xiao | CMOS-MEMS process |
US20090090693A1 (en) * | 2007-10-05 | 2009-04-09 | Pixart Imaging Inc. | Method for fabricating micromachined structures |
US20090243004A1 (en) * | 2008-03-27 | 2009-10-01 | Bang-Chiang Lan | Integrated structure for MEMS device and semiconductor device and method of fabricating the same |
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