TWI498984B - Fine pitch arrangement structur of pillar bumps on chip - Google Patents

Description

Fine pitch arrangement of columnar bumps on a wafer

The present invention relates to a bump structure for a semiconductor wafer, and more particularly to a fine pitch arrangement of a columnar bump on a wafer.

Most of the known semiconductor wafer products (such as DRAM devices) have been switched from wire bonding to flip chip bonding, and their wafer patterns have also moved toward wafer level wafer size packaging. However, as the wafer is shrunk and the pad gap is miniaturized, it is more difficult to fabricate fine-pitch solder-bonded columnar bumps (for example, copper pillar bumps CPB) on the pads, and the pads are The pitch is less than 80 microns. When the wafer is bonded, the solder easily bridges the adjacent columnar bumps, and the underfill is difficult to fill the wafer bonding gap. Conventionally, the size of the stud bumps is directly reduced, but the bumps are also affected by the solder soldering area being small and easily broken.

Another conventional method is to elongate the bump into a finger shape and extend it to a single side. For example, National Patent Publication No. 200837912 "Bump-Shaped Wafer Structure", however, the structure is applied to internal pin bonding ( The gold bumps of ILB) are bonded without the risk of solder overflow, and the thin gold bumps of the fingers are extended in a single direction. The unbalanced stress distribution will act on the aluminum pads and be thin. The gold bump of the finger completely covers the opening of the passivation insulating layer, that is, the opening of the bump is larger than the opening of the passivation insulating layer, and the application thereof is different from the problem to be solved when the solder-bonded columnar bump is arranged at a fine pitch Encountered a problem.

In order to solve the above problems, the main object of the present invention is to provide a fine pitch arrangement structure of columnar bumps on a wafer, which can prevent solder bridge short circuit of micro pitch solder joint type column bumps, and a column having a sufficient soldering area. The bumps can be arranged at a fine pitch and aligned on the opening of the insulating layer of the pad to achieve the bonding stress balance and release effect of the micro pitch bumps.

A second object of the present invention is to provide a micro-pitch arrangement of columnar bumps on a wafer for improving the conventional bumps on the active surface of the wafer and the columnar bumps having different functions on the composite insulating layer. Highly inconsistent issues.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a fine pitch arrangement of columnar bumps on a wafer, comprising a wafer, an insulating layer, a first stud bump and a second stud bump. The active surface of the wafer is provided with a first bonding pad and a second bonding pad arranged on an X axis. The insulating layer is formed on the active surface of the wafer, and the insulating layer has a first opening and a second opening in a first aspect ratio, wherein a center point of the first opening One of the center points to the second opening is defined on the X axis and is not greater than 80 microns, and a first Y axis and a second Y axis are parallel to each other and perpendicular to the X axis, and the first A center point of an opening is located on the first Y axis, and a center point of the second opening is located on the second Y axis. The first stud bump is disposed on the first pad, and the first stud bump includes a first pillar portion and a first solder layer. The second stud bump is disposed on the second solder pad, and the second stud bump includes a second pillar portion and a second solder layer. Wherein, the first column portion has a plurality of first symmetrical padding blocks extending to two sides of the first Y axis direction, and the second column portion has a plurality of two to the second Y axis direction a second symmetrically symmetrical block extending laterally, the first symmetry The padding block and the second symmetrical padding block cover the insulating layer, and the first column portion and the second column portion each have a bump shortened along the X axis Width, such that the first pillar portion and the second pillar portion have a second aspect ratio which is at least five times larger than a point of the first aspect ratio, thereby partially exposing the first pad And the second pad, and the center point of the first column portion along the first Y axis is longitudinally aligned with the center point of the first opening, and the center point of the second column portion is longitudinally aligned At the center of the second opening.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the above micro-pitch arrangement, the top surface of the first pillar portion and the second pillar portion may each have a central recess to respectively receive a portion of the first solder layer and the second solder. Layer to reduce the amount of solder spillage after bump bonding.

In the foregoing fine pitch arrangement, the first under bump metal layer and the second under bump metal layer may be further formed on the first pillar portion and the first a partial exposed area of the first pad is not covered between the pads, and the second under bump metal layer is formed between the second pillar portion and the second pad without covering the second solder The partial exposed area of the pad is such that the first exposed pad and the partial exposed area of the second pad are recessed in the corresponding first opening and the second opening to accommodate the solder overflowing the top surface of the columnar bump.

In the foregoing micro-pitch arrangement, the first under bump metal layer and the second under bump metal layer may extend to the first symmetrical padding block and the second symmetrical pad respectively. Below the high block, the bonding force and plating formation of the first symmetric padding block and the second symmetric padding blocks are improved.

In the aforementioned fine pitch arrangement, the first pillar portion and A first barrier layer may be formed between the first solder layer, and a second barrier layer is formed between the second pillar portion and the second solder layer for the first solder layer and the first solder layer The two solder layers are fixed and prevent the solder component from diffusing to the metal of the first pillar portion and the second pillar portion.

In the micro-pitch arrangement, the insulating layer may comprise a basic protective layer and a thickened organic protective layer, and the composite insulating layer may be more than 5 micrometers to improve the insulation and protection of the active surface of the wafer. The effect produces a stress buffering effect of the stud bumps.

In the foregoing micro-pitch arrangement, each of the first symmetric padding block and the second symmetric padding block may be adjacent to the horizontal extension of the first opening and the second opening. Less than 7 microns to expand the symmetrical support of the columnar bumps.

In the foregoing micro-pitch arrangement, the first symmetrical padding block and the second symmetrical padding blocks are used to make the length of the first column portion and the second column portion The distance from the center point of the first opening to the center point of the second opening is not greater than the center point of the first opening to the center of the second opening Seventy-five percent of the distance, that is, the total length of each of the columnar bumps including the symmetric extension on the insulating layer is not less than the distance between the columnar bumps, and the width of each of the columnar bumps is not more than The pitch between the stud bumps is 75%, and the micro-pitch symmetrically extends the narrow refinement stud bump structure.

In the foregoing micro-pitch arrangement, the first symmetrical padding blocks and the second symmetrical padding blocks may have substantially the same shape and size to achieve the columnar bumps in the insulating layer. Fully symmetric extension on the top.

In the above-mentioned fine pitch arrangement, a third columnar bump may be further disposed on the insulating layer, and the third columnar bump includes a third pillar portion and a third solder layer. Where the third cylinder is high The degrees are the same as the heights of the first symmetric padding blocks and the second symmetric padding blocks. The third stud bump can be used as a pair of mark or a wafer leveling joint support point, that is, the stud bump can be directly disposed on the pad without re-distribution distribution.

100‧‧‧Micro-pitch arrangement of columnar bumps on the wafer

101‧‧‧X axis

102‧‧‧First Y-axis

103‧‧‧Second Y axis

110‧‧‧ wafer

111‧‧‧First pad

112‧‧‧Second pad

113‧‧‧Active face

120‧‧‧Insulation

121‧‧‧First opening

122‧‧‧Second opening

123‧‧‧Basic protective layer

124‧‧‧ Thicken organic protective layer

125, 126‧‧‧ opening center point

130‧‧‧First cylindrical bump

131‧‧‧The first cylinder

132‧‧‧First solder layer

133‧‧‧First Symmetrical Height Block

134‧‧‧ central pocket

135‧‧‧First barrier layer

136‧‧‧The center point of the first cylinder

140‧‧‧Second columnar bump

141‧‧‧Second cylinder

142‧‧‧Second solder layer

143‧‧‧Second symmetrical padding block

144‧‧‧ central pocket

145‧‧‧second barrier layer

146‧‧‧ Center point of the second cylinder

151‧‧‧First under bump metal layer

152‧‧‧second under bump metal layer

200‧‧‧Micro-pitch arrangement of columnar bumps on the wafer

253‧‧‧3rd under bump metal layer

260‧‧‧3rd columnar bump

261‧‧‧The third cylinder

262‧‧‧ Third solder layer

263‧‧‧ third barrier layer

Figure 1 is a partial perspective view showing a fine pitch arrangement of columnar bumps on a wafer in accordance with an embodiment of the present invention.

Figure 2 is a cross-sectional view of the fine pitch arrangement of the stud bumps on the wafer taken along line 1 - 2 of Figure 1 in accordance with an embodiment of the present invention.

Figure 3 is a cross-sectional view of the fine pitch arrangement of the stud bumps on the wafer taken along line 3-3 of Figure 1 in accordance with an embodiment of the present invention.

Figure 4: A schematic view of the stud bumps on a micro-pitch arrangement on a wafer in accordance with an embodiment of the present invention.

Figure 5 is a cross-sectional view showing the arrangement of a fine pitch arrangement of another stud bump on a wafer in accordance with a variant embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to an embodiment of the invention, a columnar bump is The micro-pitch arrangement on the wafer is exemplified in a partial perspective view of FIG. 1 , a cross-sectional view taken along line 1 2-2 of FIG. 2, and a cross-section taken along line 3 - 3 of FIG. 3 . The schematic diagram and the top view of Fig. 4 are shown. The micro-pitch arrangement 100 of the stud bumps on the wafer includes a wafer 110, an insulating layer 120, a first stud bump 130, and a second stud bump 140.

The wafer 110 is a semiconductor wafer 110 having an integrated circuit, and the integrated circuit therein can include a memory, such as a dynamic random access memory (DRAM), and is fabricated on the active surface 113 of the wafer 110. The active surface 113 of the wafer 110 is provided with a first pad 111 and a second pad 112 which are arranged on an X-axis 101 as an output input terminal of the integrated circuit.

The insulating layer 120 is formed on the active surface 113 of the wafer 110 for protection of the integrated circuit of the active surface 113. The insulating layer 120 has a first opening 121 and a second opening 122 in a first aspect ratio. For example, the first aspect ratio can be one, that is, the length and width of the opening are about Similarly, the length and width of the first opening 121 and the second opening 122 may range from 30 to 80 micrometers (μm), specifically 42 micrometers. The distance from the center point 125 of the first opening 121 to the center point 126 of the second opening 122 is defined on the X axis 101 and is not more than 80 microns, that is, the first opening 121 and the The second openings 122 are spaced apart on the X-axis 101 by no more than 80 microns. And the two ends of the distance are connected to a first Y-axis 102 and a second Y-axis 103, which are parallel to each other and perpendicular to the X-axis 101, and the center point 125 of the first opening 121 is located at the first Y On the axis 102, the center point 126 of the second opening 122 is located on the second Y-axis 103 (as shown in FIG. 4). Preferably, the insulating layer 120 can include a base protective layer 123 and a thickened organic protective layer 124, and is a composite insulating layer, particularly up to 5 microns or more. The insulation and protection effect of the active surface 113 of the wafer 110 is improved and the stress buffering effect of the columnar bumps is generated. The material of the thickened organic protective layer 124 may be polyimide (PI) or polybenzoxazole (PBO), and the thickness thereof is much larger than the base protective layer 123.

The first stud bumps 130 are disposed on the first pad 111 , and the first stud bumps 130 include a first pillar portion 131 and a first solder layer 132 . The second stud bumps 140 are disposed on the second pad 112 . The second stud bumps 140 include a second pillar portion 141 and a second solder layer 142 . The material of the first column portion 131 and the second column portion 141 is a metal that cannot be reflowed and melted, such as copper (Cu). The shape of the first column portion 131 and the second column portion 141 on the active surface 113 is non-circular, for example, a narrow and thin rectangle. The first solder layer 132 and the second solder layer 142 may be lead-free solder, such as tin silver or tin silver copper. In addition, in a specific structure, a first barrier layer 135 may be formed between the first pillar portion 131 and the first solder layer 132, and the second pillar portion 141 and the second solder layer 142 may be formed. A second barrier layer 145 is formed between the first solder layer 132 and the second solder layer 142 to prevent solder components from being applied to the first pillar portion 131 and the second pillar portion 141. Metal diffusion. The material of the first barrier layer 135 and the second barrier layer 145 may be nickel.

The first column portion 131 has a plurality of first symmetric padding blocks 133 extending toward both sides of the first Y axis 102, and the second column portion 141 has a plurality of to the second A second symmetrical padding block 143 extending on both sides of the Y-axis 103 direction. The first symmetric padding block 133 and the second symmetric padding blocks 143 are overlaid on the insulating layer 120, that is, the symmetric padding block is disposed at a position beyond the corresponding first opening 121. And the second opening 122. In addition, the heights of the first symmetric padding block 133 and the second symmetric padding blocks 143 should be slightly larger than The height of the central body of the first column portion 131 and the second column portion 141 serves to support the micro-contact symmetrical support of flip chip/twist perforation bonding. Each of the first symmetrical padding block 133 and the second symmetrical padding block 143 may have a horizontal extension length of not less than 7 micrometers, for example, adjacent to the first opening 121 and the second opening 122, for example, 14.5 microns or 20 microns to expand the symmetrical support of the columnar bumps. Generally, the first symmetric padding block 133 and the second symmetric padding blocks 143 may have substantially the same shape and size to achieve complete symmetry of the columnar bumps on the insulating layer 120. extend. More specifically, the top surface of the first pillar portion 131 and the second pillar portion 141 may each have a central recess 134, 144 for respectively receiving a portion of the first solder layer 132 and the second portion Solder layer 142 to reduce the amount of solder spillage after bump bonding.

Moreover, the first pillar portion 131 and the second pillar portion 141 each have a plurality of bump widths shortened along the X axis 101, which may be about 85% of the opening width, for example, 36 micrometers, so that The first pillar portion 131 and the second pillar portion 141 have a second aspect ratio. The second aspect ratio is at least five times larger than a point of the first aspect ratio, thereby partially exposing the first pad 111 and the second pad 112, and causing the first pillar portion 131 along the first A center point 136 cut by a Y axis 102 is longitudinally aligned with a center point 125 of the first opening 121 (as shown in FIG. 3), and the center of the second cylinder portion 141 is cut along the second Y axis 103. The point 146 is also longitudinally aligned with the center point 126 of the second opening 122. When the first aspect ratio is one, the second aspect ratio is one or more five. In this embodiment, when the length of the first symmetric padding block 133 and the second symmetric padding block 143 on each side is about 7 micrometers, the first pillar portion 131 is added correspondingly to the first The length of the symmetric padding block 133 and the length of the second column portion 141 plus the corresponding second symmetric padding block 143 can each be 56 microns, divided by the 36 micron bump width, so the specific The second aspect ratio can be 1.55.

Preferably, the length of the first symmetric padding block 133 and the second symmetric padding block 143 on each side may be 10 micrometers or more, and the first symmetric padding block 133 is used. The second symmetrical padding block 143 is such that the length of the first column portion 131 and the second column portion 141 (specifically, 62 micrometers or more) is not less than the center point of the first opening 121 The distance from the center point 126 of the second opening 122 (specifically 60 micrometers), and the width of the bump may not be greater than the center point 125 from the first opening 121 to the second opening 122. Seventy-five percent of the distance from the center point 126, that is, the total length of each of the columnar bumps including the symmetric extension on the insulating layer 120 is not less than the distance between the columnar bumps, and each columnar convex The width of the block is not more than 75% of the distance between the columnar bumps, and becomes a fine pitch symmetrically extending narrow and thinned columnar bump structure. In this embodiment, the length of the first pillar portion 131 and the second pillar portion 141 is specifically 62 micrometers, so it is not less than the above-mentioned distance (specifically 60 micrometers) representing the interval of the bumps, the first pillar The width of the body portion 131 and the second column portion 141 is specifically 36 micrometers, so it is about 60% of the above-mentioned distance (specifically 60 micrometers) representing the interval of the bumps, that is, not more than 75%.

In addition, the micro-pitch array structure 100 may further include a first under bump metal layer 151 and a second under bump metal layer 152. The first under bump metal layer 151 is formed on the first pillar. The portion between the portion 131 and the first pad 111 does not cover the first exposed portion of the first pad 111. The second under bump metal layer 152 is formed on the second pillar portion 141 and the second pad. The partial exposed areas of the second pads 112 are not covered between the first pads 111 and the second exposed pads 112 to be recessed in the corresponding first opening 121 and the second opening. 122, to accommodate the solder that overflows the top surface of the stud bump. In addition, the first under bump metal layer 151 and the second under bump metal layer 152 may further extend to the first symmetric padding block 133 and the second symmetric padding blocks 143, respectively. Bottom, borrow In order to improve the bonding force and electroplating of the first symmetric padding block 133 and the second symmetric padding blocks 143.

Therefore, the micro-pitch arrangement structure of the columnar bumps on the wafer of the present invention prevents the solder bridging short circuit of the micro-pitch column bumps, and the columnar bumps having a sufficient soldering area can be arranged at a fine pitch and aligned The insulating layer of the pad is opened on the opening, and the bonding stress balance and release effect of the micro-pitch bumps are achieved. Moreover, the underfill filling gap between the fine pitch columnar bumps can be increased by about 5-6 microns to fill the underfill.

According to a specific embodiment of the present invention, the fine pitch arrangement structure of the other columnar bumps on the wafer is substantially the same as that of the foregoing embodiment, and the other modified features are illustrated in the cross-sectional view of FIG. The configuration of this modification which is substantially the same as the foregoing embodiment will not be described again. Basic Components As in the previous embodiment, the micro pitch array structure 200 includes a wafer 110, an insulating layer 120, a first stud bump 130, and a second stud bump 140. The first stud bumps 130 are disposed on the first pad 111 , and the first stud bumps 130 include a first pillar portion 131 and a first solder layer 132 . The second stud bumps 140 are disposed on the second pad 112 . The second stud bumps 140 include a second pillar portion 141 and a second solder layer 142 . The first column portion 131 has a plurality of first symmetric padding blocks 133 extending toward both sides of the first Y axis 102, and the second column portion 141 has a plurality of to the second a second symmetrical padding block 143 extending on both sides of the Y-axis 103 direction, and the first column portion 131 and the second column portion 141 each having a plurality of bump widths shortened along the X-axis 101 So that the first pillar portion 131 and the second pillar portion 141 have a second aspect ratio which is at least five times larger than a point of the first aspect ratio, thereby partially revealing the first solder The pad 111 and the second pad 112, and the center point 136 of the first column portion 131 along the first Y axis 102 is longitudinally aligned with the center point 125 of the first opening 121. The center point 146 of the second cylindrical portion 141 is longitudinally aligned with the center point 126 of the second opening 122.

In addition, the micro-pitch array structure 100 may further include a third stud bump 260 disposed on the insulating layer 120. The third stud bump 260 includes a third pillar portion 261 and a third solder layer 262, wherein the height of the third pillar portion 261 and the first symmetric padding block 133 are The heights of the second symmetrical padding blocks 143 may be approximately the same, and even if there is a slight difference, the height difference values are within 2 to 3 microns. A third barrier layer 263 may be formed between the third pillar portion 261 and the third solder layer 262. The third pillar portion 261 may form a third bump under the bottom of the insulating layer 120. Metal layer 253. The third stud bump 260 can be used as a pair of bit marks or a wafer leveling joint support point, so that the first stud bump 130 and the second stud bump 140 can be directly disposed and aligned with The first pad 111 and the second pad 112 are disposed without reconfiguration. Moreover, since the third stud bump 260 is completely disposed on the insulating layer 120, which is the height after the insulating layer 120 is raised, it is not necessary to have a symmetric padding block.

Therefore, the fine pitch arrangement structure of another kind of stud bumps on the wafer provided by the present invention can be used to improve the height inconsistency between the conventional wafer active surface pads and the columnar bumps having different functions on the composite insulating layer. The problem.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100‧‧‧Micro-pitch arrangement of columnar bumps on the wafer

101‧‧‧X axis

102‧‧‧First Y-axis

110‧‧‧ wafer

120‧‧‧Insulation

121‧‧‧First opening

122‧‧‧Second opening

123‧‧‧Basic protective layer

124‧‧‧ Thicken organic protective layer

130‧‧‧First cylindrical bump

131‧‧‧The first cylinder

132‧‧‧First solder layer

133‧‧‧First Symmetrical Height Block

134‧‧‧ central pocket

140‧‧‧Second columnar bump

141‧‧‧Second cylinder

142‧‧‧Second solder layer

143‧‧‧Second symmetrical padding block

144‧‧‧ central pocket

151‧‧‧First under bump metal layer

152‧‧‧second under bump metal layer

Claims (10)

A fine pitch arrangement structure of a columnar bump on a wafer comprises: a wafer having an active surface layer provided with a first bonding pad and a second bonding pad arranged on an X axis; an insulating layer Forming on the active surface of the wafer, and the insulating layer has a first opening and a second opening in a first aspect ratio, wherein the center point of the first opening One of the center points of the second opening is defined on the X axis and is not greater than 80 microns, and a first Y axis and a second Y axis are parallel to each other and perpendicular to the X axis, and the first opening a center point of the hole is located on the first Y axis, and a center point of the second opening is located on the second Y axis; a first columnar bump is disposed on the first pad, the first The columnar bump includes a first pillar portion and a first solder layer; and a second pillar bump is disposed on the second pad, the second pillar bump includes a second pillar a body and a second solder layer; wherein the first column portion has a plurality of extensions extending to the sides of the first Y axis a symmetrical padding block, the second column portion having a plurality of second symmetrical padding blocks extending to two sides of the second Y axis direction, the first symmetrical padding blocks and the The second symmetrical padding block covers the insulating layer, and the first column portion and the second column portion each have a bump width shortened along the X axis, so that the first The pillar portion and the second pillar portion have a second aspect ratio which is at least five times larger than a point of the first aspect ratio, thereby partially exposing the first pad and the second pad. And longitudinally aligning a center point of the first cylindrical portion along the first Y axis with a center point of the first opening, wherein a center point of the second cylindrical portion is longitudinally aligned with the second opening Center point. The micro-pitch arrangement of the columnar bumps on the wafer according to the first aspect of the patent application, wherein the first column portion and the top surface of the second column portion each have a central recess to respectively accommodate the portion The first solder layer and the second solder layer are separated. The fine pitch arrangement structure of the columnar bumps on the wafer according to the second aspect of the patent application scope further includes a first under bump metal layer and a second under bump metal layer, the first bump under metal layer Formed between the first pillar portion and the first pad without covering a local exposed area of the first pad, the second under bump metal layer is formed on the second pillar portion and the second The solder pads are not covered by the local exposed areas of the second pads. The fine pitch arrangement of the columnar bumps on the wafer according to the third aspect of the patent application, wherein the first under bump metal layer and the second under bump metal layer respectively extend to the first symmetrical The padding block and the second symmetrical padding block are below. The micro-pitch arrangement of the stud bumps on the wafer according to the first aspect of the patent application, wherein a first barrier layer is formed between the first pillar portion and the first solder layer, the second pillar A second barrier layer is formed between the portion and the second solder layer. The fine pitch arrangement of the columnar bumps on the wafer according to the first aspect of the patent application, wherein the insulating layer comprises a base protective layer and a thickened organic protective layer. The micro-pitch arrangement of the columnar bumps on the wafer according to the first aspect of the patent application, wherein each of the first symmetric padding blocks and the second symmetric padding blocks are adjacent to the first The horizontal extension length of the opening and the second opening is not less than 7 micrometers. The micro-pitch arrangement of the columnar bumps on the wafer according to the first aspect of the patent application, wherein the first symmetric padding block and the second symmetric padding blocks are used to make the first column Body and the second column The length of the body is not less than the distance from the center point of the first opening to the center point of the second opening, and the width of the protrusion is not greater than the center point of the first opening to the first Seventy-five percent of the distance between the center points of the two openings. The micro-pitch arrangement of the columnar bumps on the wafer according to the first aspect of the patent application, wherein the first symmetric padding blocks and the second symmetric padding blocks have substantially the same shape and size. The micro-pitch arrangement of the stud bumps on the wafer according to the first aspect of the patent application, further comprising a third stud bump disposed on the insulating layer, the third stud bump comprising a first The third pillar portion and a third solder layer, wherein the height of the third pillar portion is substantially the same as the height of the first symmetric padding blocks.