TWI497302B - Computer apparatus and operating method thereof - Google Patents

Description

Computer device and its operation method

The present invention relates to the field of computer related art, and in particular to a computer device and method of operating the same.

1 is a schematic diagram of a conventional computer device. Referring to FIG. 1 , the computer device 100 includes a central processing unit 110 , a chip set 120 , a serial peripheral interface (SPI) bus bar 130 , and a read-only memory 140 . The chipset 120 has a serial peripheral interface controller 122, and the serial peripheral interface controller 122 is electrically connected to the read-only memory 140 via the serial peripheral interface bus 130. The read-only memory 140 stores boot data of the computer device 100, for example, a code that stores a basic input/output system (BIOS). When the computer device 100 is powered on, the sequence peripheral interface controller 122 obtains the boot data request request from the read-only memory 140 as long as the serial peripheral interface controller 122 receives a boot data request from the central processing unit 110. The information to be obtained is transmitted to the central processing unit 110 so that the central processing unit 110 can normally execute the booting process of the computer device 100.

However, this method of operation will cause the computer device 100 to have a longer power-on self test time at boot time, as illustrated in FIG. 2 is a diagram for explaining self-detection of the computer device 100 at power-on. time. Referring to FIG. 2, it is assumed that the computer device 100 needs to execute three loops of a certain program to perform self-detection when the computer is turned on, and each loop includes three tasks, and the central processing unit 110 Each of the boot data request requirements is to obtain the code required to execute a loop. Then, according to the foregoing operation mode, when the central processing unit 110 proposes a boot request request, the computer device 100 first reads from the read only memory. The body 140 obtains the code required to execute the first loop, that is, obtains the code of the task 1-1~1-3, and then executes the code of the first loop, that is, performs the task 1 1~1-3 code. After executing the code of the first loop, when the central processing unit 110 requests a boot request request again, the computer device 100 will again obtain the program required to execute the second loop from the read-only memory 140. The code, that is, to obtain the code of the task 2-1~2-3, and then execute the code of the second loop, that is, execute the code of the task 2-1~2-3. In the same way, the code of the third loop is also performed in the same way.

Since the computer device 100 must first obtain the code required to execute the loop from the read-only memory 140 before executing the program code of the loop at the time of power-on, the data is transmitted from the read-only memory 140 to the center. The transmission speed of the processor 110 is again limited by the originally small bandwidth of the serial peripheral interface bus 130, making the computer device 100 too verbose at boot time.

The invention provides a computer device to shorten the time of booting.

The present invention further provides an operation method corresponding to the above computer device.

The invention provides a computer device comprising a central processing unit, a read-only memory, a flash memory, a first bus bar, a second bus bar and a chip set. The read-only memory system stores a boot data. The first busbar has a first bandwidth. And the second bus bar has a second bandwidth, and the second bandwidth is greater than the first bandwidth. As for the chip set, the method further includes a first bus controller, a second bus controller, a cache memory and an arbiter. The first busbar controller electrically connects the above-mentioned read-only memory through the first busbar. The second busbar controller electrically connects the flash memory to the second busbar through the second busbar. The cache memory system is electrically connected to the second busbar controller described above. The arbitrator is electrically connected to the first bus controller, the second bus controller, the cache, and the central processor. When the arbiter receives a boot request request from a central processing unit, the arbiter determines whether the boot data in the read-only memory has been completely backed up to the flash memory to generate the first determination. As a result, based on the first determination result, it is determined whether to further determine whether the information requested by the boot data request request has been stored in the cache memory to further generate the second judgment result. When the second determination result is obtained, the arbitrator decides whether to perform the first operation or the second operation according to the second determination result, wherein the first operation is to obtain the above-mentioned startup data request request from the cache memory. Acquiring the information and transmitting the information obtained to the central processing unit; and the second operation is to obtain the information requested by the above-mentioned boot data request request from the read-only memory to transmit the obtained data to the central processing unit. And the flash memory corresponding to the above-mentioned boot data request requirements The data block of the material is backed up to the cache memory.

The invention further provides a method of operating a computer device. The computer device includes a central processing unit, a read-only memory, a flash memory, a first bus, a second bus, and a chip set. The read-only memory stores a boot data. The first busbar has a first bandwidth. The second bus bar has a second bandwidth, and the second bandwidth is greater than the first bandwidth. The chip set further includes a first bus bar controller, a second bus bar controller, a cache memory and an arbiter. The first busbar controller electrically connects the above-mentioned read-only memory through the first busbar. The second busbar controller electrically connects the flash memory to the second busbar through the second busbar. The cache memory system is electrically connected to the second busbar controller. The arbitrator is electrically connected to the first busbar controller, the second busbar controller, the cache memory and the central processor. The operating method includes the following steps: when the arbiter receives a boot request request from a central processing unit, causing the arbiter to determine whether the boot data in the read-only memory has been completely backed up to the flash memory. In order to generate a first determination result; the arbitrator determines, according to the first determination result, whether to further determine whether the information requested by the startup data request request has been stored in the cache memory to further generate the second determination result; When the arbitrator obtains the second determination result, the arbitrator determines whether to perform the first operation or the second operation according to the second determination result, wherein the first operation is to obtain the boot data request request from the cache memory. The requested information is transmitted to the central processing unit, and the second operation is to obtain the information requested by the boot data request from the read-only memory to obtain the obtained information. The data is transmitted to the central processing unit, and the data block in the flash memory corresponding to the data requested by the booting data requesting request is backed up to the cache memory.

The method for solving the foregoing problem is to add a second bus bar and a flash memory in the computer device, wherein the bandwidth of the second bus bar is greater than the bandwidth of the first bus bar. In addition, a cache memory is added to the chipset, a busbar controller for controlling the second busbar, and an arbiter. In the present invention, when the arbiter receives a boot request request from a central processing unit, the arbiter determines whether the boot data in the read-only memory has been completely backed up to the flash memory. The first judgment result is generated. Next, the arbitrator determines whether to further determine whether the data requested by the boot request request is stored in the cache memory according to the first judgment result, so as to further generate the second judgment result. Once the arbiter obtains the second determination result, the arbiter determines whether to perform the first operation or the second operation described above according to the second determination result.

In other words, when the arbiter receives a boot request request from one of the central processing units, the arbiter determines whether to retrieve the memory from the cache based on the data storage status in the flash memory and the cache memory. Get the required information from the readable memory. As long as the boot data in the read-only memory has been completely backed up to the flash memory, and the data requested by the boot data request request has been stored in the cache memory, the arbiter will perform the above-mentioned An operation, that is, obtaining the information requested by the boot data request from the cache memory, and transmitting the obtained data to the central processing unit. As long as the boot data in the read-only memory is completely backed up to In the flash memory, the information requested by the boot data request is not stored in the cache memory, then the arbiter performs the second operation described above, that is, the boot data is obtained from the read-only memory. Request the requested information to transfer the obtained data to the central processing unit, and back up the data block in the flash memory corresponding to the information requested by the boot data request to the cache memory. In this way, the number of times the computer device obtains the boot data from the read-only memory can be reduced, and the data transfer speed can be prevented from being limited by the bandwidth of the corresponding bus of the read-only memory, thereby enabling the computer device of the present invention to The self-test time at boot is shorter.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

3 is a schematic diagram of a computer device in accordance with a preferred embodiment of the present invention. Referring to FIG. 3, the computer device 300 includes a central processing unit 310, a chipset 320, a bus bar 330, a read-only memory 340, a bus bar 350, and a flash memory 360. The read-only memory 340 stores boot data of the computer device 300, such as a code that stores a basic input/output system. In addition, the bus bar 330 has a first bandwidth, and the bus bar 350 has a second bandwidth, and the second bandwidth is greater than the first bandwidth.

As for the chip set 320, it further includes a cache memory 322, an arbitrator (Arbiter) 324, a bus bar controller 326, and a bus bar controller 328. The bus bar controller 328 is electrically connected to the bus bar 330 for reading only. The memory 340, the bus controller 326 is electrically connected to the flash memory 360 through the bus bar 350, and the cache memory 322 is electrically connected to the bus controller 326. As for the arbiter 324, it is electrically connected to the cache memory 322, the central processing unit 310, the bus bar controller 326, and the bus bar controller 328. In this example, the bus bar 330 is implemented, for example, by a sequence of peripheral interface bus bars, and the bus bar 350 is implemented, for example, by a secure digital input/output (SDIO) interface bus bar, and the bus bar control is implemented. The 328 is implemented, for example, by a sequence of peripheral interface controllers, and the bus controller 326 is implemented, for example, by a secure digital input/output interface controller.

When the computer device 300 is turned on, the arbiter 324 simultaneously starts the program shown in FIG. 4 and the programs shown in FIGS. 5A to 5C. 4 is a first type of program executed by the arbiter 324 when the computer device 300 is turned on, and FIGS. 5A-5C are second programs executed by the arbiter 324 when the computer device 300 is turned on. Referring first to FIG. 3 and FIG. 4, when the computer device 300 is powered on, the arbiter 324 determines whether the bus bar 330 is in an idle state. When the arbiter 324 determines that the bus bar 330 is in an idle state, the first program is started (as shown in step S410). In this procedure, the arbiter 324 first determines whether the boot material in the read-only memory 340 has been completely backed up into the flash memory 360 (as shown in step S412). When the determination is no, the arbiter 324 starts backing up the boot data in the read-only memory 340 to the flash memory 360 (as shown in step S416); and when the determination is yes, the arbiter 324 does not execute. The operation of backing up the boot data to the flash memory 360 is performed, but the flow of the program is directly ended (as shown in step S414).

Since the flash memory 360 is a non-volatile memory, the stored data does not disappear due to the loss of power supply. Therefore, in the first program described above, only in the computer When the device 300 is powered on for the first time since self-assembly, the arbiter 324 determines that the boot data in the read-only memory 340 has not been completely backed up to the flash memory 360, so the read-only memory must be started. The boot data in 340 is backed up to flash memory 360. However, starting from the second boot of the computer device 300, the arbiter 324 determines that the boot data in the read-only memory 340 has been completely backed up to the flash memory 360, thus directly ending the first program. The entire process.

Referring to FIG. 3 and FIG. 5A to FIG. 5C, when the computer device 300 is powered on, when the arbiter 324 receives a boot request request from the central processing unit 310, the second program is started (step S510). Show). In this procedure, the arbiter 324 first determines whether the boot material in the read-only memory 340 has been completely backed up into the flash memory 360 (as shown in step S512) to generate a first determination result. When the first determination result is YES, it indicates that the booting is not the first booting since the computer device 300 is self-assembled, so the booting data in the read-only memory 340 is completely backed up to the flash memory 360, then The arbiter 324 can further determine whether the data requested by the boot data request request has been stored in the cache memory 322 (as shown in step S520) to further generate a second determination result.

When the second determination result is YES, it indicates that the data stored in the cache memory 322 is the same as the data requested by the previous boot data request request, then the arbiter 324 performs the first operation (eg, Figure 5B Step S526), the first operation is to directly obtain the data requested by the boot data request request from the cache memory 322, and transmit the obtained data to the central processing unit 310. On the other hand, when the second determination result is no, it indicates that the data stored in the cache memory 322 is different from the data requested by the previous boot data request request, then the arbiter 324 performs the second operation. (as shown in step S524 of FIG. 5B), the second operation is to obtain the information requested by the boot data request request directly from the read-only memory 340, so as to transmit the obtained data to the central processing unit 310, and At the same time, the data block in the flash memory 360 corresponding to the above-mentioned boot data request request is backed up to the cache memory 322. In this way, when the arbiter 324 receives the next boot request request, if the data requested by the next boot request request is stored in the cache 322, the arbiter 324 can The required data is directly obtained in the cache memory 322. In other words, if the information requested by the next startup data request request is the same as the information to be requested at this time, the arbiter 324 can directly obtain the required data from the cache memory 322. After the step S526 or S524 is executed, the arbiter 324 directly ends the entire flow of the second program (as shown in step S518).

Please return to step S512 of FIG. 5A. When the first determination result is no, that is, the boot data in the read-only memory 340 has not been completely backed up to the flash memory 360, it indicates that the booting is the first booting of the computer device 300 since self-assembly. Therefore, the arbiter 324 further determines whether the flash memory 360 has stored the data block corresponding to the data requested by the boot data request request to generate a third determination result (as shown in FIG. 5C). Step S514). When the third determination result is YES, it indicates that the boot data in the read-only memory 340 has not been completely backed up to the flash memory 360, but the flash memory 360 has been stored in response to the above-mentioned boot data request request. The data block of the data is requested, so the requested data requested by the above-mentioned boot data request may have been backed up from the flash memory 360 to the cache memory 322. Therefore, when the third determination result is YES, the arbiter 324 can further determine whether the data requested by the boot data request request has been stored in the cache memory 322 (as shown in step S520).

On the other hand, when the third determination result is no, it indicates that the boot data in the read-only memory 340 has not been completely backed up to the flash memory 360, and the flash memory 360 is not stored corresponding to the above-mentioned boot data request request. The data block for which the data is to be requested, therefore, the above-mentioned boot data request request cannot be backed up from the flash memory 360 to the cache memory 322. Therefore, when the third determination result is no, the arbiter 324 directly obtains the information requested by the boot data request request from the read-only memory 340, and transmits the obtained data to the central processing unit 310 ( As shown in step S516). It is worth mentioning that, although the third judgment result is no, the information requested by the above-mentioned boot data request request is directly provided by the read-only memory 340, but has not been completely backed up to the boot in the flash memory 360. The data will continue to be transferred to the flash memory 360 until the boot data is completely copied to the flash memory 360. After the step S516 is executed, the arbiter 324 directly ends the entire flow of the second program (as shown in step S518).

It is worth mentioning that in the actual design manner, the flash memory 360 may be provided with a first flag and a plurality of second flags, and the foregoing The arbitrator 324 can determine whether the boot data in the read-only memory 340 has been completely backed up to the flash memory 360 according to the state of the first flag, and can determine the flash according to the state of each second flag. Whether the memory 360 has stored a corresponding data block.

As can be seen from the above teachings, when the arbiter 324 receives a boot request request from the central processing unit 310, the arbiter 324 determines based on the data storage status in the flash memory 360 and the cache memory 322. The required data is to be obtained from the cache memory 322 or from the read-only memory 340. As long as the boot data in the read-only memory 340 has been completely backed up to the flash memory 360, and the data requested by the boot data request request has been stored in the cache memory 322, the arbiter 324 will go. The first operation described above is performed, that is, the information requested by the boot data request request is obtained from the cache memory 322, and the obtained data is transmitted to the central processing unit 310. As long as the boot data in the read-only memory 340 has been completely backed up to the flash memory 360, but the data requested by the boot data request request is not stored in the cache memory 322, the arbiter 324 will To perform the second operation described above, that is, to obtain the information requested by the boot data request request from the read-only memory 340, to transfer the obtained data to the central processing unit 310, and simultaneously to flash the memory 360. The data block corresponding to the information requested by the boot data request is backed up to the cache memory 322. In this way, the number of times the computer device obtains the boot data from the read-only memory 340 can be reduced, and the data transfer speed can be prevented from being limited by the bandwidth of the corresponding bus bar 330 of the read-only memory 340, thereby making the present invention The self-detection time of the computer device 300 at the time of power-on is short.

FIG. 6 is a diagram for explaining the self-detection time of the computer device 300 at the time of power-on. Referring to FIG. 6, it is assumed that the computer device 300 needs to execute three loops of a certain program for self-detection when the computer device is turned on, and each loop includes three tasks, and each booting data of the central processing unit 310 is requested. The request is to obtain the code required to execute a loop. Then, according to the foregoing operation mode, when the central processing unit 310 requests a boot request request, the computer device 300 determines the boot data in the read-only memory 340. It has been completely backed up to the flash memory 360, but the data requested by the boot request request (for example, the code required to execute the first loop) has not been stored in the cache memory 322. Then, the computer device 300 first obtains the code required to execute the first loop from the read-only memory 340, that is, obtains the code of the tasks 1-1~1-3. At the same time, the computer device 300 also backs up the data block in the flash memory 360 corresponding to the current boot data request request to the cache memory 322. Assuming that the data block contains the code required to execute the first loop, the code required to execute the second loop, and the code required to execute the third loop, the cache memory 322 will The code of tasks 1-1~1-3, the code of tasks 2-1~2-3, and the code of tasks 3-1~3-3 will be stored. In other words, when the computer device 300 obtains the code of the tasks 1-1~1-3 required for executing the first loop from the read-only memory 340, the code of the tasks 1-1~1-3, The code of tasks 2-1~2-3 and the code of tasks 3-1~3-3 are simultaneously backed up by the flash memory 360 to the cache memory 322.

After obtaining the code of the first loop, the computer device 300 will execute the code of the first loop, that is, the code of the tasks 1-1~1-3. After executing the code of the first loop, when the central processing unit 310 again proposes a boot request request, and the data requested by the boot request request is the code required to execute the second loop. Then, the computer device 300 will change the code required to execute the second loop from the cache memory 322, that is, obtain the code of the task 2-1~2-3, and then execute the second time. The code of the circle, that is, the code of the task 2-1~2-3. Similarly, when the central processing unit 310 again proposes a boot data request request, and the boot data request requesting the requested data is the code required to execute the third loop, then the third loop code It is also performed in the same way as the code of the second loop. Since the speed of obtaining the code from the cache memory 322 is greater than the code obtained from the read-only memory 340 (eg, through the peripheral interface bus of the sequence), by comparing FIG. 6 with FIG. 2, the map can be found. The self-test time at boot time shown in Figure 6 is shorter than the self-test time at boot time shown in Figure 2.

With the teachings of the above embodiments, those skilled in the art can summarize some basic operational steps of the computer device of the present invention, as shown in FIG. FIG. 7 is a flow chart showing a method of operating a computer device in accordance with a preferred embodiment of the present invention. The computer device includes a central processing unit, a read-only memory, a flash memory, a first bus, a second bus, and a chip set. The read-only memory stores a boot data. The first busbar has a first bandwidth. The second bus bar has a second bandwidth, and the second bandwidth is greater than the first bandwidth. The chip set further includes a first bus bar controller, a second bus bar controller, a cache memory and an arbiter. The first busbar controller electrically connects the above-mentioned read-only memory through the first busbar. Place The second bus controller is electrically connected to the flash memory through the second bus. The cache memory system is electrically connected to the second busbar controller. The arbitrator is electrically connected to the first busbar controller, the second busbar controller, the cache memory and the central processor. Referring to FIG. 7, the operation method includes the following steps: when the arbitrator receives a boot request request from a central processing unit, the arbitrator determines whether the boot data in the read-only memory is completely backed up. Up to the flash memory to generate a first determination result (as shown in step S702); causing the arbiter to determine, based on the first determination result, whether to further determine whether the information requested by the boot data request request has been stored in the cache memory. In the body, to further generate a second determination result (as shown in step S704); and when the arbiter obtains the second determination result, causing the arbiter to decide whether to perform the first operation or the second operation according to the second determination result. The first operation is to obtain the information requested by the boot data request from the cache memory, and transmit the obtained data to the central processing unit, and the second operation system obtains the boot data from the read-only memory. Request the information requested to transmit the obtained data to the central processing unit, and at the same time request the corresponding flash memory in the flash memory The data block for which the desired data is requested is backed up to the cache memory (as shown in step S706).

In summary, the method for solving the foregoing problem is to add a second bus bar and a flash memory to the computer device, wherein the bandwidth of the second bus bar is greater than the bandwidth of the first bus bar. In addition, a cache memory is added to the chipset, a busbar controller for controlling the second busbar, and an arbiter. In the present invention, when the arbiter receives the When one of the central processing units requests the boot request, the arbiter determines whether the boot data in the read-only memory has been completely backed up to the flash memory to generate the first judgment result. Next, the arbitrator determines whether to further determine whether the data requested by the boot request request is stored in the cache memory according to the first judgment result, so as to further generate the second judgment result. Once the arbiter obtains the second determination result, the arbiter determines whether to perform the first operation or the second operation described above according to the second determination result.

In other words, when the arbiter receives a boot request request from one of the central processing units, the arbiter determines whether to retrieve the memory from the cache based on the data storage status in the flash memory and the cache memory. Get the required information from the readable memory. As long as the boot data in the read-only memory has been completely backed up to the flash memory, and the data requested by the boot data request request has been stored in the cache memory, the arbiter will perform the above-mentioned An operation, that is, obtaining the information requested by the boot data request from the cache memory, and transmitting the obtained data to the central processing unit. As long as the boot data in the read-only memory has been completely backed up to the flash memory, but the data requested by the boot data request is not stored in the cache memory, the arbitrator will perform the above. The second operation, that is, obtaining the information requested by the boot data request request from the read-only memory, is to transmit the obtained data to the central processing unit, and simultaneously request the corresponding information in the flash memory corresponding to the boot data. The data block of the requested data is backed up to the cache memory. In this way, the number of times the computer device obtains the boot data from the read-only memory can be reduced, and the data transfer speed can be prevented from being limited by the bandwidth of the corresponding bus of the read-only memory. Further, the self-detection time of the computer device of the present invention at the time of power-on is short.

While the present invention has been described above in terms of the preferred embodiments, it is not intended to limit the invention, and those of ordinary skill in the art can make a few changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 300‧‧‧ computer equipment

110, 310‧‧‧ central processor

120, 320‧‧‧ chipsets

122‧‧‧Sequence Peripheral Interface Controller

130‧‧‧Sequence peripheral interface bus

140, 340‧‧‧ read-only memory

322‧‧‧Cache memory

324‧‧‧ Arbitrator

326, 328‧‧ ‧ bus controller

330, 350‧‧ ‧ busbar

360‧‧‧flash memory

1-1~1-3, 2-1~2-3, 3-1~3-3‧‧‧ tasks

S410~S416, S510~S526‧‧‧ steps

1 is a schematic diagram of a conventional computer device.

Figure 2 is a diagram for explaining the self-detection time of a conventional computer device at the time of power-on.

3 is a schematic diagram of a computer device in accordance with a preferred embodiment of the present invention.

Figure 4 shows the first program executed by the arbiter when the computer device is turned on.

5A to 5C are second programs executed by the arbiter when the computer device is turned on.

Figure 6 is a diagram for explaining the self-detection time of the computer device of the present invention when it is turned on.

FIG. 7 is a flow chart showing a method of operating a computer device in accordance with a preferred embodiment of the present invention.

300‧‧‧ computer equipment

310‧‧‧Central Processing Unit

320‧‧‧ Chipset

322‧‧‧Cache memory

324‧‧‧ Arbitrator

326, 328‧‧ ‧ bus controller

330, 350‧‧ ‧ busbar

340‧‧‧Read-only memory

360‧‧‧flash memory

Claims (14)

A computer device comprising: a central processing unit; a read-only memory storing a boot data; a flash memory; a first bus having a first bandwidth; and a second bus having a second bus a second bandwidth, and the second bandwidth is greater than the first bandwidth; and a chip set, comprising: a first busbar controller electrically connected to the read-only memory through the first busbar; a second busbar controller electrically connected to the flash memory through the second busbar; a cache memory electrically connected to the second busbar controller; and an arbiter electrically connected to the a first bus controller, the second bus controller, the cache memory, and the central processor, when the arbiter receives a boot request request from the central processor, the arbiter Determining whether the boot data in the read-only memory has been completely backed up to the flash memory to generate a first determination result, and determining whether to further determine the boot request request according to the first determination result Wanted Whether the data is stored in the cache memory to further generate a second determination result, and when the second determination result is obtained, the arbiter determines, according to the second determination result, that a first operation is to be performed. Or performing a second operation, the first operation is to obtain the information requested by the boot data request request from the cache memory, and transmit the obtained data to the central processing unit, the second operation system is The reading only Retrieving the information requested by the boot data requesting request to transmit the obtained data to the central processing unit, and the information in the flash memory corresponding to the information requested by the booting data requesting request The block is backed up to the cache memory. The computer device of claim 1, wherein the arbiter performs the first operation when the second determination result is YES, and the arbitrator performs the first operation when the second determination result is negative Second operation. The computer device of claim 2, wherein when the first determination result is YES, the arbitrator further determines whether the information requested by the startup data request request is stored in the cache memory. And when the first determination result is no, the arbiter further determines whether the flash memory has stored the data block corresponding to the information requested by the boot data request request to generate a third determination result. And determining, according to the third judgment result, whether to further determine whether the information requested by the boot data request request has been stored in the cache memory, or whether the boot data request request is obtained from the read-only memory The information requested and the information obtained is transmitted to the central processor. The computer device of claim 3, wherein when the third determination result is YES, the arbitrator further determines whether the information requested by the startup data request request is stored in the cache memory. And when the third determination result is no, the arbiter obtains the information requested by the boot data request request from the read-only memory, and transmits the obtained data to the central processing unit. The computer device of claim 1, wherein the arbiter determines whether the boot data in the read-only memory has been completely backed up to the flash when the first bus is in an idle state. Memory And when the determination is no, the arbiter starts backing up the boot data in the read-only memory to the flash memory, and when the determination is yes, the arbiter does not perform the booting The data is backed up to the backup operation of the flash memory. The computer device of claim 1, wherein the flash memory is provided with a first flag and a plurality of second flags, and the arbiter determines the read only according to the state of the first flag. Whether the booting data in the memory has been completely backed up into the flash memory, and determining whether the flash memory has stored a corresponding data block according to the state of each second flag. The computer device of claim 1, wherein the first bus bar comprises a sequence of peripheral interface bus bars, and the second bus bar comprises a secure digital input/output interface bus bar, the first bus bar The controller includes a sequence of peripheral interface controllers, and the second bus controller includes a secure digital input/output interface controller. A computer device includes a central processing unit, a read-only memory, a flash memory, a first bus, a second bus, and a chip set. The read-only memory is stored. Having a booting data, the first bus bar has a first bandwidth, the second bus bar has a second bandwidth, and the second bandwidth is greater than the first bandwidth, and the chip set further includes a first confluence a row controller, a second bus controller, a cache memory and an arbitrator, the first bus controller electrically connecting the read-only memory through the first bus, the second bus The controller is electrically connected to the flash memory through the second bus bar, the cache memory system is electrically connected to the second bus bar controller, and the arbiter is electrically connected to the first bus bar controller, The second bus controller, the cache memory And the central processing unit, the operating method includes: when the arbitrator receives a boot request request from the central processor, causing the arbitrator to determine whether the boot data in the read-only memory is completely Backing up to the flash memory to generate a first determination result; causing the arbiter to determine, according to the first determination result, whether to further determine whether the information requested by the boot data request request has been stored in the cache In the memory, to further generate a second determination result; and when the arbitrator obtains the second determination result, causing the arbiter to decide whether to perform a first operation or a second according to the second determination result The operation, wherein the first operation obtains the information requested by the boot data request request from the cache memory, and transmits the obtained data to the central processing unit, and the second operation system reads from the read only Obtaining the information requested by the boot request request in the memory to transmit the obtained data to the central processing unit and corresponding to the flash memory The boot block desired information requests received requests for information to back up the cache memory. The operation method of claim 8, wherein when the second determination result is YES, the arbiter is caused to perform the first operation, and when the second determination result is negative, the arbiter is caused to perform This second operation. The method of claim 9, wherein when the first determination result is YES, the arbitrator further determines whether the information requested by the startup data request request is stored in the cache memory. And when the first determination result is no, the arbitrator further determines whether the flash memory has stored the data block corresponding to the information requested by the boot data request request to generate a third judgment. Result and The arbitrator determines, according to the third determination result, whether it is further determined whether the information requested by the boot data request request has been stored in the cache memory, or whether the boot data is obtained from the read-only memory. Request the information requested and transmit the information obtained to the central processor. The method of claim 10, wherein when the third determination result is YES, the arbitrator further determines whether the information requested by the startup data request request is stored in the cache memory. And when the third determination result is no, the arbitrator obtains the information requested by the boot request request from the read-only memory, and transmits the obtained data to the central processing unit. The operation method of claim 8, wherein when the first bus is in an idle state, the arbitrator determines whether the boot data in the read-only memory has been completely backed up to the flash. In the memory, and when the determination is no, the arbiter starts backing up the boot data in the read-only memory to the flash memory, and when the determination is yes, the arbiter is not executed. The boot data is backed up to the backup operation of the flash memory. The operating method of claim 8, wherein the flash memory further comprises a first flag and a plurality of second flags, and the operating method further comprises: causing the arbiter to be based on the first flag Determining whether the boot data in the read-only memory has been completely backed up into the flash memory, and causing the arbiter to determine whether the flash memory has been stored according to the status of each second flag A good corresponding data block. The operating method of claim 8, wherein the first bus bar comprises a sequence of peripheral interface bus bars, the second bus bar The method includes a secure digital input/output interface bus, the first bus controller includes a sequence of peripheral interface controllers, and the second bus controller includes a secure digital input/output interface controller.