JP2008299632A - Semiconductor integrated circuit, image processor with semiconductor integrated circuit, and communication control method of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, capable of performing another processing without stall of a function module having a master function even in the event of a communication error between function modules within the semiconductor integrated circuit. <P>SOLUTION: The ASIC (semiconductor integrated circuit) 100 including a plurality of function modules for transmitting and receiving predetermined data comprises a master module 101 having the master function of requesting data and a slave module 109 having the slave function of transmitting data in response to the request. The master module 101 has the function of monitoring the response to the request for a fixed time to thereby avoid occurrence of stall. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including a plurality of functional modules that transmit and receive predetermined data, an image processing apparatus including the semiconductor integrated circuit, and a communication control method between the functional modules in the semiconductor integrated circuit.

  As this type of technology, for example, the invention described in Patent Document 1 or 2 is known. Among them, Patent Document 1 is a method for communicating data between functional blocks in a communication device for the purpose of providing a communication device and method for providing flexible communication capability between electronic subsystems. Set at least one thread identifier, each thread identifier associating a data transfer with a transaction stream that is part of the data transfer between the initiator functional block and the target functional block, if the target functional block is the initiator If the data transfer from the functional block cannot be received, the target functional block sends a busy signal identified by the thread identifier, and the initiator functional block refrains from transferring the data associated with the thread identifier in response to the busy signal, Identified by the transmitted busy signal The thread identifier is a data transfer unrelated be sent, discloses the invention to methods and features, including the.

  Further, Patent Document 2 aims to reduce a decrease in the usage rate of a common bus in a system that performs communication using a common bus among a plurality of modules connected to the common bus. The invention is characterized in that each module is provided with a bus control means, and when communication is performed between modules, the bus control means of the module controls access to the common bus.

That is, in Patent Document 1, a plurality of functional blocks are connected by an external bus, and a communication control method between the functional blocks is proposed. In Patent Document 2, a plurality of LSIs (CPU, memory, etc.) are provided on a common external bus. Have been proposed, and a control method for efficiently using a common bus has been proposed.
JP-T-2004-530197 Japanese Patent Laid-Open No. 03-188549

  In the inventions described in Patent Documents 1 and 2, a communication control method between a plurality of blocks has been proposed, but nothing is said about the error control method. Accordingly, as in the inventions described in Patent Documents 1 and 2, when a communication error occurs between a plurality of functional blocks or a plurality of functional modules, it cannot be appropriately dealt with. For example, when an access request is made from the master module to the slave module, if there is no access response from the slave module for some reason (such as a circuit failure), the master module will wait indefinitely for an access response and stall. There was no way to deal with this situation.

  Therefore, the problem to be solved by the present invention is that even if a communication error occurs between functional modules in a semiconductor integrated circuit, it is possible to perform another processing without stalling the functional module having the master function. Is to make it.

  In order to solve the above-described problem, a first means includes a functional module having a master function for requesting data in a semiconductor integrated circuit including a plurality of functional modules for transmitting and receiving predetermined data, and data in response to the request. And a function module having a slave function of transmitting, wherein the function module having the master function has a function of monitoring the response to the request for a certain period of time.

  The second means generates an interrupt for notifying the host side when the functional module having the master function detects no response from the functional module having the slave function for a predetermined time in the first means. It has the function to perform.

  According to a third means, in the second means, the functional module having the master function has a function of arbitrarily setting a response time from the functional module having the slave function.

  The fourth means is characterized in that, in the third means, the function module having the master function has a function of enabling or disabling the function of monitoring the response time.

  A fifth means is characterized in that, in the fourth means, the functional module having the master function has a function of holding the last address requested to be accessed.

  A sixth means is characterized in that, in the fifth means, the functional module having the master function has a function of holding last write data requested for write access or last read data of a read access response. .

  The seventh means includes a semiconductor integrated circuit according to any one of the first to sixth means, and the semiconductor integrated circuit performs a predetermined process on the image data input or read from the storage means. An image processing apparatus including

  According to an eighth means, in a communication control method between the functional modules in a semiconductor integrated circuit including a plurality of functional modules that transmit and receive predetermined data, a functional module having a master function that requests data, and in response to the request A functional module having a slave function for transmitting data, wherein the functional module having the master function monitors the response to the request for a certain period of time.

  A ninth means generates an interrupt for notifying the host side when the functional module having the master function detects no response from the functional module having the slave function for a predetermined time in the eighth means. It is characterized by doing.

  A tenth means is the ninth means, wherein the functional module having the master function arbitrarily sets a response time from the functional module having the slave function.

  The eleventh means is characterized in that, in the tenth means, the functional module having the master function enables or disables the monitoring of the response time.

  A twelfth means is characterized in that, in the eleventh means, the functional module having the master function holds the last address requested to be accessed.

  A thirteenth means is characterized in that, in the twelfth means, the functional module having the master function holds the last write data requested for write access or the last read data of the read access response.

  In the embodiments described later, the semiconductor integrated circuit has a function for performing predetermined processing on image data in the ASIC 100, the functional module having a master function in the master module 101, and the functional module having a slave function in the slave module 109. The modules correspond to the image rotation unit 170 and the compression / decompression unit 180, and the host corresponds to the CPU 210.

  According to the present invention, since the functional module having the master function monitors the response to the request for a certain time, even if a communication error occurs between the functional modules in the semiconductor integrated circuit, the functional module having the master function Another process can be performed without stalling.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an example of a system configuration using an ASIC to which the present invention is applied. In the figure, an ASIC 100 is printed with an interface 110 with a CPU 210 that controls system control, a memory interface 120 such as a DRAM 220 that stores image data and programs, a scanner interface 130 that controls input of an image read by a scanner 230, and a plotter 240. A plotter interface 140 for controlling output of the image to be transmitted, a network interface 150 for controlling input of image data transmitted from the network 250, and an HDD interface 160 for storing image data in the HDD 260. Further, an image rotation unit 170 for rotating the image and a compression / decompression unit 180 for compressing and expanding the image are provided. Reference numeral 211 denotes a ROM connected to the CPU 210.

  The arbiter 105 is connected to a scanner DMAC 131, a plotter DMAC 141, a network DMAC 151, an HDD DMAC 161, a rotating DMAC read 171, a rotating DMAC write 172, an image DMAC 181, and a code DMAC 182, and arbitrates data transfer between each DMAC and the memory unit 120. ing. Each DMAC or unit includes a register for determining an operation, and the register setting is performed by the CPU 210.

  The inter-module interface in the present embodiment is, for example, between each DMAC and unit (for example, between the rotating DMAC lead 171 and the image rotating unit 170 or between the HDD DMAC 161 and the HDD unit 160) in the ASIC 100 in FIG. It is between the DMAC / unit register interface. The master module is a module that actively requests to read or write data (functional module having a master function). The slave module passively receives write data or requests from the master module. In response to this, the module transmits the read data to the master module (functional module having a slave function).

  For example, when rotating image data, the rotating DMAC lead 171 serves as a master module for the image read from the DRAM 220 and transfers the image data to the image rotating unit 170 which is a slave module. When the CPU 210 sets a register in the scanner DMAC 131, the CPU interface 110 becomes a master module and transfers register data to the scanner DMAC 131 that is a slave module.

  In this embodiment, for example, when the clock supply to the slave module is stopped, when the data transfer from the master module stops the response from the slave module, or there is a problem with the slave module. Suppose that the response from the slave module is lost when data is transferred from the master module under certain conditions.

  Hereinafter, each example in the present embodiment will be described in detail.

  FIG. 2 is a block diagram illustrating the configuration of the ASIC according to the first embodiment. In this embodiment, a semiconductor integrated circuit having a plurality of functional modules for transmitting and receiving predetermined data, that is, an ASIC, a functional module having a master function for requesting data, here a master module, and data in response to the request. A function module having a slave function of transmitting, here a slave module, having a function of monitoring the response to the request for a certain time by the master module.

  That is, in FIG. 2, the ASIC 100 is provided with a master module 101 and a slave module 109, an access request is output to the master module 101, and an access response corresponding to the request is sent from the slave module 109 to the master module 101. Is called. A response monitoring circuit 102 is further provided in the master module 101. Further, a down counter having a fixed initial value is provided in the monitoring circuit 102.

  FIG. 3 is a flowchart showing a control procedure of the ASIC 100 of FIG. After issuing an access request from the master module 101 (step S101), the monitoring circuit 102 monitors an access response from the slave module 109 at regular time intervals (for example, every operation clock). When there is no access response from the slave module 109 (step S102-No), the fixed initial value is decremented by 1 (step S103), and whether or not the value is equal to “0” is compared (step S104). If it is equal to “0” (step S104—Yes), the response timeout flag is set to “1” (step S106). If the response counter is not “0”, the process returns to step S102 to monitor the access response again. If there is an access response from the slave module 109, the down counter is reset to a fixed initial value (step S105).

  When configured and processed in this way, the master module 101 can detect that there is no access response from the slave module 109 within a certain time, so that another process can be performed without the master module 101 stalling.

  FIG. 4 is a block diagram illustrating the configuration of the ASIC according to the second embodiment. In this embodiment, an interrupt generation circuit 103 is added to the master module 101 of the ASIC 100 in the first embodiment, and a function for monitoring an access response for a predetermined time is provided in the master module. It is configured equally. The interrupt generation circuit 103 generates an interrupt based on the output from the response monitoring circuit 102 and outputs it to the interrupt control circuit 104.

  FIG. 5 is a flowchart showing the control procedure of the ASIC in the second embodiment. Also in the present embodiment, as in the first embodiment, the response monitoring circuit 102 monitors the access response from the slave module 109 (steps S101 and S102), and there is no access response and the response counter becomes “0” ( In step S103, S104), a response timeout interrupt signal is asserted (step S107). This signal is processed by the interrupt control circuit 104 in the ASIC 100 to cause the CPU 210 to generate an interrupt. In the flowchart of the second embodiment illustrated in FIG. 5, the description of the flowchart of the first embodiment illustrated in FIG. 3 is omitted because step S <b> 106 in FIG. 3 is replaced with step S <b> 107.

  When configured and processed in this way, when a stall occurs between the master module 101 and the slave module 109, the CPU 210 can be notified by an interrupt, so it is determined that the CPU 210 is stalled between modules. Thus, it is possible to perform appropriate processing according to the determination result.

  FIG. 6 is a block diagram illustrating the configuration of the ASIC according to the third embodiment. In this embodiment, a response count register 102a writable by the CPU 210 is added to the response monitoring circuit 102 of the master module 101 of the ASIC 100 in the second embodiment, and the response time from the slave module 109 can be arbitrarily set in the master module 101. A function is added. Other parts are configured in the same manner as in the second embodiment.

  FIG. 7 is a flowchart illustrating an ASIC control procedure according to the third embodiment. The flowchart of FIG. 7 is obtained by providing the procedure of step S201 before the step S101 of the flowchart of FIG. That is, before starting data transfer between the master module 101 and the slave module 109 in the ASIC 100, a desired value is set in the response count register 102a from the CPU 210 in advance. Then, after starting the data transfer from the CPU 210, the value set in the response count register 102a is loaded into the down counter (step S201). Next, the procedure after step S101 is executed in the same manner as in the second embodiment. That is, the response monitoring circuit 102 in the master module 101 monitors the access response from the slave module 109 (101, S102). If there is an access response (step S102-Yes), the down counter is reset. At this time, it is reset with the value set in the response count register 102a.

  When configured and processed in this manner, the access response time from the slave module 109 can be arbitrarily set, so that an interrupt is generated to the CPU 210 only when there is no access response after waiting for the intended maximum time. can do.

  FIG. 8 is a block diagram illustrating the configuration of the ASIC according to the fourth embodiment. In this embodiment, an access response control register 102b writable by the CPU 210 is added to the response monitoring circuit 102 of the master module 101 in the third embodiment. In this register 102b, a bit for controlling whether or not to monitor an access response from the slave module is defined, and the response time monitoring function can be enabled or disabled. Other parts are configured in the same manner as in the third embodiment.

  FIG. 9 is a flowchart illustrating an ASIC control procedure according to the fourth embodiment. In this flowchart, an access response monitoring ON determination step is provided as a step S202 after the step S101 of the flowchart of FIG. In this control procedure, it is set in advance whether to monitor the access response from the CPU 210 to the access response control register 102b before starting the data transfer between the master module 101 and the slave module 109 in the ASIC 100. Then, after the data transfer from the CPU 210 is started, according to the monitoring ON / OFF setting (step S202), if ON, the processing after step S102 is executed, and the response monitoring circuit 102 in the master module 101 is executed as in the third embodiment. Monitors the access response from the slave module 109. In the case of OFF, the processing from step S102 to step S107 is skipped and the processing is terminated, and the access response itself from the slave module 109 is not monitored. Since the other steps are the same as those in the third embodiment, description thereof is omitted.

  When configured and processed in this way, the access response monitoring function from the slave module 109 can be turned ON / OFF, so that an unintended interrupt to the CPU 210 can be prevented from occurring.

  FIG. 10 is a block diagram illustrating the configuration of the ASIC according to the fifth embodiment. In this embodiment, an access address register 102c readable by the CPU 210 is added to the response monitoring circuit 102 of the master module 101 in the fourth embodiment. The access address register 102c holds the last address requested for access. That is, in the fifth embodiment, the response monitoring circuit 102 monitors the access response from the slave module 109 as in the fourth embodiment, but each time the master module 101 issues an access request, the address is assigned to the access address register 102c. To store. Other parts are configured in the same manner as in the fourth embodiment.

  FIG. 11 is a flowchart illustrating an ASIC control procedure according to the fifth embodiment. In this flowchart, an access address store processing step is provided as step S203 between step S202 and step S102 in the flowchart of FIG. In this step, since the last address requested to be accessed is held, when a stall occurs between the master module 101 and the slave module 109 in the third embodiment, the address to which address is requested by reading the access address register 102c. It is possible to determine whether a stall has occurred after issuance. Since the other steps are the same as those in the fourth embodiment, description thereof is omitted.

  When configured and processed in this way, the final access address from the master module 101 can be determined, so that the number of steps for analyzing the cause of stall between modules can be reduced.

  FIG. 12 is a block diagram illustrating the configuration of the ASIC according to the sixth embodiment. In this embodiment, an access data register 102d readable by the CPU 210 is added to the response monitoring circuit 102 of the master module 101 in the fifth embodiment. The access data register 102d holds the last write data requested for write access or the last read data of the read access response. That is, in the sixth embodiment, the response monitoring circuit 102 monitors the access response from the slave module 109 as in the fifth embodiment. However, in the case of write access after storing the access address of the master module 101, the write data is changed to the access data. Store in the register 102d. In the case of read access, if there is an access response during access response monitoring, the read data at that time is stored in the access data register 102d. Other parts are configured in the same manner as in the fifth embodiment.

  FIG. 13 is a flowchart illustrating an ASIC control procedure according to the sixth embodiment. In this flowchart, the write access request determination procedure in step S204 and the write data store processing procedure in step S205 are provided between step S203 and step S102 in the fifth embodiment, and step S206 is executed between step S102 and step S105. A determination procedure for a read access request and a read data store processing procedure in step S207 are provided. Thus, after storing the access address in step S203, if there is a write access request (step S204-Yes), the write data is stored (step S205), and if there is no write access request, the processing from step S102 onward is executed. . If there is an access request in step S102 (step S102-Yes), it is checked whether or not there is a read access request (step S206). If there is a read access request, read data is stored (step S207). If there is no read access request, the down counter is reset to a fixed initial value in step S105 and the process is terminated.

  As a result, when a stall occurs between the master module 101 and the slave module 109, the access data register 102d is read so that the data when the stall occurs in the case of write access and the stall occurs in the case of read access. It is possible to discriminate data before one transaction.

  By configuring and processing in this way, the last write data requested by the master module 101 for the write access to the slave module 109 or the last read data of the read access response from the slave module 109 can be determined. The number of man-hours for analyzing the cause of stalls can be reduced.

It is a block diagram which shows an example of the system configuration using ASIC with which this invention is applied. 1 is a block diagram illustrating a configuration of an ASIC according to a first embodiment. 3 is a flowchart illustrating an ASIC control procedure according to the first embodiment. FIG. 6 is a block diagram illustrating a configuration of an ASIC according to a second embodiment. 6 is a flowchart illustrating an ASIC control procedure according to the second embodiment. FIG. 9 is a block diagram illustrating a configuration of an ASIC according to a third embodiment. 12 is a flowchart illustrating an ASIC control procedure according to the third embodiment. FIG. 10 is a block diagram illustrating a configuration of an ASIC according to a fourth embodiment. 14 is a flowchart illustrating an ASIC control procedure according to the fourth embodiment. FIG. 10 is a block diagram illustrating a configuration of an ASIC according to a fifth embodiment. 14 is a flowchart illustrating an ASIC control procedure according to the fifth embodiment. FIG. 10 is a block diagram illustrating a configuration of an ASIC according to a sixth embodiment. 14 is a flowchart illustrating an ASIC control procedure according to the sixth embodiment.

Explanation of symbols

100 ASIC
101 Master Module 102 Response Monitoring Circuit 102a Response Count Register 102b Access Response Control Register 102c Access Address Register 102d Access Data Register 103 Interrupt Generation Circuit 104 Interrupt Control Circuit 105 Arbiter 110 CPU Interface 120 Memory Unit 210 CPU

Claims (13)

A semiconductor integrated circuit comprising a plurality of functional modules for transmitting and receiving predetermined data,
A functional module having a master function for requesting data;
A functional module having a slave function of transmitting data in response to the request;
With
The function module having the master function has a function of monitoring the response to the request for a predetermined time. The semiconductor integrated circuit according to claim 1,
The function module having the master function has a function of generating an interrupt for notifying the host side when it detects that there is no response from the function module having the slave function for a predetermined time. . A semiconductor integrated circuit according to claim 2, wherein
The function module having the master function has a function of arbitrarily setting a response time from the function module having the slave function. A semiconductor integrated circuit according to claim 3, wherein
The function module having the master function has a function of enabling or disabling the function of monitoring the response time. A semiconductor integrated circuit according to claim 4, wherein
The function module having the master function has a function of holding the last address requested to be accessed. A semiconductor integrated circuit according to claim 5, wherein
The function module having the master function has a function of holding last write data requested for write access or last read data of a read access response. A semiconductor integrated circuit according to any one of claims 1 to 6, comprising:
The image processing apparatus according to claim 1, wherein the semiconductor integrated circuit includes a functional module that performs predetermined processing on image data that is input or read out from storage means. A communication control method between the functional modules in a semiconductor integrated circuit including a plurality of functional modules for transmitting and receiving predetermined data,
A functional module having a master function for requesting data;
A functional module having a slave function of transmitting data in response to the request;
With
The communication control method, wherein the functional module having the master function monitors the response to the request for a predetermined time. The communication control method according to claim 8, comprising:
The communication control method according to claim 1, wherein the functional module having the master function generates an interrupt for notifying the host side when detecting that there is no response from the functional module having the slave function for a predetermined time. The communication control method according to claim 9, comprising:
A communication control method, wherein the functional module having the master function arbitrarily sets a response time from the functional module having the slave function. The communication control method according to claim 10, comprising:
The communication control method, wherein the functional module having the master function enables or disables monitoring of the response time. The communication control method according to claim 11, comprising:
The communication control method, wherein the functional module having the master function holds the last address requested to be accessed. A communication control method according to claim 12, comprising:
The communication control method, wherein the functional module having the master function holds the last write data requested for write access or the last read data of a read access response.

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