TWI495264B - Clock-shared differential signaling interface and related method - Google Patents

Description

Clock sharing micro-distribution interface and related methods

The present invention generally relates to circuits and control methods associated with display devices. More particularly, the present invention relates to circuits and associated methods associated with timing controllers and interfaces between timing controllers and display devices.

The present application claims the benefit of the Korean Patent Application No. 10-2008-0097941, filed on Oct. 7, 2008, the disclosure of which is hereby incorporated by reference.

The total physical size of display devices such as monitors for computers and laptops, video displays, televisions and the like has greatly increased. At the same time, high definition (HD) functionality has been incorporated into such much larger display devices. Many display devices now operate at frame rates in excess of 120 Hz and enable more channels to be displayed with much higher resolution. All of the foregoing has caused a very real need for an increased rate of digital data supply for modern display devices.

A critical point along the digital data transfer path to the display device is the interface between the display device and the corresponding timing controller (TCON). It is expected that the data transfer rate between TCON and associated display devices will reach 500 to 2000 megabits per second (Mbps) in order to provide the necessary information to support the number and quality of video/audio channels promised to consumers. bandwidth. The current data transfer rate between the conventional TCON and the associated display device is about 100 to 200 Mbps.

Embodiments of the present invention provide a clock sharing micro-distribution interface and a method for driving output information to a display panel.

In accordance with at least one embodiment, the present invention provides an apparatus comprising a plurality of driver circuits, wherein each of the plurality of driver circuits provides output data, respectively. The apparatus also includes a timing controller that provides a first clock signal to the plurality of driver circuits via a multipoint connection and provides a separate differential data signal to each via a separate point-to-point connection Driver circuit.

In accordance with at least one embodiment, the present invention provides a display device that includes a display panel and a plurality of driver circuits that provide output data to the display panel, respectively. The display panel also includes a timing controller that provides a first clock signal to the plurality of driver circuits via a multipoint connection and provides a separate differential data signal to each via a separate point-to-point connection. A driver circuit.

In accordance with at least one embodiment, the present invention provides a method of driving output data to a display panel. The method includes: generating a first clock signal from a second clock signal; providing the first clock signal to each of the plurality of driver circuits via a multi-point connection; and connecting via a point-to-point connection Differential data signals are provided to the driver circuits, respectively. The method also includes regenerating a third clock signal from the first clock signal at each of the driver circuits; generating a third clock signal at each of the driver circuits And a portion of the output data of the received differential data signal; and providing the output data to the display panel.

The embodiments of the present invention are described with reference to the drawings, in which like reference characters

1 is a conceptual block diagram illustrating a clock sharing micro-distribution interface 1 in a display device in accordance with an embodiment of the present invention. In the embodiment illustrated in FIG. 1, the clock-sharing micro-distribution interface 1 includes a timing controller 20 coupled to a source driver including a plurality of source drivers 10-0 to 10-9. Unit 10. Although the source driver unit 10 illustrated in FIG. 1 includes ten source drivers, the source driver unit 10 can include any reasonable number of source drivers in accordance with other embodiments of the present invention.

In addition, the clock sharing micro-distribution interface 1 includes data bus rows DB0 to DB9. Each of the data bus bars DB0 to DB9 is connected between the timing controller 20 and a respective one of the plurality of source drivers 10-0 to 10-9. Therefore, the timing controller 20 supplies the differential data signals D0 to D9 to the source drivers 10-0 to 10-9 via the data bus bars DB0 to DB9, respectively. With this configuration, the data busses DB0 to DB9 form a "peer-to-peer" connection between the timing controller 20 and the source drivers 10-0 to 10-9. As used herein, a point-to-point connection between a timing controller and an associated driver specifically connects a timing controller to a given driver only. Thus, as this term is used herein, any connection (eg, a signal line or bus) that a timing controller provides to a number of signals to more than one drive (eg, a multipoint connection) is not considered a "point-to-point" "connection.

The clock sharing micro-distribution interface 1 also includes a shared differential clock signal bus 30 that is commonly coupled to the timing controller 20 and each of the plurality of source drivers 10-0 to 10-9. Therefore, the shared differential clock signal bus 30 forms a multipoint connection between the timing controller 20 and the plurality of source drivers 10-0 to 10-9 such that the timing controller 20 communicates via the shared differential clock signal bus The shared differential clock signal CLK is supplied to each of the source drivers 10-0 to 10-9.

With the foregoing configuration, the timing controller 20 in the clock sharing micro-distribution interface 1 of FIG. 1 supplies the differential data signal to the plurality of source drivers 10-0 to 10-9 via a point-to-point connection, and also via multiple The dot connection supplies the shared differential clock signal CLK to each of the source drivers 10-0 to 10-9. For the purposes of this description, it is assumed that the clock sharing micro-distribution interface 1 uses a two-bit quasi-transmission. As used herein, "two-bit quasi-transmission" is a signaling system that uses signals that transition between two meaningful logical levels, and that "multi-bit quasi-transmission" is meaningful for use in three or more A signaling system that signals the transition between logic levels.

In addition, the clock sharing micro-distribution interface in accordance with an embodiment of the present invention enables provisioning relative to a conventional multi-point interface without the use of multi-bit messaging or embedded-clock signaling Increase the data rate. Therefore, the clock sharing micro-distribution interface according to an embodiment of the present invention can provide an increased data rate while avoiding the disadvantages of multi-bit transmission and embedded clock transmission. As used herein, "embedded clock signaling" means transmitting a signal having an embedded clock signal.

Since the clock sharing micro-distribution interface 1 according to an embodiment of the present invention uses a two-bit quasi-signal, the circuits and processing in the timing controller 20 for supplying signals to the source drivers 10-0 to 10-9 are used. The circuits in the source drivers 10-0 to 10-9 from the signals received by the timing controller 20 can be less complex than the corresponding circuits in the conventional interface using embedded clock signaling and multi-bit signaling. . In addition, the circuit in the source drivers 10-0 to 10-9 sharing the micro-distribution interface 1 of the clock received by the timing controller 20 and the use of embedded clock signaling and two-bit signaling The corresponding circuit in the interface can also be less complicated.

Therefore, the size and power consumption of the circuit for implementing the clock sharing micro-distribution interface according to an embodiment of the present invention may be smaller than that for implementing the embedded clock signaling and the two-bit or multi-digit transmission. The size and power consumption of the circuit of the conventional interface of the letter. For example, the clock sharing micro-distribution interface in accordance with an embodiment of the present invention may omit the encoding and decoding circuitry necessary to implement embedded clock signaling.

In addition, a correspondence between a transport protocol for providing data from a timing controller to a source driver and a conventional interface using embedded clock signaling in a clock sharing micro-distribution interface according to an embodiment of the present invention Delivery protocols can be less complex.

Moreover, the speed at which the signal is supplied to the source drivers 10-0 to 10-9 of the clock sharing micro-distribution interface 1 can be less than the speed at which the signals are supplied to the source driver in the conventional interface using embedded clock signaling. . For example, the speed at which the signal is provided to the source drivers 10-0 to 10-9 of the clock sharing micro-distribution interface 1 can be provided to the source driver in a conventional interface using embedded clock signaling. The speed is less than 20%. Thus, the clock sharing micro-distribution interface in accordance with an embodiment of the present invention does not require a particular conventional hosted circuit necessary to supply relatively fast signal transmission speeds, such as often with conventional embedded clock interfaces. The circuit used. As a result, the size and power consumption of the circuitry for implementing the clock sharing micro-distribution interface in accordance with an embodiment of the present invention may be less than the size of conventional circuitry associated with conventional interfaces using embedded clock signaling and power consumption.

Moreover, the clock sharing micro-distribution interface in accordance with an embodiment of the present invention may also have reduced impedance mismatch relative to conventional interfaces using multi-point connections, and may thus provide improved signal integrity.

2 is a circuit diagram illustrating a clock sharing micro-distribution interface 2 in accordance with an embodiment of the present invention. The clock sharing micro-distribution interface 2 provides an interface between the timing controller 20 and the plurality of source drivers 10-0 to 10-N of the source driver unit 10, where N is a positive integer greater than two. The clock sharing micro-distribution interface 2 includes a point-to-point connection between the timing controller 20 and each of the source drivers 10-0 to 10-N, and the timing controller 20 provides the differential data to the source using the point-to-point connections. Each of the pole drivers 10-0 to 10-N. The clock sharing micro-distribution interface 2 further includes a shared differential clock signal bus 30 that provides a multipoint connection between the timing controller 20 and the source drivers 10-0 to 10-N. Further, the timing controller 20 supplies the shared differential clock signal CLK to each of the source drivers 10-0 to 10-N via a multipoint connection provided by the shared differential clock signal bus 30.

In the embodiment illustrated in FIG. 2, timing controller 20 receives primary clock signal MCLK and input data DA from, for example, a host (not shown) or external memory (not shown). The timing controller 20 autonomous clock signal MCLK generates a shared differential clock signal CLK, and provides the shared differential clock signal CLK to the source drivers 10-0 to 10- via a multipoint connection provided by the shared differential clock signal bus 30. Each of N. The frequency of the main clock signal MCLK is greater than the frequency of the shared differential clock signal CLK.

The timing controller 20 also generates differential data signals D00, D01 to DN0, DN1 from the input data DA, and supplies the differential data signals D00, D01 to DN0, DN1 to the source drivers 10-0 to 10-N, respectively. In addition, the timing controller 20 supplies the differential data signals to the source drivers via the data bus bars DB00, DB01 to DBN0, DBN1, and the data bus bars DB00, DB01 to DBN0, DBN1 form the timing controller 20 and the source driver 10-0. Point-to-point connection between 10-N. Therefore, in the embodiment illustrated in FIG. 2, the timing controller 20 supplies the differential data signals D00, D01 to DN0, DN1 to the source drivers 10-0 to 10, respectively, via the data bus bars DB00, DB01 to DBN0, DBN1, respectively. -N. In addition, each of the source drivers 10-0 to 10-N includes a clock regenerator (CR) circuit 11 including a phase locked loop (PLL) or a delay locked loop. (DLL) circuit. The clock sharing micro-distribution interface 2 can also include a terminating resistor (TR) circuit 22 coupled to the shared differential clock signal bus 30. In the illustrated embodiment of FIG. 2, termination resistor 22 is shown as a finite busbar component associated with the last source driver 10-N. However, the terminating resistor 22 can be provided as a decentralized component along the shared differential clock signal busbar 30. Regardless of the method provided, terminating resistor 22 can be used to correct impedance mismatch and reduce or eliminate signal reflection along shared differential clock signal bus 30.

By providing a clock signal having a relatively low frequency to the source driver, the signal integrity of the clock signal provided to the source driver via the shared differential clock signal bus 30 can be enhanced. In addition, the adverse effects of electromagnetic interference (EMI) on the clock signal can be reduced by providing a clock signal having a relatively low frequency to the source driver.

3 is a circuit diagram of a timing controller 20 that additionally details the clock sharing micro-distribution interface 2 of FIG. 2 in accordance with an embodiment of the present invention. In the embodiment illustrated in FIG. 3, timing controller 20 includes a data processing unit 22 and a clock generator 21. Further, the clock generator 21 includes a PLL circuit 23 and a clock divider 24.

The data processing unit 22 receives the input data DA from a host (not shown) or an external memory (not shown), and also receives the main clock signal MCLK. In addition, the data processing unit 22 receives the synchronous main clock signal FCLK from the clock generator 21. After processing the input data DA, the data processing unit 22 supplies the two differential data signals Di0 and Di1 to the source drivers 10-0 to 10-N via a point-to-point connection between the timing controller 20 and the source driver 10-i. Source driver 10-i. As used herein, "i" is an integer between 0 and N (including 0 and N), and each of the differential data signals Di0 and Di1 may be a pair of data signals. Referring to FIGS. 2 and 3, the data processing unit 22 can provide the two differential data signals Di0 and Di1 to the source driver 10 via respective point-to-point connections between the timing controller 20 and the source drivers 10-0 to 10-N. Each of the source drivers 10-i in 0 to 10-N. In addition, the data processing unit 22 can provide two or more differential data signals to each of the source drivers 10-i via two or more point-to-point connections between the timing controller 20 and the source driver 10-i. Additional point-to-point connections can be provided by additional data busses.

The clock generator 21 receives the main clock signal MCLK and supplies the shared differential clock signal CLK to each of the source drivers 10-0 to 10-N via a multipoint connection. The PLL circuit 23 of the clock generator 21 receives the main clock signal MCLK, generates a synchronous main clock signal FCLK, and supplies the synchronous main clock signal FCLK to the data processing unit 22 and the clock divider 24. The clock divider 24 receives the synchronous master clock signal FCLK and generates a shared differential clock signal CLK, and the timing controller 20 supplies the shared differential clock signal CLK to each of the source drivers 10-0 to 10-N. . In the embodiment illustrated in FIG. 3, the clock divider 24 receives the synchronous main clock signal FCLK derived from the autonomous clock signal MCLK, and divides the synchronous main clock signal FCLK to generate a shared differential clock signal CLK. . The frequency of the shared differential clock signal CLK is lower than the frequency of the main clock signal MCLK. The clock divider 24 can divide (for example) the frequency of the main clock signal MCLK by ten (10) to generate a shared differential clock signal CLK. Thus, for example, when the primary clock signal MCLK has a frequency of 1 Ghz, the shared differential clock signal CLK generated by the clock divider 24 can have a frequency of 100 Mhz.

4 is a circuit diagram additionally illustrating the source driver 10-i of the clock sharing micro-distribution interface 2 of FIG. 2 in accordance with an embodiment of the present invention. The source driver 10-i of FIG. 4 illustrates the configuration of each of the source drivers 10-0 to 10-N of FIG. 2 in accordance with an embodiment of the present invention. In the embodiment illustrated in FIG. 4, the source driver 10-i includes a source driver data processing unit 14, a de-warping unit 12, a deserializer unit 13, and a clock regenerator 11. The source driver data processing unit 14 includes a first data processing unit 14-1 and a second data processing unit 14-2. The first data processing unit 14-1 includes a first de-warping circuit 12-1 and a first des-serializer circuit 13-1. The second data processing unit 14-2 includes a second de-warping circuit 12-2 and a second deserializer circuit 13-2.

The clock regenerator 11 receives the shared differential clock signal CLK having a frequency lower than the frequency of the main clock signal MCLK, and regenerates an internal clock signal CLK'. The frequency of the internal clock signal CLK' is higher than the frequency of the shared differential clock signal CLK. Further, although the internal clock signal CLK' has a frequency greater than the frequency of the shared differential clock signal CLK, the frequency of the internal clock signal CLK' is not necessarily the same as the frequency of the main clock signal MCLK. As used herein, "regenerating" a clock signal means generating a second clock signal from a first clock signal (where the first clock signal has a frequency higher than the frequency of the second clock signal) Thereafter, a third clock signal is generated from the second clock signal (where the third clock signal has a frequency higher than a frequency of the second clock signal). However, the frequencies of the first clock signal and the third clock signal are not necessarily equal. Thus, as used herein, "regeneration" does not necessarily mean that the first clock signal has the same frequency as the third clock signal.

The clock regenerator 11 supplies the internal clock signal CLK' to the first de-warping circuit 12-1 and the second de-warping circuit 12-2. The clock regenerator 11 can include a PLL circuit or a DLL circuit. In addition, in the embodiment illustrated in FIG. 4, the source driver data processing unit 14 receives the first differential data signal Di0 and the second differential data signal Di1 from the timing controller 20 (see FIG. 2). As illustrated in FIG. 4, the first differential data signal Di0 includes complementary data signals Di0P and Di0R. The first data processing unit 14-1 receives the data signals Di0P and Di0R of the first differential data signal Di0 and the internal clock signal CLK', and generates an output data d_1 and an output data clock signal BCLK1. Specifically, the first de-warping circuit 12-1 receives the data signals Di0P and Di0R and the internal clock signal CLK', and generates the de-warped data signal Di0' and the de-warped internal clock signal CLK". The de-warping circuit 12-1 supplies the de-warped data signal Di0' and the de-twisted internal clock signal CLK" to the first deserializer circuit 13-1. The first deserializer circuit 13-1 generates an output data d_1 and an output data clock signal BCLK1 from the demodulated data signal Di0' and the demodulated internal clock signal CLK". According to an embodiment of the present invention, The source driver 10-i can supply the output data d_1 and the output data clock signal BCLK1 to the display panel 40 (see, for example, FIG. 6).

The source driver 10-i can provide color information as the output material d_1 to the display panel 40. For example, as illustrated in FIG. 10, the output data d_1 may be in the form of a multi-bit data packet D<9:0> continuously supplied to the display panel 40 through each cycle of the output data clock signal BCLK1. That is, the source driver 10-i can provide a data packet D<9:0> as the output data d_1 to the display panel 40 through each cycle of the output data clock signal BCLK1. Each data packet D<9:0> can provide color information of 10-bit depth to the display panel 40, and the display panel 40 can include a lock for latching individual bits in the data packet D<9:0> Save the block. The data latch provides the latched data as input data to an external digital to analog converter (DAC). As illustrated in FIG. 10, the source driver 10-i can continuously provide the following to the display panel 40 as the output data d_1: the data packet Ra of the data packet D<9:0> of the red color information is green The data packet of the color information packet D<9:0> and the data packet of the blue color information packet D<9:0> Ba. In addition, the output data d_1 is not limited to the 10-bit data packet D<9:0>. For example, the output data d_1 may be an 8-bit data packet D<7:0> each providing 8-bit depth color information or a 12-bit data packet D<11 each providing 12-bit depth color information: 0> form.

Similarly, as illustrated in Figure 4, the second differential data signal Di1 contains complementary data signals Di1P and Di1R. The second data processing unit 14-2 receives the data signals Di1P and Di1R of the second differential data signal Di1 and the internal clock signal CLK', and generates an output data d_2 and an output data clock signal BCLK2. Specifically, the second de-warping circuit 12-2 receives the data signals Di1P and Di1R and the internal clock signal CLK', and generates the de-warped data signal Di1' and the distorted internal clock signal CLK". The de-warping circuit 12-2 supplies the de-warped data signal Di1' and the de-warped internal clock signal CLK" to the second deserializer circuit 13-2. The second deserializer circuit 13-2 generates the output data d_2 and the output data clock signal BCLK2 from the decomposed data signal Di1' and the demodulated internal clock signal CLK". According to an embodiment of the present invention, The source driver 10-i can provide the output data d_2 and the output data clock signal BCLK2 to the display panel 40 (see, for example, Figure 6). The format of the output data d_2 can be similar to the output illustrated in Figure 10 and described above. An exemplary format of the data d_1. Further, as the output data d_1 corresponds to the output data clock signal BCLK1 illustrated in FIG. 10 and in the example described above, the output data d_2 may correspond to the output data clock signal BCLK2.

According to an embodiment of the invention, the clock regenerator 11 can generate a single phase clock signal from the shared differential clock signal CLK, which can be used to track the clock and data recovery circuit (CDR). Alternatively, in accordance with an embodiment of the present invention, the clock regenerator 11 may generate a plurality of polyphase clocks for operating the data latches in the source driver 10-i from the shared differential clock signal CLK. In this embodiment, the particular latched material can be selected for further processing in the source driver 10-i. In addition, according to an embodiment in which the clock regenerator 11 generates a plurality of multi-phase clock signals, the source driver data processing unit 14 of the source driver 10-i can receive based on one of the plurality of multi-phase clock signals. The data is distorted and deserialized.

The multi-phase clock signals can have different phases from each other and can be used to latch data inputs at relatively high speeds. For example, each of the multi-phase clock signals can be used to latch input data at half the data rate. Since the data is latched according to each of the multi-phase clock signals, the same data can be latched multiple times. Thus, a particular latched data among all of the latched data can be selected for further processing in the source driver 10-i. 11 shows an exemplary differential data signal Di0 and exemplary multiphase clocks Ph0, Ph1, and Ph2. In the example illustrated in FIG. 11, the multiphase clocks Ph0, Ph1, and Ph2 have phases different from each other, and are cycled at half the data rate with respect to the differential data signal Di0.

FIG. 5 illustrates a display driver integrated circuit (IC) module 60 in accordance with an embodiment of the present invention. In the embodiment illustrated in FIG. 5, display driver IC module 60 includes a clock sharing micro-distribution interface 2. The display driver IC module 60 includes a timing controller 20 and a source driver unit 10, and the source driver unit 10 includes source drivers 10-0 to 10-N. In addition, the timing controller 20 supplies the shared differential clock signal CLK to the source drivers 10-0 to 10-N via a multipoint connection provided by the shared differential clock signal bus 30. Moreover, in the display driver IC module 60, the timing controller 20 supplies two differential data signals to the source driver 10 via respective point-to-point connections between the timing controller 20 and the source drivers 10-0 to 10-N. Each of the source drivers 10-i in 0 to 10-N. These respective point-to-point connections are provided by data bus rows DB00, DB01 to DBN0, DBN1. In addition, the timing controller 20 can provide two or more differential data signals to each of the source drivers 10-i via two or more point-to-point connections between the timing controller 20 and the source driver 10-i. Additional point-to-point connections can be provided by additional data busses. In addition, the timing controller 20 receives the main clock signal MCLK and the input data DA from outside the display driver IC module 60.

FIG. 6 illustrates a display device 100 (which may also be referred to herein as display system 100) in accordance with an embodiment of the present invention. The display device 100 includes a timing controller 20, a source driver unit 10, a gate driver 50, and a display panel 40. The source driver unit 10 includes source drivers (SD) 10-0 to 10-N. In addition, display device 100 includes a clock-sharing micro-distribution interface similar to the clock-sharing micro-distribution interface illustrated in FIG. In particular, in the embodiment illustrated in FIG. 6, the timing controller 20 provides the shared differential clock signal CLK to the source drivers 10-0 to 10 via a multipoint connection provided by the shared differential clock signal bus 30. -N each. Further, the timing controller 20 supplies the differential data signals to the source drivers 10-0 to 10-N via point-to-point connections provided by the data bus bars DB00, DB01 to DBN0, DBN1 (see, for example, FIG. 2). In the embodiment illustrated in FIG. 6, the timing controller 20 connects the two differential data signals Di0 and Di1 via two data busses DBi0, DBi1 connected between the timing controller 20 and the source driver 10-i via a point-to-point connection. Provided to each source driver 10-i. In addition, the timing controller 20 can provide two or more differential data signals to each of the source drivers 10-i via two or more point-to-point connections between the timing controller 20 and the source driver 10-i. Additional point-to-point connections can be provided by additional data busses.

The source driver unit 10 can also provide various output signals to the display panel 40. In particular, according to an embodiment of the present invention, the source drivers 10-0 to 10-N can provide data and time signals to the display panel 40. For example, as illustrated in FIG. 4, the source driver 10-i outputs the output data d_1 and d_2 and outputs the output data clock signals BCLK1 and BCLK2. Each of the source drivers 10-0 to 10-N can provide an analog output data clock signal to the display panel 40, and the source driver unit 10 can thereby provide the data clock signal to the display panel 40.

Further, the gate driver 50 receives the gate signal GS from the timing controller 20 and supplies various output signals to the display panel 40. The gate signal GS supplied from the timing controller 20 to the gate driver 50 is a gate switch signal that periodically turns the gate driver in the gate driver 50 on and off.

In the embodiment illustrated in Figures 6-8, display panel 40 is an LCD display panel. However, the display panel 40 may be, for example, a PDP display panel, an OLED display panel, a flexible display panel, or the like. The display panel 40 includes a plurality of display circuits including, for example, a transistor T1, a capacitor C _LC, and a capacitor C _ST . Each of the capacitors C _LC and C _ST is connected between one of the terminals of the transistor T1 and the ground. Although FIG. 6 shows only one display circuit in display panel 40, display panel 40 can include a plurality of display circuits.

FIG. 7 illustrates a display device 101 in accordance with another embodiment of the present invention. As illustrated in FIG. 7, the display device 101 can include a source driver chip 200, wherein the timing controller 20, the source driver unit 10 (including the source drivers (SD) 10-0 to 10-N), and the connection timing control The busbars of the source 20 and the source driver unit 10 are disposed on the source driver wafer 200 (i.e., disposed on a single wafer). Additionally, display device 101 including source driver wafer 200 can be disposed in a single wafer package. Display panel 40, gate driver 50, and their respective configurations within display device 101 are similar to display panel 40, gate driver 50, and their respective configurations within display device 100 of FIG. Therefore, further description thereof will be omitted herein.

FIG. 8 illustrates a display device 102 in accordance with yet another embodiment of the present invention. As illustrated in FIG. 8, display device 102 can include a gate driver die 300 in which timing controller 20 and gate driver 50 are disposed on gate driver die 300 (i.e., disposed on a single wafer). However, the source driver unit 10 (including the source drivers (SD) 10-0 to 10-N) is not disposed on the gate driver wafer 300. Additionally, display device 102 including gate driver die 300 can be disposed in a single wafer package. Display panel 40, source driver unit 10, and their respective configurations within display device 102 are similar to display panel 40, source driver unit 10, and their respective configurations within display device 100. Therefore, further description thereof will be omitted herein.

9 is a flow chart outlining a method of driving output data to a display panel in accordance with an embodiment of the present invention. The method outlined in Figure 9 will be described with reference to Figures 2, 3, 4 and 6.

Referring to Figures 2, 3 and 9, the timing controller 20 autonomous clock signal MCLK generates a shared differential clock signal CLK (S100), wherein MCLK has a higher frequency than the frequency of the shared differential clock signal CLK. According to the embodiment illustrated in FIG. 3, the clock generator 21 of the timing controller 20 autonomous clock signal MCLK generates a shared differential clock signal CLK. Next, the timing controller 20 supplies the shared differential clock signal CLK to the source drivers 10-0 to 10-N via the multipoint connection, and supplies the differential data signals to the source drivers 10-0 to 10-N via the point-to-point connection (S102) ). In the embodiment illustrated in FIG. 2, the shared differential clock signal bus 30 provides a multipoint connection, and the data bus rows DB00, DB01 through DBN0, DBN1 provide a point-to-point connection. Each of the source drivers 10-0 to 10-N then regenerates the internal clock signal CLK' from the shared differential clock signal CLK (S104). The internal clock signal CLK' has a frequency higher than the frequency of the shared differential clock signal CLK, but the frequency of the internal clock signal CLK' is not necessarily the same as the frequency of the main clock signal MCLK. According to the embodiment illustrated in FIG. 4, the clock regenerator 11 of each of the source drivers 10-0 to 10-N regenerates the internal clock signal CLK' from the shared differential clock signal CLK. . According to an embodiment of the invention, the internal clock signal CLK' may be a single phase clock signal. Alternatively, in accordance with an embodiment of the present invention, the clock regenerator 11 may generate a plurality of polyphase clock signals from the shared differential clock signal CLK instead of the internal clock signal CLK'.

Next, referring to FIG. 4, the clock regenerator 11 of each source driver 10-i supplies the internal clock signal CLK' to the data processing unit 14 of the source driver 10-i (S106). Alternatively, according to an embodiment of the present invention, the clock regenerator 11 of each of the source drivers 10-i may provide a selected one of the plurality of multiphase clock signals to the source driver 10-i. Processing unit 14. Subsequently, the data processing unit 14 of each source driver 10-i de-distorts and deserializes the received differential data signal according to the internal clock signal CLK' (S108). Alternatively, in accordance with an embodiment of the present invention, each of the source drivers 10-i may receive a selected one of the plurality of polyphase clock signals from the clock regenerator 11 of the source driver 10-i. The received differential signals Di0 and Di1 are twisted and deserialized. Each source driver 10-i then supplies the processed material to the display panel (S110). For example, in the embodiment illustrated in FIG. 4, each source driver 10-i provides output data d_1 and d_2 and output material clock signals BCLK1 and BCLK2 to display panel 40 (see FIG. 6).

The method described above in accordance with an embodiment of the present invention can provide an increased data rate and a supply of clock signals separate from the differential data signal using a two-bit interface. Therefore, the method described above can avoid the disadvantages of using multi-bit transmission and embedded clock signaling. In addition, by providing a clock signal having a relatively low frequency to the source driver, the signal integrity of the clock signal provided to the source driver via the shared differential clock signal bus 30 can be enhanced. Moreover, the adverse effects on electromagnetic interference (EMI) of the clock signal can be reduced by providing a clock signal having a relatively low frequency to the source driver.

Embodiments of the present invention provide a clock sharing micro-distribution interface and a method for driving output data to a display panel. In the clock sharing micro-distribution interface, a timing controller provides a differential data signal to the source driver via a point-to-point connection and provides the shared differential clock signal to the source driver via the multipoint connection. The clock sharing micro-distribution interface according to an embodiment of the present invention can provide increased data transfer between the timing controller and the source driver without using multi-bit or embedded clock signaling rate. Thus, the clock-sharing micro-distribution interface in accordance with an embodiment of the present invention can provide an increased data rate without the disadvantages of using multi-bit or embedded clock signaling. Additionally, in a clock sharing micro-distribution interface in accordance with an embodiment of the present invention, a timing controller can provide a clock signal having a relatively low frequency to the source driver. Thus, the clock sharing micro-distribution interface in accordance with an embodiment of the present invention can enhance the signal integrity of the clock signal provided to the source driver and reduce the adverse effects of electromagnetic interference (EMI) on the clock signal.

Although the embodiments of the present invention have been described herein, the embodiments may be modified without departing from the scope of the invention as defined by the appended claims.

1. . . Clock sharing micro-distribution interface

2. . . Clock sharing micro-distribution interface

10. . . Source driver unit

10-0~10-9. . . Source driver (SD)

11. . . Clock regenerator (CR) circuit / clock regenerator

12. . . De-twist unit

12-1. . . First de-warping circuit

12-2. . . Second solution twist circuit

13. . . Deserializer unit

13-1. . . First deserializer circuit

13-2. . . Second deserializer circuit

14. . . Source driver data processing unit

14-1. . . First data processing unit

14-2. . . Second data processing unit

20. . . Timing controller

twenty one. . . Clock generator

twenty two. . . Terminating resistor (TR) circuit / data processing unit

twenty three. . . PLL circuit

twenty four. . . Clock divider

30. . . Shared differential clock signal bus

40. . . Display panel

50. . . Gate driver

60. . . Display driver integrated circuit (IC) module

100. . . Display device / display system

101. . . Display device

102. . . Display device

200. . . Source driver chip

300. . . Gate driver chip

C _LC . . . Capacitor

C _ST . . . Capacitor

DB0~DB9. . . Data bus

DB00~DBN0. . . Data bus

DB01~DBN1. . . Data bus

T1. . . Transistor

1 is a conceptual block diagram illustrating a clock sharing micro-distribution interface in a display device in accordance with an embodiment of the present invention;

2 is a circuit diagram illustrating a clock sharing micro-distribution interface in accordance with an embodiment of the present invention;

3 is a circuit diagram additionally illustrating in detail a timing controller of the clock sharing micro-distribution interface of FIG. 2, in accordance with an embodiment of the present invention;

4 is a circuit diagram additionally illustrating in detail a source driver of the clock sharing micro-distribution interface of FIG. 2, in accordance with an embodiment of the present invention;

5 illustrates a display driver integrated circuit module in accordance with an embodiment of the present invention;

Figure 6 illustrates a display device in accordance with an embodiment of the present invention;

Figure 7 illustrates a display device in accordance with another embodiment of the present invention;

Figure 8 illustrates a display device in accordance with yet another embodiment of the present invention;

9 is a flow chart outlining a method of driving output data to a display panel in accordance with an embodiment of the present invention;

10 is a timing diagram illustrating clock signals of an output data signal and an output data according to an embodiment of the present invention; and

11 is a timing diagram illustrating a differential data signal and a multi-phase clock in accordance with an embodiment of the present invention.

1. . . Clock sharing micro-distribution interface

10. . . Source driver unit

10-0~10-9. . . Source driver

20. . . Timing controller

30. . . Shared differential clock signal bus

DB0~DB9. . . Data bus

Claims (26)

A display driver integrated circuit includes: a plurality of driver circuits, wherein each of the plurality of driver circuits respectively provides output data; and has a multi-point connection to one of the plurality of driver circuits a resistive termination circuit coupled to the clock bus; and a timing controller, the timing controller providing a first clock signal to the plurality of plurality of connections via the multi-point connection of the clock bus The driver circuit provides a respective differential data signal to each of the driver circuits via a respective point-to-point connection, wherein each of the driver circuits includes a clock regenerator that receives the first clock signal and generates a The three-clock signal, and each of the driver circuits includes: a de-warping circuit, the de-warping circuit receiving the respective differential data signals and the third clock signal, and generating a distorted data signal and a fourth time a pulse signal; and a deserializer circuit, the deserializer circuit receiving the demodulated data signal and the fourth clock signal And generating the output data and a corresponding fifth clock signal. The display driver integrated circuit of claim 1, wherein the first clock signal is derived from a received second clock signal in the timing controller, and wherein the first clock signal is a shared differential signal Pulse signal. The display driver integrated circuit of claim 2, wherein one of the second clock signals has a frequency higher than a frequency of the first clock signal. The display driver integrated circuit of claim 3, wherein the timing controller includes a clock generator circuit, the clock generator circuit receives the second clock signal and generates the first clock from the second clock signal signal. The display driver integrated circuit of claim 4, wherein the clock generator circuit comprises: a phase locked loop (PLL) circuit, the phase locked loop (PLL) circuit receives the second clock signal and generates a third time And a clock divider, the clock divider receives the third clock signal and divides the frequency to generate the first clock signal. The display driver integrated circuit of claim 1, wherein one of the third clock signals has a frequency higher than the frequency of the first clock signal. The display driver integrated circuit of claim 1, wherein the timing controller and the plurality of driver circuits are generally integrated in a single integrated circuit chip. The display driver integrated circuit of claim 7, wherein the first clock signal is derived from a second clock signal in the timing controller. The display driver integrated circuit of claim 8, wherein one of the second clock signals has a frequency higher than a frequency of the first clock signal. The display driver integrated circuit of claim 9, wherein the timing controller includes a clock generator circuit, the clock generator circuit receives the second clock signal and generates the first clock from the second clock signal Signal, and The first clock signal is a shared differential clock signal. The display driver integrated circuit of claim 1, wherein each of the respective point-to-point connections comprises a data bus connected between the timing controller and only one of the plurality of driver circuits. The display driver integrated circuit of claim 1, wherein each of the driver circuits is a source driver circuit. A display device comprising: a display panel; a plurality of driver circuits, wherein the driver circuits respectively provide output data to the display panel; and have a multi-point connection to one of the plurality of driver circuits, a clock bus; a resistive termination circuit connected to the clock bus; and a timing controller, the timing controller providing a first clock signal to the plurality of driver circuits via the multipoint connection of the clock bus and Providing a respective differential data signal to each of the driver circuits via a respective point-to-point connection, wherein each of the driver circuits includes a clock regenerator that receives the first clock signal and generates a third clock The signal, and each of the driver circuits includes: a de-warping circuit, the de-warping circuit receiving the respective differential data signals and the third clock signal, and generating a de-twisted data signal and a fourth clock signal; and a deserializer circuit, the deserializer circuit receives the demodulated data signal and the fourth clock signal, and generates the output data and a corresponding fifth clock signal. The display device of claim 13, wherein the first clock signal is derived from the received second clock signal in the timing controller. The display device of claim 14, wherein one of the second clock signals has a frequency higher than a frequency of the first clock signal. The display device of claim 15, wherein the timing controller includes a clock generator circuit, the clock generator circuit receives the second clock signal and generates the first clock signal from the second clock signal, and The first clock signal is a shared differential clock signal. The display device of claim 13, further comprising: a gate driver that receives a gate signal from the timing controller and provides an output signal to the display panel, wherein the timing controller and the driver The circuitry is typically integrated into a single integrated circuit chip. The display device of claim 17, wherein the source driver unit, the gate driver, the timing controller, and the display panel are disposed in a single package. The display device of claim 13, further comprising: a gate driver that receives a gate signal from the timing controller and provides an output signal to the display panel, wherein the timing controller and the gate The pole drivers are typically integrated into a single integrated circuit chip. The display device of claim 19, wherein the driver circuit, the gate driver, the timing controller, and the display panel are disposed in a single package. A method for driving output data to a display panel, the method comprising: generating a first clock signal from a second clock signal; providing the first clock signal to a clock bus having a multi-point connection, One of the resistive termination circuits is coupled to the clock bus; the multi-point connection of the clock bus provides the first clock signal to each of the plurality of driver circuits; via respective point-to-point Connecting, respectively, the differential data signals to the driver circuits; regenerating a third clock signal from the first clock signal at each of the driver circuits; at each of the driver circuits Generating a portion of the output data relating to the third clock signal and the received differential data signal; and providing the output data to the display panel, wherein for each of the driver circuits, And generating, in each of the driver circuits, a portion of the output data relating to the internal clock signal and the received differential data signal comprising: generating Deriving a distorted data signal and a fourth clock signal of the third data signal; and generating a distorted data signal and the fourth clock signal using a deserializer circuit The part of the output data and a corresponding number Five clock signals. The method of claim 21, wherein one of the second clock signals has a frequency higher than a frequency of the first clock signal; and wherein one of the third clock signals has a higher frequency than the first clock signal frequency. The method of claim 21, further comprising: providing a fifth clock signal to the display panel for each of the driver circuits. The method of claim 22, wherein generating the first clock signal from the second clock signal comprises: providing the second clock signal to a timing controller; generating a fourth time from the second clock signal a pulse signal; and generating the first clock signal from the fourth clock signal. The method of claim 23, further comprising: providing input data to the timing controller; and wherein each of the differential data signals is provided to each of the driver circuits via respective point-to-point connections comprising: from the input data Generating the differential data signals for the second clock signal; and providing the differential data signals to the driver circuits via a plurality of data busses, wherein each of the data bus bars is connected to the Only one of the timing controller and the driver circuits. The method of claim 22, wherein each of the driver circuits Retrieving the third clock signal from the first clock signal includes providing, for each of the driver circuits, the first clock signal to a clock regenerator of the driver circuit.