TWI494984B - Semiconductor process - Google Patents

Description

Semiconductor process

The present invention relates to a semiconductor process, and more particularly to a semiconductor process for etching a recess using an etchant containing H ₂ O ₂ .

As semiconductor processes enter the deep submicron era, such as processes below 65 nanometers (nm), the drive current of MOS transistor components has become increasingly important. In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to strain the germanium lattice of the gate channel portion, so that the charge passes through the strain gate channel. The movement force at the time increases, thereby achieving the purpose of making the MOS transistor operate faster.

Figures 1-2 are schematic cross-sectional views of conventional semiconductor processes for use in strain enthalpy techniques. As shown in FIG. 1, a semiconductor structure 10 includes a substrate 12, and a gate structure 14 is formed on the substrate 12. The gate structure 14 can have a gate dielectric layer 14a and a gate. The electrode 14b, a side wall 14c and a cover layer 14d. Next, an ion implantation process is performed to form source/drain regions in a specific region 16 on both sides of the sidewalls 14c. Thereafter, a dry etching process is performed on the specific region 16 to form a recess of a predetermined depth (as shown in FIG. 1). Subsequently, ammonia (NH ₄ OH) is used as an etchant, and a wet etching process is performed on the specific region 16 to form a groove having a V-shaped structure (as shown in FIG. 2). Thereafter, an epitaxial process is performed to form an epitaxial layer filled in the recess (not shown).

It is worth noting that the groove etched with NH ₄ OH as an etchant has a bottom-like structure similar to a V-shape, and this V-shaped structure causes a problem of leakage current in the fabricated semiconductor element, thereby reducing The electrical quality of the semiconductor component. However, with the development of the industry, as the size of the semiconductor component is gradually reduced, the effect of the above-described etched groove structure on the electrical quality will become more serious.

The present invention provides a semiconductor process that solves the above problems by etching a recess having a flat bottom using an etchant containing H ₂ O ₂ .

The present invention also provides a semiconductor process that etches a semiconductor component having good electrical quality using an etchant containing NH ₄ OH/H ₂ O ₂ .

The present invention provides a semiconductor process comprising providing a substrate having a specific region defined thereon and performing an etching process for etching a specific region to form a recess using an etchant containing H ₂ O ₂ .

In an embodiment of the invention, the etching process includes a wet etching process, and the etchant of the wet etching process further comprises NH ₄ OH.

In a preferred embodiment, the volume percentage of H ₂ O ₂ is less than one percent of the volume percentage of NH ₄ OH. Further, in another preferred embodiment, the pH of the etchant of NH ₄ OH/H ₂ O ₂ is substantially greater than 10, and the temperature of the etchant of NH ₄ OH/H ₂ O ₂ is substantially between 25. ~80 °C.

In accordance with a preferred embodiment of the present invention, the etch process further includes a dry etch process prior to the wet etch process described above. In addition, the semiconductor process of the present invention may further comprise an epitaxial process for forming an epitaxial layer in the recess, wherein the epitaxial layer may further comprise a germanium epitaxial layer or a germanium carbon epitaxial layer, and the recessed layer The trough can include a flat bottom groove. In one embodiment, the semiconductor process of the present invention includes a cleaning step for removing an oxide layer on the surface of the substrate prior to the etching process. In other embodiments, the semiconductor process of the present invention includes a cleaning process for cleaning the recesses, wherein the cleaning process can include a cleaning solution containing NH ₄ OH/H ₂ O ₂ and the cleaning solution of H ₂ O ₂ The volume percentage is greater than or equal to the volume percentage of NH ₄ OH.

In one embodiment of the invention, the gate structure includes a gate dielectric layer and a gate electrode, and the specific region may include a source/drain region. The substrate can be a tantalum substrate, and the etchant containing NH ₄ OH/H ₂ O ₂ etches the (100) and (110) planes of the tantalum substrate at an etch rate greater than the (111) plane of the etched tantalum substrate.

The invention also provides a semiconductor process comprising: providing a substrate; forming a gate structure on the substrate, wherein the edge of the gate structure defines a specific region on the substrate; performing an etching process to contain an NH An etchant of ₄ OH/H ₂ O ₂ etches away a specific region to form a recess; and forms an epitaxial layer to fill the recess.

In a preferred embodiment, the volume fraction of H ₂ O ₂ in the wet etch process is less than one percent of the volume percent of NH ₄ OH. Further, in another preferred embodiment, the etchant of NH ₄ OH/H ₂ O ₂ has a pH substantially greater than that of the etchant of NH ₄ OH/H ₂ O ₂ is generally between 25 and 80. °C.

In accordance with a preferred embodiment of the present invention, the etch process further includes a dry etch process prior to the wet etch process described above. In addition, the semiconductor process of the present invention may further comprise an epitaxial process for forming an epitaxial layer in the recess, wherein the epitaxial layer may further comprise a germanium (SiGe) epitaxial layer or a germanium carbon (SiC). The epitaxial layer, and the groove is a flat bottom groove. In one embodiment, the semiconductor process of the present invention includes a cleaning step for removing an oxide layer on the surface of the substrate prior to the etching process. In other embodiments, the semiconductor process of the present invention includes a cleaning process for cleaning the recesses, wherein the cleaning process can include a cleaning solution containing NH ₄ OH/H ₂ O ₂ and the cleaning solution of H ₂ O ₂ The volume percentage is greater than or equal to the volume percentage of NH ₄ OH.

In one embodiment of the invention, the gate structure includes a gate dielectric layer and a gate electrode, and the specific region may include a source/drain region. The substrate can be a tantalum substrate, and the etchant containing NH ₄ OH/H ₂ O ₂ etches the (100) and (110) planes of the tantalum substrate at an etch rate greater than the (111) plane of the etched tantalum substrate.

Based on the above, the present invention proposes a semiconductor process for etching a recess using an etchant containing H ₂ O ₂ , particularly an etchant containing NH ₄ OH/H ₂ O ₂ . In particular, the semiconductor process can slow down the etching rate of the substrate, and can etch a groove containing a flat bottom, thereby preventing the conventional etchant from etching the shape of the groove having the bottom of the V-shaped structure, resulting in leakage. The problem of current, thus improving the electrical quality of the device.

3-6 are schematic cross-sectional views showing a semiconductor process in accordance with a preferred embodiment of the present invention.

Referring to FIG. 3, first, a substrate 110 is provided. The substrate 110 can be a single crystal coffin with or without dopants. Next, a desired well doped region is formed in the substrate 110, and a desired insulating layer, such that a semiconductor element, such as a transistor or other electronic device, subsequently formed on the substrate 110, is similar to the other adjacent thereto. The semiconductor component (not shown) is insulated. The insulating layer can be, for example, a trench insulating structure. The manufacturing method can be performed by etching a recess and depositing an oxide layer in the recess, which will not be described here. In an embodiment, the trench isolation structure is a shallow trench isolation region (STI), but the invention is not limited thereto.

Next, a gate structure 120 is formed on the substrate 110. The gate structure 120 mainly includes a gate dielectric layer 122 and a gate electrode 124. The gate structure 120 can be formed by a heat treatment or a deposition process to form a gate dielectric layer on the substrate 110. 122. Then, a gate electrode 124 and a cap layer 126 are sequentially deposited on the gate dielectric layer 122, and then patterned by using a patterned photoresist (not shown). Transfer process, but the invention is not limited thereto. The gate dielectric layer 122 may be a high dielectric constant material such as hafnium oxide, tantalum nitride, hafnium oxynitride, or metal oxide, and the gate electrode 124 may be heavily doped polysilicon or include titanium or tantalum. The metal gate of a metal alloy such as titanium nitride, tantalum nitride or tungsten, and the cover layer 126 may be tantalum nitride or the like.

In addition, the gate structure 120 may further include sidewall spacers 130 formed on both sides of the gate structure 120. As such, its edges may define a particular region 140 on the substrate 110. In the present embodiment, the specific region 140 is a source/drain region (hereinafter, the source/drain region 140 represents the specific region 140, but the specific region 140 of the present invention may also be defined in other regions that need to be etched into grooves), The sidewall spacer 130 is, for example, a tantalum nitride layer, which can be used together with the cap layer 126 as a hard mask for subsequent ion implantation and etching processes to form the source/drain region 140. Furthermore, the sidewall 130 of the present embodiment may include a multilayer structure such as an inner sidewall spacer 132 and an outer sidewall spacer 134.

Thus, after the sidewalls 132 are formed on the gate structure 120, an ion implantation process may be performed to form a lightly doped source/drain region 150 in the substrate 110 on opposite sides of the gate structure 120. . Next, sidewall spacers 134 are formed on both sides of the sidewall spacers 132. Next, another ion implantation is performed with the gate structure 120 and the sidewall spacers 134 as hard masks to form the source/drain regions 140. The above-described method for fabricating the gate structure 120 and the source/drain region 140 of the present embodiment is well known to those skilled in the art, and the gate structure 120, the sidewall spacers 130, and the lightly doped source/germanium are known. The pole region 150 and the source/drain region 140 may also be formed in other manners or in different order, and the invention is not limited thereto. For example, if the present invention is applied to a gate last process, then the gate electrode 124 in the gate structure 120 is only a metal gate.

Next, referring to FIG. 5, after forming the source/drain region 140, an etching process is performed. The etching process includes at least one wet etching process, which is an etchant containing H ₂ O ₂ to etch the source/ The drain region 140 forms a recess 160. It is to be noted that the groove 160 etched by the etchant containing H ₂ O ₂ is a flat-bottomed groove. Compared with the prior art, the groove etched by the NH ₄ OH etchant can flatten the V-shaped structure having the bottom end of the sharp corner, thereby avoiding the occurrence of leakage current of the semiconductor element. In other words, the etchant containing H ₂ O ₂ can slow down the etch rate of the etchant to the substrate 110 down. In a preferred embodiment, the etchant is an aqueous solution containing NH ₄ OH/H ₂ O ₂ , and the volume of H ₂ O ₂ added to NH ₄ OH is less than one percent of the volume of NH ₄ OH. In addition, the pH of the etchant of NH ₄ OH/H ₂ O ₂ is substantially greater than 10, and the operating temperature of the etchant of NH ₄ OH/H ₂ O ₂ is room temperature, if the temperature is better under the preferred operation. It is roughly between 25 and 80 °C. For example, if the substrate 110 is a germanium substrate and the germanium substrate is etched with an etchant containing NH ₄ OH/H ₂ O ₂ , the etching rate of the etchant on the tantalum substrate (100) and (110) plane will be greater than The etch rate of the (111) face of the ruthenium substrate is etched so that a groove 160 having a flat bottom can be etched.

In addition, referring to FIG. 4-5, the etching process preferably further includes a dry etching process (such as FIG. 4) and a wet etching process (such as FIG. 5), that is, performing etching agent removal source/drainage. Prior to region 140, a dry etch process S may be performed, such as plasma etching. In a preferred process operation, since the etching rate of the dry etching process S is faster, the substrate 110 may be first etched by a dry etching process S to a predetermined depth (the depth dimension is set according to actual needs). A groove 160 having a flat bottom shape is continuously etched by a wet etching process containing NH ₄ OH/H ₂ O ₂ as an etchant. In this way, not only the rate of the etching process can be accelerated, but also the amount and cost of the wet etching etchant can be saved.

Next, referring to FIG. 6 , after the recess 160 is etched, an epitaxial process is performed to form an epitaxial layer 170 filled in the recess 160 , wherein the epitaxial layer 170 is, for example, an epitaxial layer or A carbon epitaxial layer.

In addition, the present invention may further comprise a cleaning step before performing the etching process of the recess, wherein the cleaning step is performed, for example, by diluting hydrofluoric acid (DHF) and deionized water as a cleaning agent, before performing the etching process. A native oxide or the like on the surface of the substrate 110 is removed.

Moreover, after forming the recess 160 and forming an epitaxial layer, the present invention may also perform a cleaning process for cleaning the recess 160 to remove the microparticles attached to the recess 160 or even the surface of the substrate 110. For example, the residue after etching. This cleaning process utilizes standard clean cleaning step 1 (standard clean, SC-1) with NH ₄ OH/H ₂ O ₂ /H ₂ O (volume ratio: 1:1:5 to 1:2:7) The cleaning temperature is 75~85 °C, which mainly uses H ₂ O ₂ to oxidize the surface layer of the substrate and the groove to form an oxide layer, and then utilizes the weak alkalinity of NH ₄ OH to dissolve the formed oxide layer by hydrolysis. Further, the fine particles adsorbed on the oxide layer can be removed. Moreover, in an alkaline aqueous solution, the microparticles are negatively charged at the same time as the surface of the wafer, and the microparticles are removed by the "double layer repulsive force". Therefore, the proportion of the standard wet cleaning step 1 composition, the volume percentage of H ₂ O ₂ must be greater than or equal to the volume percentage of NH ₄ OH. In addition, the standard wet cleaning step 1 can be as high as 75~85 °C cleaning solution temperature, which can increase the kinetic energy of the adsorbed particles and leave the wafer surface.

As described above, the embodiment shown in FIGS. 3 to 6 utilizes an etchant containing NH ₄ OH/H ₂ O ₂ to etch a flat-bottomed groove 160 in the source/drain region. Further, the problem of leakage current of the semiconductor element is improved; however, the present invention can also be used to form a substrate 110 of another structure for etching a groove, and in particular, the present invention is particularly suitable for etching a flat bottom. The structure of the groove.

In summary, the present invention proposes a semiconductor process that etches a recess using an etchant containing H ₂ O ₂ , particularly an etchant containing NH ₄ OH/H ₂ O ₂ . In particular, the semiconductor process can slow down the etch rate for the substrate, for example, the etch rate of the ruthenium substrate (100) and (110) plane is greater than the etch rate of the (111) plane of the etch ruthenium substrate, and a flat bottom can be etched. The groove shape avoids the shape of the groove etched by the conventional etchant, causing a problem of leakage current, thereby improving the electrical quality of the device.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Semiconductor structure

110. . . Substrate

120. . . Gate structure

122. . . Gate dielectric layer

124. . . Gate electrode

130. . . Side wall

132. . . Inner side wall

134. . . Outer side wall

140. . . Specific area (source/bungee area)

150. . . Lightly doped source/drain region

160. . . Groove

170. . . Epitaxial layer

S. . . Dry etching process

Figures 1-2 are schematic cross-sectional views of conventional semiconductor processes for use in strain enthalpy techniques.

3-6 are schematic cross-sectional views of a semiconductor process applied to a strain enthalpy technique in accordance with a preferred embodiment of the present invention.

100. . . Semiconductor structure

110. . . Substrate

120. . . Gate structure

122. . . Gate dielectric layer

124. . . Gate electrode

130. . . Side wall

132. . . Inner side wall

134. . . Outer side wall

160. . . Groove

Claims (17)

A semiconductor process comprising: providing a substrate, wherein the substrate comprises a substrate, and a specific region is defined thereon; and performing an etching process to etch the specific region by using an etchant containing H ₂ O ₂ Forming a recess, wherein the etching process includes a wet etching process, and etching the etch rate of the (100) and (110) faces of the germanium substrate by the wet etching process is greater than etching rate of the (111) face of the germanium substrate . The semiconductor process of claim 1, wherein the etchant further comprises NH ₄ OH, and in the etchant, the volume percentage of H ₂ O ₂ is less than one percent by volume of NH ₄ OH . The semiconductor process of claim 2, wherein the etchant has a pH substantially greater than 10 and the wet etch process has a temperature range generally between 25 and 80 °C. The semiconductor process of claim 1, wherein the etching process further comprises a dry etching process prior to the wet etching process. The semiconductor process of claim 1, wherein the specific region comprises a source/drain region. The semiconductor process of claim 1, further comprising an epitaxial process for forming an epitaxial layer in the recess. The semiconductor process of claim 1, wherein the recess comprises a flat bottom recess. The semiconductor process of claim 1, further comprising a cleaning step performed to remove an oxide layer on the surface of the substrate prior to the etching process. The semiconductor process of claim 1, further comprising a cleaning process for cleaning the recess, wherein the cleaning process of the cleaning process comprises NH ₄ OH/H ₂ O ₂ and the volume of H ₂ O ₂ The percentage is greater than or equal to the volume percentage of NH ₄ OH. A semiconductor process comprising: providing a substrate, wherein the substrate is a germanium substrate; forming a gate structure on the substrate, wherein an edge of the gate structure defines a source on the substrate/ a draining region; performing an etching process to etch the source/drain region by an etchant containing NH ₄ OH/H ₂ O ₂ to form a recess having a flat bottom, wherein the etching process includes a wet etching process And etching the etch rate of the (100) and (110) planes of the germanium substrate by the wet etching process is greater than etching the (111) plane of the germanium substrate; and forming an epitaxial layer to fill the recess. The semiconductor process of claim 10, wherein in the etchant, the volume percentage of H ₂ O ₂ is less than one percent of the volume percentage of NH ₄ OH. The semiconductor process of claim 11, wherein the etchant has a pH substantially greater than 10 and the wet etch process has a temperature range generally between 25 and 80 °C. The semiconductor process of claim 11, wherein the etching process further comprises a dry etching process prior to the wet etching process. The semiconductor process of claim 10, further comprising performing at least one ion implantation process on the source/drain region prior to the etching process. The semiconductor process of claim 10, wherein the epitaxial layer comprises a tantalum epitaxial layer or a tantalum carbon epitaxial layer. The semiconductor process of claim 10, further comprising a cleaning step performed to remove an oxide layer on the surface of the substrate prior to the etching process. The semiconductor process of claim 10, further comprising a cleaning process for cleaning the recess, wherein the cleaning process of the cleaning process comprises NH ₄ OH/H ₂ O ₂ and the volume of H ₂ O ₂ The percentage is greater than or equal to the volume percentage of NH ₄ OH.