TWI493878B - System of using a low-cost data weighted averaging algorithm to improve the linearity of a dac circuit with merged capacitor switching technique - Google Patents

Description

Data Weighted Average Algorithm System for Improving Linearity of Digital Analog Conversion Circuit of Capacitor Combining Switching Technology

The invention relates to the technical field of data weighted averaging (DWA), in particular to a data weighted average algorithm system for improving the linearity of a digital analog conversion circuit of a capacitance combining switching technique.

Conventional digital analog converter (DAC) circuits use a combination of capacitance techniques to double the capacitance of each unit capacitor in the circuit to directly and effectively improve the problem of capacitance mismatch between the capacitors due to process errors. Fig. 1(A) and Fig. 1(B) are schematic diagrams showing the combination of conventional techniques. As shown in FIG. 1(A) and FIG. 1(B), the capacitor C ₁ and the capacitor C _{2 are} combined into C ₀ ', and the capacitor C ₃ and the capacitor C _{4 are} combined into C ₁ ', and the capacitor C ₅ , Capacitor C _{6 is} combined into C ₂ '. Prior to combining, capacitors C ₁ -C ₆ can be connected to a positive reference voltage (+V _ref ) or a negative reference voltage (-V _ref ). As shown in FIG. 1B, the combined capacitor C ₀ '~C ₂ ' may be connected to the positive reference voltage (+V _ref ), a negative reference voltage (-V _ref ), or a common mode reference voltage (V _cm ).

FIG. 2 is a comparison diagram of a conventional digital analog-to-digital converter (DAC) circuit using a capacitance combining technique and a digital analog-to-digital converter (DAC) circuit. Although the current analog-to-digital converter (DAC) circuit has used this capacitor combining technique to double the capacitance of each unit capacitor in the circuit, the method is directly and effectively improved because the total capacitance value required for the circuit is maintained. The problem that the capacitance caused by the error in the process does not match each other, and the degree of improvement is achieved by achieving a high resolution. The degree of delta-sigma modulator is still quite limited. At the same time, there is no correlation technique for data weighted average algorithm data weighted average (DWA) to improve the linearity of such a digital analog converter using capacitance combining techniques. Therefore, the present invention proposes a data weighted average algorithm system for improving the linearity of a digital analog conversion circuit of a capacitance combining switching technique.

The main object of the present invention is to provide a data weighted average algorithm system for improving the linearity of a digital analog conversion circuit of a capacitor combining switching technique, which can reduce the problem of harmonic distortion caused by mismatch between capacitors, and can also reduce In addition to the complexity of the circuit implementation, the area can be effectively reduced to achieve the effect of reducing the manufacturing cost of the integrated circuit.

According to a feature of the present invention, the present invention provides a data weighted average algorithm system for improving the linearity of a digital analog conversion circuit of a capacitance combining switching technique for setting a plurality of unit capacitances connected to a common mode reference voltage (V _cm ). Configuration, the data weighted average algorithm system includes a 2's complement correction circuit, an indicator generator circuit, a decoder circuit, a binary code to temperature code conversion circuit, and a barrel shifter (barrel shifter) circuit, and a back end to generate logic circuit for controlling unit capacitance signal. The 2's complement correction circuit receives an N-bit binary code input signal, and the 2's complement correction circuit corrects a partial binary code input signal of the N-bit binary code input signal to correctly generate a connection to The binary code signal of the number of unit capacitances of the common mode reference voltage. The indicator generator circuit is connected to the complement correction circuit of the 2, according to the binary code signal, to update the start address binary code signal that points to the next selection of the plurality of unit capacitors. The decoder circuit is connected to the indicator generator circuit for converting the start address binary code signal outputted by the indicator generator circuit into an index signal of 2 ^N-1 bits respectively pointing to a plurality of unit capacitors, The barrel shifter circuit is controlled to point to the first unit capacitance that is selected next time. The binary code to temperature code conversion circuit is connected to the 2's complement correction circuit, and the binary code to temperature code conversion circuit converts the binary code output signal output by the 2's complement correction circuit into a temperature code output signal . The barrel shifter circuit is coupled to the decoder circuit and the binary code to temperature code conversion circuit to generate a first control signal that selects a unit capacitance connected to the common mode reference voltage. The back end generates a logic circuit for controlling the unit capacitance signal to be connected to the barrel shifter circuit to generate second and third control signals connected to a unit capacitance of a positive reference voltage and a negative reference voltage.

3 is a block diagram of a data weighted average algorithm system 300 for linearity conversion of a digital analog conversion circuit of the improved capacitance combining switching technique of the present invention for setting a plurality of unit capacitances connected to a common mode reference voltage (V _cm ). Configuration. The data weighted average algorithm system 300 includes a 2's complement correction circuit 310, an indicator generator circuit 320, a decoder circuit 330, a binary code to temperature code conversion circuit 340, and a barrel shifter (barrel The shifter circuit 350 and a back end generate a logic circuit 360 for controlling the unit capacitance signal.

The 2's complement correction circuit 310 receives an N-bit binary code input signal (B<3:0>). For convenience of explanation, in the present embodiment, N is 4. The 2's complement correction circuit corrects a partial binary code input signal (B<2:0>) of the N-bit binary code input signal to correctly generate a connection to the common mode reference voltage ( _Vcm ). A number of binary code signals (B _C <3:0>) of the number of unit capacitors.

4 is a flow chart showing the operation of the complement correction circuit 310 of the second embodiment of the present invention. As shown in FIG. 4, in step (A), the 2's complement correction circuit 310 inputs the N-bit binary code input signal (B<3:0>). In the step (B), the 2's complement correction circuit 310 determines the highest bit of the N-bit input signal. If the highest bit is 1, the step (C) is performed to convert the N-bit input signal. If it is 2's complement, if the highest bit is 0, then step (C) is executed, and no change is made to the N-bit input signal.

5(A) and 5(B) are block diagrams of the 2's complement correction circuit 310. As shown in FIG. 5A, the 2's complement correction circuit 310 includes a plurality of XOR logic gates 52 and a half adder circuit 51. Fig. 5B is a circuit diagram of the half adder circuit. As shown in FIG. 5(B), the half adder circuit 51 is composed of a plurality of inverters (INV) 53 and a NAND gate 54.

The indicator generator circuit 320 is connected to the complement correction circuit 310 of the 2, according to the binary code signal (B _C <2:0>), to update the start address of the majority of the unit capacitors to be selected next time. Binary code signal (P _b <2:0>).

The indicator generator circuit 320 adds each of its input signals to the last indicator signal to generate the updated start address signal (P _b <2:0>).

6 is a block diagram of an indicator generator circuit 320 of the present invention. As shown in FIG. 6, the indicator generator circuit 320 is composed of a full adder 610 and a D-type flip-flop 620. Figure 7 is a circuit diagram of the full adder 610 of the present invention. Figure 8 is a circuit diagram of a D-type flip-flop 620 of the present invention.

The decoder circuit 330 is coupled to the indicator generator circuit 320 for converting the start address binary code signal (P _b <2:0>) output by the indicator generator circuit into 2 ^N-1 bits. Index signals (P<7:0>) pointing to the majority of the unit capacitors, respectively, to control the barrel shifter circuit to point to the first unit capacitor selected next time.

9 is a block diagram of a decoder circuit 330 of the present invention. As shown in FIG. 9, the decoder circuit 330 is composed of a plurality of reverse gates 81 (INV) and a plurality of reverse gates 82 (NAND). When the decoder circuit 330 is actually implemented, the decoder circuit 330 can be replaced with a first truth table. That is, the decoder circuit 330 has a first truth table built in, the first built-in truth table may be changed as the number of bits thereof increases or decreases, and the input terminal of the first built-in true value It is N-1 bits and the output is 2 ^N-1 bits. 10 is a schematic diagram of a truth table of decoder circuit 330 of the present invention.

The binary code to temperature code conversion circuit 340 is connected to the 2's complement correction circuit 310, and the binary code to temperature code conversion circuit 340 outputs the binary code output signal of the 2's complement correction circuit 310 (B) _C <3:0>) is converted to a temperature code output signal (T<7:0>).

Figure 11 is a block diagram of a binary carry code to temperature code conversion circuit 340 of the present invention. As shown in FIG. 11, the binary code to temperature code conversion circuit 340 is composed of a plurality of inverters 63, a plurality of inverse OR gates (61), and two binary binary code to three bits. The temperature code sub-converter 64 is composed of. Figure 12 is a block diagram of a binary binary code to three bit temperature code subconverter 64 of the present invention.

When the binary code is actually implemented to the temperature code conversion circuit 340, the binary code to temperature code conversion circuit 340 can be replaced with a second truth table. That is, the binary code to temperature code conversion circuit 340 has a second truth table built in, and the second built-in truth table can be changed according to the increase or decrease of the number of bits. The second built-in The input of the true value is N bits, and the output is 2 ^N-1 bits.

The barrel shifter circuit 350 is coupled to the decoder circuit 330 and the binary code to temperature code conversion circuit 340 to generate a first unit capacitance selected to be connected to a common mode reference voltage (V _cm ). Control signal (Q _CM <7:0>).

Figure 13 is a circuit diagram of a barrel shifter circuit 350 of the present invention. As shown in FIG. 13, barrel shifter circuit 350 includes a 2 ^N-1 by 2 ^N-1 field effect transistor (MOSFET) array and output buffer circuit. Only one bit in P<7:0> will be high. When P<1> is high, only the second group of field effect transistors (MOSFETs) will be turned on, and when T<0>, T<1>, and T<2> are high, only Q _CM <1 >, Q _CM <2>, Q _CM <3> is high. The operation principle is familiar to those skilled in the art based on the circuit of the present invention, and will not be described again.

The back end generates a logic circuit 360 for controlling the unit capacitance signal to be connected to the barrel shifter circuit 350 to generate a unit capacitance connected to a positive reference voltage (+V _ref ) and a negative reference voltage (-V _ref ). Two control signals (Q _P <7:0>) and third control signals (Q _N <7:0>).

The back end generates a logic circuit 360 for controlling the unit capacitance signal to reverse the control signal (Q _CM <7:0>) of the unit capacitance outputted by the barrel shifter 350 and the highest input signal of the N bit. The bit is NAND operated through the NAND gate to generate the second control signal (Q _P <7:0>) representing a unit capacitance selected to be connected to the positive reference voltage (+V _ref ). The logic circuit 360 for generating the control unit capacitance signal at the back end reverses the control signal (Q _CM <7:0>) of the unit capacitance outputted by the barrel shifter and is opposite to the N-bit input signal. The highest bit, the NAND operation is performed through the NAND gate to generate the third control signal (Q _N <7:0>) representing the unit capacitance selected to be connected to the negative reference voltage (-V _ref ).

Figure 14 is a circuit diagram of a logic circuit 360 that produces a control unit capacitance signal at the rear end of the present invention. As shown in FIG. 14, the highest bit of the second control signal (Q _P <7>) is the highest bit of the control signal (Q _CM <7>), and the highest bit of the N-bit input signal Yuan (B<3>), generated by NAND operation through NAND gate. The highest bit of the third control signal (Q _N <7>) is the reverse bit of the N-bit input signal after the highest bit of the control signal (Q _CM <7>) is inverted (!B <3>), generated by an AND operation through the AND gate.

The 2's complement correction circuit 310, the indicator generator circuit 320, the decoder circuit 330, the binary code to temperature code conversion circuit 340, the barrel shifter circuit 350, and the back end generate a control unit capacitance signal The logic circuit 360 is implemented in a circuit or as an integrated circuit (IC).

FIG. 15 is a schematic diagram showing the operation of the data weighted average algorithm system for improving the linearity of the digital analog conversion circuit using the capacitance combining switching technique of the present invention. As shown in Figure 15, an indicator (P) refers to the capacitance C ₀ . When the 4-bit binary code input signal (B<3:0>) is 0010b (remark: B means binary), the selection capacitors C ₀ and C _{1 are} connected to the common mode reference voltage (V _cm ). The remaining capacitors C ₂ -C _{7 are} connected to the negative reference voltage (-V _ref or V _rfn ).

This indicator (P) refers to the capacitance C ₂ . When the 4-bit binary code input signal (B<3:0>) is 1001b, the selection capacitors C ₂ to C7 and C _{0 are} connected to the common mode reference voltage (V _cm ), and the remaining capacitor C _{1 is} connected to the Positive reference voltage (+V _ref or V _rfp ). The operation principle of the present invention is understood by those skilled in the art based on the disclosure of the present invention and will not be described again.

FIG. 16 is a schematic diagram of a signal to noise-and-distortion ratio (SNDR) simulation of the prior art. 17 is a schematic diagram showing the simulation of the signal noise distortion ratio (SNDR) of the present invention. In circuit simulation, eight capacitive components in a digital analog converter (DAC) circuit use a random number to give an error of 1% of the capacitance of each unit capacitive component to simulate the actual CMOS. The error value that can occur on the process.

Comparing Fig. 16 and Fig. 17, it can be clearly seen from the circuit simulation results that the highest harmonic on the output spectrum of the whole system has been effectively reduced, and the noise floor is also greatly reduced. On the signal-to-noise distortion ratio (SNDR) of the system, it is increased from 63.77 dB which is not added to the inventive technique to 77.31 dB after the addition of the present invention. That is equivalent to the effective number of bits (ENOB), which is not added to the invention. The 10.3 bit of the technique was upgraded to 12.55 bits after the addition of the present invention. It can be seen from the simulation results that it has a very significant contribution to the improvement of the resolution of the triangular integrator.

As shown in Figure 2, it can be found that the reference voltage to which all the unit capacitors are connected can only be two at most in each case, or: if it is selected to be connected to the common mode reference voltage (V _cm ) For the reference, when each voltage analog converter (DAC) circuit is voltage-converted, a data weighted average algorithm can be designed to be applied to the digital analog converter (DAC) circuit of the capacitor combining technology. The newly proposed data weighted average algorithm can also be used in turn around all capacitive elements connected to the common mode reference voltage (V _cm ).

As can be seen from the above description, the present invention selectively uses a unit capacitance connected to a common mode reference voltage (Vcm) in a digital analog converter for the purpose of improving the linearity of the digital analog converter. In addition to being able to use a capacitance combining technique in a digital analog converter (DAC) circuit in a delta-sigma modulator, the capacitance value of each unit capacitive component is directly increased to directly reduce the error ratio in the process, and The data weighted average algorithm system for improving the linearity of the digital analog conversion circuit using the capacitance combining switching technique proposed by the present invention further reduces the harmonic distortion caused by the mismatch between capacitors to improve the triangular integral modulator Resolution.

The object of the present invention is to provide a data weighted average algorithm system for improving the linearity of a digital analog conversion circuit using a capacitance combining switching technique to improve a digital analog converter (DAC) circuit of a capacitance combining technique. The linearity can directly and effectively improve the harmonic distortion caused by the mismatch between the unit capacitances in the digital analog converter (DAC), and can greatly reduce the weighted average algorithm of this data on the hardware implementation. Required area, implementation cost and power consumption.

It can be seen from the foregoing circuit that the data weighted average algorithm system for improving the linearity of the digital analog conversion circuit using the capacitance combining switching technique has the main operation concept: when the digital output of the triangular integral modulator is 4 bits, because The digital analog converter (DAC) circuit on the feedback path in this delta-sigma modulator uses capacitor combining techniques, so it also represents the total number of unit capacitors in this digital analog converter (DAC) circuit from the original 16 units. The capacitance is reduced to 8 unit capacitors. Therefore, when a digital output code is subjected to a data weighted average algorithm system for improving the linearity of a digital analog conversion circuit using a capacitance combining switching technique according to the present invention, (1) when the first group digital code output is 2 (0010b) When the digital analog converter (DAC) selects the unit capacitance component numbered C ₀ ~ C ₁ ; (2) when the second group digital code output is 9 (1001b), the digital analog converter (DAC) Then select the unit capacitive component numbered C ₂ ~ C ₇ in order, and add the unit to continue to select the unit capacitance component numbered C ₀ ; (3) when the third group digital code output is 13 (1101b) At the time, the digital analog converter (DAC) selects the unit capacitive components numbered C ₁ ~ C ₃ sequentially; (4) when the fourth group digital code output is 5 (0101b), the digital analog converter ( DAC) selects the unit capacitance component numbered C ₄ ~ C ₇ , and adds the heavy head to continue selecting the unit capacitance component numbered C ₀ .

According to the above operation mode, it can be found that the data weighted average algorithm system for improving the linearity of the digital analog conversion circuit using the capacitance combining switching technique of the present invention selects the unit capacitance element every time bit analog converter (DAC). It is possible to avoid reusing the last selected capacitive element, so that after the digital analog converter (DAC) circuit is running for a certain period of time, each unit capacitive element in the circuit can be in this period of time. The highest average usage rate is achieved, and the problem of harmonic distortion due to mismatch between capacitors is achieved.

18 is a schematic diagram of a comparison of the present invention with the prior art. As shown in FIG. 18, the barrel shifter circuit 350 of the present invention is a 16 by 16 field effect transistor (MOSFET) array required by the prior art. The size is effectively reduced to an 8 by 8 field effect transistor (MOSFET) array size. In this way, in addition to reducing the complexity of the circuit implementation, the area can be effectively reduced to achieve the purpose of reducing the manufacturing cost of the integrated circuit. At the same time, the indicator generator circuit 320, the decoder circuit 330, and the binary code to temperature code conversion circuit 340 can be reduced to 3-bit by the conventional 4-bit, thereby reducing circuit cost and power consumption.

The present invention can directly and effectively improve the unit capacitance of a digital analog converter by comparing a data weighted average algorithm system for linearity of a digital analog conversion circuit using a capacitance combining switching technique with a conventional data weighted average algorithm. The harmonic distortion generated by the mismatch between each other can greatly reduce the area, implementation cost and power consumption required for the weighted averaging circuit of this data.

From the above, it can be seen that the present invention is extremely useful in terms of its purpose, means, and efficacy, both of which are different from those of the prior art. It should be noted that the various embodiments described above are merely illustrative for ease of explanation, and the scope of the invention is intended to be limited by the scope of the claims.

300‧‧‧Data weighted average algorithm system for linearity of digital analog conversion circuit for improving capacitance combining switching technology

310‧‧‧2 complement correction circuit

320‧‧‧ indicator generator circuit

330‧‧‧Decoder circuit

350‧‧‧ barrel shifter circuit

340‧‧‧ binary code to temperature code conversion circuit

360‧‧‧The back end generates the logic circuit that controls the unit capacitance signal

Step (A) ~ Step (D)

52‧‧‧XOR logic gate

51‧‧‧ Half adder circuit

53‧‧‧Inverter (INV)

54‧‧‧Anti-gate (NAND)

610‧‧‧Full adder

620‧‧‧D type flip-flop

73‧‧‧Inverter (INV)

81‧‧‧Inverter (INV)

82‧‧‧Anti-gate (NAND)

63‧‧‧Inverter (INV)

61‧‧‧Anti-or gate (NOR)

62‧‧‧Anti-gate (NAND)

64‧‧‧2-digit binary code to three-digit temperature code converter

91‧‧‧Inverter (INV)

101, 102‧‧‧Anti-gate (NAND)

Fig. 1(A) and Fig. 1(B) are schematic diagrams showing the combination of conventional techniques.

FIG. 2 is a comparison comparison table between a digital bit analog converter (DAC) circuit using a capacitor combining technique and a digital analog code converter (DAC) circuit and a corresponding analog voltage.

3 is a block diagram of a data weighted average algorithm system for linearity of a digital analog conversion circuit of the improved capacitance combining switching technique of the present invention.

Figure 4 is a flow chart showing the operation of the complement correction circuit of the second embodiment of the present invention.

5(A) and 5(B) are block diagrams showing a complement correction circuit of the second aspect of the present invention.

Figure 6 is a block diagram of the indicator generator circuit of the present invention.

Figure 7 is a circuit diagram of the full adder of the present invention.

Figure 8 is a circuit diagram of a D-type flip-flop of the present invention.

Figure 9 is a block diagram of a decoder circuit of the present invention.

Figure 10 is a schematic illustration of the truth table of the decoder circuit of the present invention.

Figure 11 is a block diagram of a binary carry code to temperature code conversion circuit of the present invention.

Figure 12 is a block diagram of a binary binary code to a three bit temperature code subconverter of the present invention.

Figure 13 is a circuit diagram of a barrel shifter circuit of the present invention.

Figure 14 is a circuit diagram showing the logic circuit for generating a unit capacitance signal at the rear end of the present invention.

FIG. 15 is a schematic diagram showing the operation of the data weighted average algorithm system for improving the linearity of the digital analog conversion circuit using the capacitance combining switching technique of the present invention.

Figure 16 is a schematic diagram showing the simulation of the signal-to-noise distortion ratio of the prior art.

Figure 17 is a schematic diagram showing the simulation of the signal noise distortion ratio of the present invention.

Figure 18 is a schematic illustration of a comparison of the present invention with prior art techniques.

300‧‧‧Data weighted average algorithm system for linearity of digital analog conversion circuit for improving capacitance combining switching technology

310‧‧‧2 complement correction circuit

320‧‧‧ indicator generator circuit

330‧‧‧Decoder circuit

350‧‧‧ barrel shifter circuit

340‧‧‧ binary code to temperature code conversion circuit

360‧‧‧The back end generates the logic circuit that controls the unit capacitance signal

Claims (10)

A data weighted average algorithm system for improving the linearity of a digital analog conversion circuit using a capacitance combining switching technique for setting a configuration of a plurality of unit capacitors connected to a common mode reference voltage, the data weighted average algorithm system comprising: a 2's complement correction circuit, which receives an N-bit binary code input signal, and the 2's complement correction circuit corrects a partial binary code input signal of the N-bit binary code input signal to correctly generate a representative a binary code signal connected to a plurality of unit capacitances of the common mode reference voltage; an indicator generator circuit connected to the 2's complement correction circuit, according to the binary code signal, to update to point to the next start selection The start address of the plurality of unit capacitors is a binary code signal; a decoder circuit is connected to the indicator generator circuit for converting the start address binary code signal outputted by the indicator generator circuit into 2 ^{N -1} bit respectively points to the index signal of the majority of the unit capacitance, to control the barrel shifter circuit to point to the first unit capacitance selected next time; a binary code to temperature code conversion circuit is connected to the 2's complement correction circuit, and the binary code to temperature code conversion circuit converts the binary code output signal outputted by the 2's complement correction circuit into a temperature code output a barrel shifter circuit coupled to the decoder circuit and the binary code to the temperature code conversion circuit to generate a first control signal for selecting a unit capacitance connected to the common mode reference voltage; and a back end generation A logic circuit for controlling the unit capacitance signal is coupled to the barrel shifter circuit to generate second and third control signals connected to a unit capacitor of a positive reference voltage and a negative reference voltage. The data weighted average algorithm system according to claim 1, wherein the 2's complement correction circuit determines the highest bit of the N-bit input signal, and if the highest bit is 1, the N bit is The meta-input signal is converted into its 2's complement. If the highest bit is 0, no change is made to the N-bit input signal. The data weighted average algorithm system of claim 2, wherein the 2's complement correction circuit comprises a plurality of XOR logic gate and half adder circuits. The data weighted average algorithm system of claim 3, wherein the indicator generator circuit adds each input signal to the last indicator signal to generate the updated start bit. Address signal. The data weighted average algorithm system of claim 4, wherein the decoder circuit has a first truth table built in, the first built-in truth table may increase or decrease with the number of bits thereof. With some changes, the input of the first built-in true value is N-1 bit, and the output end is 2 ^N-1 bit. The data weighted average algorithm system according to claim 5, wherein the binary code to temperature code conversion circuit has a second truth table built in, and the second built-in truth table can follow its bit The increment of the number of elements varies, the input of the second built-in true value is N bits, and the output is 2 ^N-1 bits. For example, the data weighted average algorithm system described in claim 6 wherein the barrel shifter circuit architecture comprises a 2 ^N-1 by 2 ^N-1 field effect transistor array and an output buffer circuit. The data weighted average algorithm system of claim 7, wherein the back end generates a logic circuit for controlling the unit capacitance signal, and the control signal of the unit capacitance outputted by the barrel shifter is reversed The highest bit of the N-bit input signal is NANDed through the NAND gate to generate the second control signal representative of the unit capacitance selected to be connected to the positive reference voltage. The data weighted average algorithm system of claim 8, wherein the back end generates a logic circuit for controlling the unit capacitance signal, and the control signal of the unit capacitance outputted by the barrel shifter is reversed The reverse highest bit of the N-bit input signal is ANDed by an AND gate to generate the third control signal representing a unit capacitance selected to be connected to the negative reference voltage. The data weighted average algorithm system according to claim 9, wherein the 2's complement correction circuit, the indicator generator circuit, the decoder circuit, the binary code to temperature code conversion circuit, and the barrel The shifter circuit, the logic circuit for generating the control unit capacitance signal at the back end is realized by a circuit or as an integrated circuit.