TWI493330B - Power control apparatus and power control system - Google Patents
Power control apparatus and power control system Download PDFInfo
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Description
本發明係關於電源控制裝置,更係關於操作於複數個電壓模式下之電源控制裝置。The present invention relates to a power control device, and more particularly to a power control device operating in a plurality of voltage modes.
隨著半導體製程進入次微米時代,各種電子裝置為了達到減低耗電的目的,通常將其工作電壓予以降低。如此一來,該電子裝置所接收的電源供應電壓往往相異並遠高於本身所需之工作電壓。此時,一般的作法是在該電源與該電子裝置之間配置一穩壓器(voltage regulator)或一直流對直流轉換器(DC-to-DC converter)等裝置以協調電源與電子裝置間相異的電壓。As semiconductor processes enter the sub-micron era, various electronic devices typically reduce their operating voltage in order to reduce power consumption. As a result, the power supply voltage received by the electronic device tends to be different and much higher than the operating voltage required by itself. At this time, it is common practice to arrange a voltage regulator or a DC-to-DC converter between the power source and the electronic device to coordinate the phase between the power source and the electronic device. Different voltage.
第1圖為先前技術之一低壓差(Low Dropout)線性穩壓器的示意圖。低壓差線性穩壓器(簡稱LDO)為穩壓器的一種,如第1圖所示,LDO 100用以自電源(圖未示)接收一輸入電壓Vin ,並將一輸出電壓Vout 供應至電子裝置(圖未示)。其中,取樣電路110由電阻R1 及R2 所組成,用以自輸出電壓Vout 取得一取樣電壓Vsp ,並將該取樣電壓Vsp 回饋至比較放大器120與一參考電壓VREF 進行比較,兩者的差值經比較放大器120放大後,控制功率放大器130的壓降,從而穩定輸出電壓Vout 。Figure 1 is a schematic diagram of a low dropout linear regulator of the prior art. The low dropout linear regulator (LDO) is a type of voltage regulator. As shown in FIG. 1, the LDO 100 is configured to receive an input voltage V in from a power source (not shown) and supply an output voltage V out . To the electronic device (not shown). The sampling circuit 110 is composed of resistors R 1 and R 2 for obtaining a sampling voltage V sp from the output voltage V out , and feeding the sampling voltage V sp to the comparison amplifier 120 for comparison with a reference voltage V REF . after the difference between the two comparison amplifier 120 amplifies the control voltage drop of the power amplifier 130, thereby stabilizing the output voltage V out.
值得注意的是,某些電子產品不只以一固定電源操作,而是切換於多種電源模式之間,其間之電力變化可能相當大。以電腦主機為例,其常見的電源模式包括:工作 模式與省電模式(甚至更細分為休眠模式及睡眠模式)。第2圖為電腦主機切換於不同電源模式之示意圖。當指令IN1 啟動高壓電源放大器21時,電腦主機以較高電流(舉例而言,100mA)操作於工作模式下;而當指令IN2 啟動低壓電源放大器22時,電腦主機則改以較低電流(舉例而言,0.1μA)操作於省電模式下以節省電能。兩模式間常具有不同之工作電流,以上述LDO 100而言,當輸出負載產生劇烈變化時,由於包括功率放大器130在內之輸出控制元件切換速度不及,使得輸出電壓Vout 出現巨大之壓差,此易使LDO 100損毀進而導致主機發生異常。解決此問題雖然可採用傳統的作法,在LDO 100之輸出端上配置一大電容來降低此效應,然而,並非所有電子產品皆允許在IC外配置大電容,若將此大電容內建於IC上亦會使製造成本大幅提高。It is worth noting that some electronic products are not only operated with a fixed power supply, but switch between multiple power modes, and the power variation between them may be quite large. Taking a computer host as an example, its common power modes include: working mode and power saving mode (even subdivided into sleep mode and sleep mode). Figure 2 is a schematic diagram of the computer host switching to different power modes. When the command IN 1 starts the high voltage power amplifier 21, the host computer operates at a higher current (for example, 100 mA) in the operating mode; and when the command IN 2 starts the low voltage power amplifier 22, the host computer changes to a lower current. (For example, 0.1 μA) operates in a power saving mode to save power. Between the two modes having different constant current, LDO 100 as described above, when the output load changes violently, due to the power amplifier 130 including output control element, including its switching speed less, so that the output voltage V out of a huge pressure difference This will cause the LDO 100 to be damaged and cause an abnormality in the host. To solve this problem, although a conventional method can be used, a large capacitor is placed at the output of the LDO 100 to reduce this effect. However, not all electronic products allow a large capacitor to be disposed outside the IC. If this large capacitor is built in the IC It will also increase the manufacturing costs.
本發明提供一種電源控制裝置,用以控制一主機自一省電模式安全進入一工作模式,其中該主機在該省電模式即將進入該工作模式之際發出一電源切換訊號。該電源控制裝置包括一穩壓器及一控制負載。其中該穩壓器用以接收一輸入電壓,並以一輸出端用以提供一輸出電壓至該主機;而該控制負載用以當接收該電源切換訊號時,自該穩壓器之該輸出端汲取一電流,並在一既定時間後送出一啟動訊號至該主機以通知該主機進入該工作模式。The present invention provides a power control device for controlling a host to safely enter a working mode from a power saving mode, wherein the host issues a power switching signal when the power saving mode is about to enter the working mode. The power control device includes a voltage regulator and a control load. The voltage regulator is configured to receive an input voltage, and an output terminal is used to provide an output voltage to the host; and the control load is used to receive the power switching signal from the output terminal of the voltage regulator. A current, and after a predetermined time, sends a start signal to the host to notify the host to enter the working mode.
本發明另提供一種系統,可自一省電模式安全進入一 工作模式。該系統包括一主機、一穩壓器、一控制電路以及一虛擬負載。其中該主機在該省電模式即將進入該工作模式之際發出一電源切換訊號;該穩壓器用以接收一輸入電壓,並以一輸出端提供一輸出電壓至該主機;該控制電路,用以當接收該電源切換訊號時發出一控制訊號,並在一既定時間後送出該啟動訊號至該主機以通知該主機進入該工作模式;而該虛擬負載,耦接於該控制電路與該穩壓器之間,用以接收該控制訊號之控制而在該既定時間內使該穩壓器輸出之該電流提升至一定值The invention further provides a system, which can safely enter one from a power saving mode Operating mode. The system includes a host, a voltage regulator, a control circuit, and a virtual load. The host sends a power switching signal when the power saving mode is about to enter the working mode; the voltage regulator is configured to receive an input voltage, and provide an output voltage to the host by an output terminal; the control circuit is configured to: Sending a control signal when receiving the power switching signal, and sending the startup signal to the host after a predetermined time to notify the host to enter the working mode; and the virtual load is coupled to the control circuit and the voltage regulator Between the control for receiving the control signal, the current outputted by the voltage regulator is raised to a certain value within the predetermined time.
為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉數較佳實施例,並配合所附圖示,作詳細說明如下。The above and other objects, features, and advantages of the present invention will become more apparent and understood by the appended claims appended claims
第3圖為依據本發明一實施例之電源控制裝置示意圖。主機320可切換於一省電模式(在此實施例中為低電流模式)與一工作模式(在此實施例中為正常電流模式)之間。熟悉本技藝人士可知,電腦主機在切換電源模式之際會發出訊號通知其周邊裝置。在本實施例中,當該主機320在該省電模式即將進入該工作模式時,會對本發明之電源控制裝置發出一電源切換訊號Power_up,而本發明之電源控制裝置310之目的即在於:當該主機320由省電模式返回工作模式而電流劇增時仍能穩定地提供電源至該主機320。Figure 3 is a schematic diagram of a power supply control device in accordance with an embodiment of the present invention. The host 320 can switch between a power saving mode (in this embodiment, a low current mode) and an operating mode (in this embodiment, a normal current mode). Those skilled in the art will appreciate that the host computer will signal the peripheral device when switching the power mode. In this embodiment, when the host 320 is about to enter the working mode in the power saving mode, a power switching signal Power_up is issued to the power control device of the present invention, and the purpose of the power control device 310 of the present invention is: The host 320 returns to the operating mode from the power saving mode and can stably supply power to the host 320 when the current is suddenly increased.
本發明之電源控制裝置310至少包括一穩壓器330及一控制負載340。舉例而言,該穩壓器330在此實施例中 為一低壓差(Low Dropout)線性穩壓器330(簡稱LDO 330),然而在其他實施例中可以直流對直流轉換器(DC-to-DC converter)等其他穩壓器替代,熟悉本技藝人士不必以此為限。其中,LDO 330用以自一電壓源(圖未示)接收一輸入電壓Vin ,並以一輸出端A將一輸出電壓Vout 提供至主機320。該控制負載340耦接該LDO 330之輸出端A及該主機320,其中,當該控制負載340接收到主機320所發出之電源切換訊號Power_up時,會自該LDO 330之輸出端A汲取一電流,而LDO 330之輸出電流IVO 會因此逐步提升。此外,控制負載340又會在一既定時間後送出一啟動訊號LDO_ready至該主機320以通知該主機320可以安全地進入該工作模式。舉例而言,若該主機320為一數位裝置,則主機320可藉由開啟一時脈產生器(Clock Generator)之方式來啟動其工作模式。藉由本發明該既定時間的延遲作用,使得主機320不致於猛然自該省電模式切換至該工作模式,此將避免使LDO 330遭受瞬時壓差而損毀,進而影響主機320之穩定性。The power control device 310 of the present invention includes at least a voltage regulator 330 and a control load 340. For example, the regulator 330 is a low dropout linear regulator 330 (LDO 330 for short) in this embodiment, but in other embodiments a DC to DC converter (DC-to-) Other regulators such as DC converters are not to be limited by those skilled in the art. The LDO 330 is configured to receive an input voltage V in from a voltage source (not shown) and provide an output voltage V out to the host 320 at an output terminal A. The control load 340 is coupled to the output terminal A of the LDO 330 and the host 320. When the control load 340 receives the power switching signal Power_up from the host 320, a current is drawn from the output terminal A of the LDO 330. And the output current I VO of the LDO 330 will gradually increase. In addition, the control load 340 sends a start signal LDO_ready to the host 320 after a predetermined time to notify the host 320 that the operating mode can be safely entered. For example, if the host 320 is a digital device, the host 320 can initiate its working mode by turning on a clock generator. By the delay of the predetermined time of the present invention, the host 320 is not suddenly switched from the power saving mode to the working mode, which will prevent the LDO 330 from being damaged by the instantaneous voltage difference, thereby affecting the stability of the host 320.
在一較佳的實施例中,本發明之控制負載340更包括一控制電路342及一虛擬負載(Dummy Load)346。該控制電路342耦接至主機320,用以在接收自主機320而來之電源切換訊號Power_up時,發出一控制訊號Crl至該虛擬負載346,並在上述既定時間後送出該啟動訊號LDO_ready至主機320。而該虛擬負載(Dummy Load)346,耦接於該控制電路342與該LDO 330之間,用以接收該控制訊號Crl之控制而在該既定時間內使該LDO 330之輸出電流IVO 提 升至一定值。舉例而言,該虛擬負載346可受該控制訊號Crl之控制而在該既定時間內使得該LDO 330之輸出電流進入其飽和區,則該定值即為該虛擬負載346之飽和電流值。關於虛擬負載346之特性為一習知技術,故在此不再贅述。In a preferred embodiment, the control load 340 of the present invention further includes a control circuit 342 and a dummy load 346. The control circuit 342 is coupled to the host 320 for transmitting a control signal Crl to the virtual load 346 when receiving the power switching signal Power_up from the host 320, and sending the startup signal LDO_ready to the host after the predetermined time. 320. The Dummy Load 346 is coupled between the control circuit 342 and the LDO 330 for receiving the control of the control signal Crl to increase the output current I VO of the LDO 330 to the predetermined time. A certain value. For example, the virtual load 346 can be controlled by the control signal Crl to cause the output current of the LDO 330 to enter its saturation region within the predetermined time. The set value is the saturation current value of the virtual load 346. The characteristics of the virtual load 346 are a conventional technique and will not be described here.
第4圖為依照本發明之電源控制裝置之時序圖。請一併參照上述實施例。從圖中可知,依照本發明,低位準的電源切換訊號Power_up即表示該主機320仍處於該省電模式。主機320在時間t1 時發出一電源切換訊號Power_up(即電源切換訊號Power_up由低位準切換至高位準),此時主機320將不直接進入該工作模式,取而代之的,受到本發明之控制電路342之作用,主機320將在間隔一既定時間td 後始進入該工作模式。而在此既定時間td 之內,該虛擬負載346會自該LDO 330汲取電流而使該LDO 330之輸出電流IVO 由省電模式下之電流值ia 逐步上升,而後,舉例而言,虛擬負載346可在時間t2 時依其本身特性,使得輸出電流IVO 達到一飽和電流值ib 。在該既定時間td 過後,主機320會在時間t3時完全進入工作模式,此時LDO 330在經本發明作用後已達理想狀態而將不致遭受工作模式之高電流破壞。最後,在時間t4 時,該控制電路342可將該虛擬負載346汲取電流之功能予以關閉以節省電能,然而本發明不以此為限。此外,熟悉技藝人士當可依據本發明對既定時間td 之各時段(包括t1 至t2 ,t2 至t3 )作適當之配置。Figure 4 is a timing diagram of a power control device in accordance with the present invention. Please refer to the above embodiment together. As can be seen from the figure, according to the present invention, the low level power switching signal Power_up means that the host 320 is still in the power saving mode. The host 320 sends a power switching signal Power_up at time t 1 (ie, the power switching signal Power_up is switched from the low level to the high level). At this time, the host 320 will not directly enter the working mode, and instead, the control circuit 342 of the present invention is adopted. the role of the host 320 d t after the beginning of entering the operating mode in a predetermined time interval. During the predetermined time t d , the virtual load 346 draws current from the LDO 330 to increase the output current I VO of the LDO 330 from the current value i a in the power saving mode, and then, for example, The virtual load 346 can be such that its output current I VO reaches a saturation current value i b at time t 2 . After the predetermined time t d has elapsed, the host 320 will fully enter the operating mode at time t3, at which time the LDO 330 has reached an ideal state after being acted upon by the present invention and will not be subjected to high current destruction by the operating mode. Finally, at time t 4, the control circuit 342 may be the dummy load 346 draws current control functions be turned off to save power, but the present invention is not limited thereto. Moreover, those skilled in the art can suitably configure each of the time periods (including t 1 to t 2 , t 2 to t 3 ) for a given time t d in accordance with the present invention.
上述實施例整體而言即為一種可自一省電模式安全進入一工作模式的系統300。請參照第3圖,該系統300包 括一主機320、一LDO 330、一控制電路342、及一虛擬負載346。其中該主機320在該省電模式即將進入工作模式之際發出一電源切換訊號Power_up。而該LDO 330用以接收一輸入電壓Vin,並以一輸出端A提供一輸出電壓Vout至該主機320。該控制電路342用以當接收該電源切換訊號Power_up時發出一控制訊號Crl,並在一既定時間td後送出該啟動訊號LDO_ready至該主機320以通知該主機320進入該工作模式。而該虛擬負載346耦接於該控制電路342與該LDO 330之間,用以接收該控制訊號Crl之控制而在該既定時間td 內使該LDO 330之輸出電流IVO 提升至一定值。The above embodiment is generally a system 300 that can safely enter a working mode from a power saving mode. Referring to FIG. 3, the system 300 includes a host 320, an LDO 330, a control circuit 342, and a virtual load 346. The host 320 sends a power switching signal Power_up when the power saving mode is about to enter the working mode. The LDO 330 is configured to receive an input voltage Vin and provide an output voltage Vout to the host 320 at an output terminal A. The control circuit 342 is configured to send a control signal Crl when receiving the power switching signal Power_up, and send the startup signal LDO_ready to the host 320 after a predetermined time td to notify the host 320 to enter the working mode. The virtual load 346 is coupled between the control circuit 342 and the LDO 330 for receiving the control of the control signal Crl to increase the output current I VO of the LDO 330 to a certain value within the predetermined time t d .
在本發明的範圍內,將包含所有修飾及改變,將由下述的申請專利範圍所保護。All modifications and variations are intended to be included within the scope of the invention.
100‧‧‧LDO100‧‧‧LDO
Vin ‧‧‧輸入電壓V in ‧‧‧ input voltage
Vout ‧‧‧輸出電壓V out ‧‧‧output voltage
110‧‧‧取樣電路110‧‧‧Sampling circuit
R1 ‧‧‧電阻R 1 ‧‧‧resistance
R2 ‧‧‧電阻R 2 ‧‧‧resistance
Vsp ‧‧‧取樣電壓V sp ‧‧‧Sampling voltage
120‧‧‧比較放大器120‧‧‧Comparative amplifier
VREF ‧‧‧參考電壓V REF ‧‧‧reference voltage
130‧‧‧功率放大器130‧‧‧Power Amplifier
IN1 ‧‧‧指令IN 1 ‧‧‧ Directive
IN2 ‧‧‧指令IN 2 ‧‧‧ Directive
300‧‧‧系統300‧‧‧ system
310‧‧‧電源控制裝置310‧‧‧Power control unit
320‧‧‧主機320‧‧‧Host
330‧‧‧LDO330‧‧‧LDO
340‧‧‧控制負載340‧‧‧Control load
342‧‧‧控制電路342‧‧‧Control circuit
346‧‧‧虛擬負載346‧‧‧Virtual load
Power_up‧‧‧電源切換訊號Power_up‧‧‧Power Switching Signal
IVO ‧‧‧輸出電流I VO ‧‧‧Output current
LDO_ready‧‧‧啟動訊號LDO_ready‧‧‧ start signal
Crl‧‧‧控制訊號Crl‧‧‧ control signal
ib ‧‧‧飽和電值i b ‧‧‧saturated electricity value
ia ‧‧‧省電模式下之電流值i a ‧‧‧current value in power saving mode
t1 ‧‧‧時間t 1 ‧‧‧ time
t2 ‧‧‧時間t 2 ‧‧‧ time
t3 ‧‧‧時間t 3 ‧‧‧Time
第1圖為先前技術之一低壓差線性穩壓器的示意圖;第2圖為電腦主機切換於不同電源模式之示意圖;第3圖為依據本發明一實施例之電源控制裝置示意圖;第4圖為依照本發明之電源控制裝置之時序圖。1 is a schematic diagram of a low-dropout linear regulator of the prior art; FIG. 2 is a schematic diagram of a computer host switching to different power modes; FIG. 3 is a schematic diagram of a power control device according to an embodiment of the invention; A timing diagram of a power control device in accordance with the present invention.
300‧‧‧系統300‧‧‧ system
310‧‧‧電源控制裝置310‧‧‧Power control unit
320‧‧‧主機320‧‧‧Host
330‧‧‧LDO330‧‧‧LDO
340‧‧‧控制負載340‧‧‧Control load
342‧‧‧控制電路342‧‧‧Control circuit
346‧‧‧虛擬負載346‧‧‧Virtual load
Power_up‧‧‧電源切換訊號Power_up‧‧‧Power Switching Signal
IVO ‧‧‧輸出電流I VO ‧‧‧Output current
LDO_ready‧‧‧啟動訊號LDO_ready‧‧‧ start signal
Crl‧‧‧控制訊號Crl‧‧‧ control signal
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US10551862B2 (en) | 2017-11-09 | 2020-02-04 | Nuvoton Technology Corporation | System on chip with different current setting modes |
Citations (1)
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TW200513011A (en) * | 2003-09-26 | 2005-04-01 | Asustek Comp Inc | Active virtual loading and power supply system |
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2009
- 2009-03-24 TW TW098109471A patent/TWI493330B/en active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200513011A (en) * | 2003-09-26 | 2005-04-01 | Asustek Comp Inc | Active virtual loading and power supply system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US10551862B2 (en) | 2017-11-09 | 2020-02-04 | Nuvoton Technology Corporation | System on chip with different current setting modes |
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