TWI493330B - Power control apparatus and power control system - Google Patents

Description

Power control device and power control system

The present invention relates to a power control device, and more particularly to a power control device operating in a plurality of voltage modes.

As semiconductor processes enter the sub-micron era, various electronic devices typically reduce their operating voltage in order to reduce power consumption. As a result, the power supply voltage received by the electronic device tends to be different and much higher than the operating voltage required by itself. At this time, it is common practice to arrange a voltage regulator or a DC-to-DC converter between the power source and the electronic device to coordinate the phase between the power source and the electronic device. Different voltage.

Figure 1 is a schematic diagram of a low dropout linear regulator of the prior art. The low dropout linear regulator (LDO) is a type of voltage regulator. As shown in FIG. 1, the LDO 100 is configured to receive an input voltage V _in from a power source (not shown) and supply an output voltage V _{out .} To the electronic device (not shown). The sampling circuit 110 is composed of resistors R ₁ and R ₂ for obtaining a sampling voltage V _sp from the output voltage V _out , and feeding the sampling voltage V _sp to the comparison amplifier 120 for comparison with a reference voltage V _REF . after the difference between the two comparison amplifier 120 amplifies the control voltage drop of the power amplifier 130, thereby stabilizing the output voltage V _out.

It is worth noting that some electronic products are not only operated with a fixed power supply, but switch between multiple power modes, and the power variation between them may be quite large. Taking a computer host as an example, its common power modes include: working mode and power saving mode (even subdivided into sleep mode and sleep mode). Figure 2 is a schematic diagram of the computer host switching to different power modes. When the command IN ₁ starts the high voltage power amplifier 21, the host computer operates at a higher current (for example, 100 mA) in the operating mode; and when the command IN ₂ starts the low voltage power amplifier 22, the host computer changes to a lower current. (For example, 0.1 μA) operates in a power saving mode to save power. Between the two modes having different constant current, LDO 100 as described above, when the output load changes violently, due to the power amplifier 130 including output control element, including its switching speed less, so that the output voltage V _out of a huge pressure difference This will cause the LDO 100 to be damaged and cause an abnormality in the host. To solve this problem, although a conventional method can be used, a large capacitor is placed at the output of the LDO 100 to reduce this effect. However, not all electronic products allow a large capacitor to be disposed outside the IC. If this large capacitor is built in the IC It will also increase the manufacturing costs.

The present invention provides a power control device for controlling a host to safely enter a working mode from a power saving mode, wherein the host issues a power switching signal when the power saving mode is about to enter the working mode. The power control device includes a voltage regulator and a control load. The voltage regulator is configured to receive an input voltage, and an output terminal is used to provide an output voltage to the host; and the control load is used to receive the power switching signal from the output terminal of the voltage regulator. A current, and after a predetermined time, sends a start signal to the host to notify the host to enter the working mode.

The invention further provides a system, which can safely enter one from a power saving mode Operating mode. The system includes a host, a voltage regulator, a control circuit, and a virtual load. The host sends a power switching signal when the power saving mode is about to enter the working mode; the voltage regulator is configured to receive an input voltage, and provide an output voltage to the host by an output terminal; the control circuit is configured to: Sending a control signal when receiving the power switching signal, and sending the startup signal to the host after a predetermined time to notify the host to enter the working mode; and the virtual load is coupled to the control circuit and the voltage regulator Between the control for receiving the control signal, the current outputted by the voltage regulator is raised to a certain value within the predetermined time.

The above and other objects, features, and advantages of the present invention will become more apparent and understood by the appended claims appended claims

Figure 3 is a schematic diagram of a power supply control device in accordance with an embodiment of the present invention. The host 320 can switch between a power saving mode (in this embodiment, a low current mode) and an operating mode (in this embodiment, a normal current mode). Those skilled in the art will appreciate that the host computer will signal the peripheral device when switching the power mode. In this embodiment, when the host 320 is about to enter the working mode in the power saving mode, a power switching signal Power_up is issued to the power control device of the present invention, and the purpose of the power control device 310 of the present invention is: The host 320 returns to the operating mode from the power saving mode and can stably supply power to the host 320 when the current is suddenly increased.

The power control device 310 of the present invention includes at least a voltage regulator 330 and a control load 340. For example, the regulator 330 is a low dropout linear regulator 330 (LDO 330 for short) in this embodiment, but in other embodiments a DC to DC converter (DC-to-) Other regulators such as DC converters are not to be limited by those skilled in the art. The LDO 330 is configured to receive an input voltage V _in from a voltage source (not shown) and provide an output voltage V _out to the host 320 at an output terminal A. The control load 340 is coupled to the output terminal A of the LDO 330 and the host 320. When the control load 340 receives the power switching signal Power_up from the host 320, a current is drawn from the output terminal A of the LDO 330. And the output current I _{VO of the} LDO 330 will gradually increase. In addition, the control load 340 sends a start signal LDO_ready to the host 320 after a predetermined time to notify the host 320 that the operating mode can be safely entered. For example, if the host 320 is a digital device, the host 320 can initiate its working mode by turning on a clock generator. By the delay of the predetermined time of the present invention, the host 320 is not suddenly switched from the power saving mode to the working mode, which will prevent the LDO 330 from being damaged by the instantaneous voltage difference, thereby affecting the stability of the host 320.

In a preferred embodiment, the control load 340 of the present invention further includes a control circuit 342 and a dummy load 346. The control circuit 342 is coupled to the host 320 for transmitting a control signal Crl to the virtual load 346 when receiving the power switching signal Power_up from the host 320, and sending the startup signal LDO_ready to the host after the predetermined time. 320. The Dummy Load 346 is coupled between the control circuit 342 and the LDO 330 for receiving the control of the control signal Crl to increase the output current I _{VO of} the LDO 330 to the predetermined time. A certain value. For example, the virtual load 346 can be controlled by the control signal Crl to cause the output current of the LDO 330 to enter its saturation region within the predetermined time. The set value is the saturation current value of the virtual load 346. The characteristics of the virtual load 346 are a conventional technique and will not be described here.

Figure 4 is a timing diagram of a power control device in accordance with the present invention. Please refer to the above embodiment together. As can be seen from the figure, according to the present invention, the low level power switching signal Power_up means that the host 320 is still in the power saving mode. The host 320 sends a power switching signal Power_up at time t ₁ (ie, the power switching signal Power_up is switched from the low level to the high level). At this time, the host 320 will not directly enter the working mode, and instead, the control circuit 342 of the present invention is adopted. the role of the host 320 _d t after the beginning of entering the operating mode in a predetermined time interval. During the predetermined time t _d , the virtual load 346 draws current from the LDO 330 to increase the output current I _{VO of} the LDO 330 from the current value i _{a in the} power saving mode, and then, for example, The virtual load 346 can be such that its output current I _VO reaches a saturation current value i _b at time t ₂ . After the predetermined time t _{d has} elapsed, the host 320 will fully enter the operating mode at time t3, at which time the LDO 330 has reached an ideal state after being acted upon by the present invention and will not be subjected to high current destruction by the operating mode. Finally, at time t _4, the control circuit 342 may be the dummy load 346 draws current control functions be turned off to save power, but the present invention is not limited thereto. Moreover, those skilled in the art can suitably configure each of the time periods (including t ₁ to t ₂ , t ₂ to t ₃ ) for a given time t _{d in} accordance with the present invention.

The above embodiment is generally a system 300 that can safely enter a working mode from a power saving mode. Referring to FIG. 3, the system 300 includes a host 320, an LDO 330, a control circuit 342, and a virtual load 346. The host 320 sends a power switching signal Power_up when the power saving mode is about to enter the working mode. The LDO 330 is configured to receive an input voltage Vin and provide an output voltage Vout to the host 320 at an output terminal A. The control circuit 342 is configured to send a control signal Crl when receiving the power switching signal Power_up, and send the startup signal LDO_ready to the host 320 after a predetermined time td to notify the host 320 to enter the working mode. The virtual load 346 is coupled between the control circuit 342 and the LDO 330 for receiving the control of the control signal Crl to increase the output current I _{VO of} the LDO 330 to a certain value within the predetermined time t _d .

All modifications and variations are intended to be included within the scope of the invention.

100‧‧‧LDO

V _in ‧‧‧ input voltage

V _out ‧‧‧output voltage

110‧‧‧Sampling circuit

R ₁ ‧‧‧resistance

R ₂ ‧‧‧resistance

V _sp ‧‧‧Sampling voltage

120‧‧‧Comparative amplifier

V _REF ‧‧‧reference voltage

130‧‧‧Power Amplifier

IN ₁ ‧‧‧ Directive

IN ₂ ‧‧‧ Directive

300‧‧‧ system

310‧‧‧Power control unit

320‧‧‧Host

330‧‧‧LDO

340‧‧‧Control load

342‧‧‧Control circuit

346‧‧‧Virtual load

Power_up‧‧‧Power Switching Signal

I _VO ‧‧‧Output current

LDO_ready‧‧‧ start signal

Crl‧‧‧ control signal

i _b ‧‧‧saturated electricity value

i _a ‧‧‧current value in power saving mode

t ₁ ‧‧‧ time

t ₂ ‧‧‧ time

t ₃ ‧‧‧Time

1 is a schematic diagram of a low-dropout linear regulator of the prior art; FIG. 2 is a schematic diagram of a computer host switching to different power modes; FIG. 3 is a schematic diagram of a power control device according to an embodiment of the invention; A timing diagram of a power control device in accordance with the present invention.

300‧‧‧ system

310‧‧‧Power control unit

320‧‧‧Host

330‧‧‧LDO

340‧‧‧Control load

342‧‧‧Control circuit

346‧‧‧Virtual load

Power_up‧‧‧Power Switching Signal

I _VO ‧‧‧Output current

LDO_ready‧‧‧ start signal

Crl‧‧‧ control signal

Claims (19)

A power control device for controlling a host to safely enter a working mode from a power saving mode, wherein the host sends a power switching signal when the power saving mode is about to enter the working mode, the power control device includes: a voltage converter for receiving an input voltage, and an output terminal for providing an output voltage to the host; and a control load for capturing from the output terminal of the voltage regulator when receiving the power supply switching signal A current, and after a predetermined time, sends a start signal to the host to notify the host to enter the working mode. The power control device of claim 1, wherein the control load further comprises: a control circuit for issuing a control signal when receiving the power switching signal, and sending the start signal after the predetermined time; And a dummy load coupled between the control circuit and the voltage regulator for receiving the control of the control signal to increase the current output by the voltage regulator to a certain value within the predetermined time. . The power control device of claim 2, wherein the setting is higher than a current value required for the host to operate in the power saving mode. The power control device of claim 2, wherein the control circuit causes the virtual load to output the regulator into a saturation region within the predetermined time. The power control device of claim 2, wherein the control circuit turns off the virtual load after the host enters the working mode. The power control device of claim 1, wherein the first current received by the host in the power saving mode is less than a second current received by the host in the operating mode. The power control device of claim 1, wherein the voltage regulator is a DC-to-DC converter. The power control device of claim 1, wherein the voltage regulator is a low dropout linear regulator. The power control device of claim 1, wherein the input voltage is different from the output voltage. The power control device of claim 1, wherein the host enters the working mode by turning on a clock generator. A power control system can safely enter a working mode from a power saving mode, the system includes: a host that sends a power switching signal when the power saving mode is about to enter the working mode; and a power control device, including: a voltage regulator for receiving an input voltage and providing an output voltage to the host by an output terminal; a control circuit for issuing a control signal when receiving the power switching signal, and sending out after a predetermined time The startup signal is sent to the host to notify the host to enter the working mode; and a dummy load is coupled between the control circuit and the voltage regulator for receiving the control of the control signal. The current output from the regulator is raised to a certain value during the time. Such as the power control system described in claim 11 of the patent scope, The value is higher than the current value required for the host to operate in the power saving mode. The power control system of claim 11, wherein the control circuit causes the virtual load to cause the regulator output to enter a saturation region within the predetermined time. The power control system of claim 11, wherein the control circuit turns off the virtual load after the host enters the working mode. The power control system of claim 11, wherein a first current received by the host in the power saving mode is less than a second current received by the host in the operating mode. The power control system of claim 11, wherein the voltage regulator is a DC-to-DC converter. The power control system of claim 11, wherein the voltage regulator is a low dropout linear regulator. The power control system of claim 11, wherein the input voltage is different from the output voltage. The power control system of claim 11, wherein the host enters the working mode by opening a clock generator.