201035740 六、發明說明： 【發明所屬之技術領域】 本發明係關於電源控制裝置，更係關於操作於複數個 電壓模式下之電源控制裝置。 【先前技術】 • 隨著半導體製程進入次微米時代，各種電子裝置為了 - 達到減低耗電的目的’通常將其工作電壓予以降低。如此 0 一來，該電子裝置所接收的電源供應電壓往往相異並遠高 於本身所需之工作電壓。此時，一般的作法是在該電源與 該電子裝置之間配置一穩壓器（voltage regulator)或一直流 對直流轉換器（DC-to-DC converter)等裝置以協調電源與電 子裝置間相異的電壓。 第1圖為先前技術之一低壓差（Low Dropout)線性穩壓 器的示意圖。低壓差線性穩壓器（簡稱LDO)為穩壓器的一 種，如第1圖所示，LD0 100用以自電源（圖未示）接收一 Ο 輸入電壓vin ’並將一輸出電壓ν_供應至電子裝置（圖未 ‘示）。其中’取樣電路110由電阻Rl及r2所組成，用以自 輸出電壓乂_取得一取樣電壓Vsp，並將該取樣電壓Vsp回 饋至比較放大器120與一參考電壓VREF進行比較，兩者的 差值經比較放大器120放大後，控制功率放大器130的壓 降，從而穩定輸出電壓Vout。 值得注意的是，某些電子產品不只以一固定電源操 作，而是切換於多種電源模式之間，其間之電力變化可能 相當大。以電腦主機為例，其常見的電源模式包括：工作 97-〇〇7-NTC/0492A-A41968-TW/Finay 4 201035740 模式與省電模式（甚至更細分為休 圖為電腦主機切換於不同電源模式，睡眠模式）。第2 啟動高壓電源放大器21時，電腦^意圖。當指令叫 言，驗A)操作於工作模式下；交高電流(舉例而 源放大器22時，電腦主機則改以較低 # A)操作於省電模式下以節省電能。1 ° 之工作電流，以上述LD〇1〇〇而言，春j間常具有不同 m，由於包括功率放大器13()在内之輸出控制元件切 換速度不及’使得輸出電壓v_出現巨大之 UX) 100損毁進而導致主機發生 ’此易使 樣用值私：、i —τα 解决此問題雖然可 2用傳統的作法，在LD0刚之輪出端上配置一 降低此效應，然而，並非所有電子產品皆 大電容，若將此大電容内建於1(： 今在1c外配置 高。 建於1C上亦會使製造成本大幅提 【發明内容】 ❹，、树明提供-種電源控制裝置，用以控制—一 ‘ 省電杈式安全進入一工作模式，其中該主 ^ 即將進入該工作模式之際發出一電源气°":電核式 —職置包括一穩壓器及—控制負載。其3二== 收-輸入電壓’並以—輪出端用以提供—輪出電；： 機；而該控制負載用以當接收該電源切換訊號時= 壓器之該輸出端没取-電流，並在一既定時間後 ^ 動訊號至該主機以通知該主機進入該工作模式。 本發明另提供一種系統，可自一省電模式安全 97-007-NTC/0492A-A41 %8-TW/Final/ 201035740 作，式。該系統包括一主機、一一 及—虛擬負載。苴由外士』， °。 徑制電路以 模式之4 該省㈣切將進人該工作 電壓，並二電㈣換訊號；該穩壓11用以接收一輸入 路，用以〜輪出端提供一輸出電壓至該主機；該控制電 n ^㈣電源切換訊號時發出-控制訊號，並在 該工麵出該啟動訊號至該主機以通知該主機進入 哭、工’而該虛擬負載，耦接於該控制電路與該穩壓 Ο 接收該控龍狀控制而在該既定時間内使 該％壓讀出之該電流提升至-定值 日請ίI讓本發明之上述和其他目的、特徵、和優點能更 二、，’"董下文特舉數較佳實施例，並配合所附圖示，作 詳細說明如下。 【實施方式】 第3圖為依據本發明一實施例之電源控制裝置示意 圖。、主機320可切換於一省電模式（在此實施例中為低電流 〇 模式）與一工作模式(在此實施例中為正常電流模式）之間。 •熟&本技藝人士可知，電駐機在切換電_式之際會發 出。fl號通知其周邊裝置。在本實施例中，當該主機32〇在 該省電模式即將進入該工作模式時，會對本發明之電源控 制裝置發出一電源切換訊號p〇wer-Up ’而本發明之電源控 制I置310之目的即在於：當該主機320由省電模式返回 工作模式而電流劇增時仍能穩定地提供電源至該主機32〇。 本發明之電源控制裝置31〇至少包括一穩壓器33〇及 —控制負載340。舉例而言，該穩壓器330 ·在此實施例中 5>7-0〇7-NTC/〇492A-A41968-TWFina!/ 201035740 為一低壓差（Low Dropout)線性穩壓器33〇(簡稱ld〇 330)，然而在其他實施例中可以直流對直流轉換器 (DC-to-DC converter)等其他穩壓器替代，熟悉本技藝人士 不必以此為限。其中，LDO 330用以自一電壓源（圖未示） 接收一輸入電壓Vin，並以一輸出端A將一輸出電壓 • 提供至主機32〇。該控制負載340耦接該LDO 330之輸出 端A及該主機320，其中，當該控制負載34〇接收到主機 320所發出之電源切換訊號power—Up時，會自該ld〇 330 〇 之輸出端A汲取一電流’而LDO 330之輸出電流1抑會 因此逐步提升。此外’控制負載340又會在一既定時間後 送出一啟動訊號LDO_ready至該主機320以通知該主機 320可以安全地進入該工作模式。舉例而言，若該主機32〇 為一數位裝置，則主機320可藉由開啟一時脈產生器（cl〇ck Generator)之方式來啟動其工作模式。藉由本發明該既定時 間的延遲作用，使得主機320不致於猛然自該省電模式切 換至該工作模式，此將避免使LDO 330遭受瞬時壓差而損 ❹ 毁，進而影響主機320之穩定性。 在一較佳的實施例中，本發明之控制負載340更包括 一控制電路342及一虛擬負載(Dummy Load)346。該控制 電路340编接至主機320，用以在接收自主機320而來之 電源切換訊號Power_up時，發出一控制訊號Crl至該虛擬 負載344,並在上述既定時間後送出該啟動訊號LD0_ready 至主機320。而該虛擬負載(Dummy Load)346，轉接於該控 制電路342與該LDO 330之間，用以接收該控制訊號Crl 之控制而在該既定時間内使該LDO 330之輸出電流1¥0提 97-007-NTC/0492A-A41968-TW/Final/ 7 201035740 升至一定值。舉例而言’該虛擬負載346可受該控制訊號 Crl之控制而在該既定時間内使得該ld〇 330之輸出電流 進入其飽和區’則該定值即為該虚擬負載346之飽和電流 值。關於虛擬負載346之特性為一習知技術，故在此不再 贅述。 第4圖為依照本發明之電源控制裝置之時序圖。請一 併參照上述貫施例。從圖中可知，依照本發明，低位準的 電源切換訊號P〇wer_up即表示該主機320仍處於該省電模 〇式。主機320在時間、時發出一電源切換訊號p〇wer_up(即 電源切換訊號P〇wer_up由低位準切換至高位準），此時主 機320將不直接進入該工作模式，取而代之的，受到本發 明之控制該路342之作用，主機32〇將在間隔一既定時間 td後始進入該工作模式。而在此既定時間^之内，該虛擬 負載346會自該LDO 330汲取電流而使該LD〇 33〇之輸出 電流Ivo由省電模式下之電流值ϋ步上升，而後，舉例 而言’虛擬負載346可在時間t2時依其本身特性，使得輸 A電流Iv。办卜飽和電流值ib。在該既定時間td過後， 主機320會在時間t3時完全進入工作模式，此時ld〇33〇 在經本發明作職已達理想狀態而將不致冑受工作模式之 高電流破壞。最後’在時間％時，該控制該路⑷可將該 虛擬負載346 &取電流之功能予以關閉以節省電能，然而 本發明不以此為限。此外，熟悉技藝人士當可依據本發明 對既定時間td之各時段（包括^至“至邮適當之配置。 上述實施例整體而言即為一種可自—省電模式安全進 入-工作模式的系統3ϋ〇α請㈣第3圖，該系統3〇〇包 97-007-NTC/0492A-A41968-TW/Final/ 8 201035740 括一主機320、一 LDO 330、一控制電路342、及一虛擬負 載346。其中該主機320在該省電模式即將進入工作模式 之際發出一電源切換訊號Power_up。而該LD0 330用以接 收一輸入電壓Vin，並以一輸出端A提供一輸出電壓v〇ut 至該主機320。該控制電路342用以當接收該電源切換訊 號Power_up時發出一控制訊號Crl，並在一既定時間记後 送出該啟動訊號LD0_ready至該主機320以通知該主機 320進入§亥工作模式。而該虛擬負載346耗接於該控制電 〇 路342與該LD0 330之間，用以接收該控制訊號Crl之控 制而在該既定時間td内使該LD0 330之輸出電流ιν〇提升 至一定值。 在本發明的範圍内，將包含所有修斜及改變，將由下 述的申請專利範圍所保護。 【圖式簡單說明】 第1圖為先前技術之一低壓差線性穩壓器的示意圖； 第2圖為電腦主機切換於不同電源模式之示意圖；201035740 VI. Description of the Invention: [Technical Field] The present invention relates to a power supply control device, and more particularly to a power supply control device operating in a plurality of voltage modes. [Prior Art] • As semiconductor processes enter the sub-micron era, various electronic devices typically lower their operating voltages for the purpose of reducing power consumption. As a result, the power supply voltage received by the electronic device tends to be different and much higher than the operating voltage required by itself. At this time, it is common practice to arrange a voltage regulator or a DC-to-DC converter between the power source and the electronic device to coordinate the phase between the power source and the electronic device. Different voltage. Figure 1 is a schematic diagram of one of the prior art Low Dropout linear regulators. The low dropout linear regulator (LDO) is a kind of voltage regulator. As shown in Fig. 1, LD0 100 is used to receive an input voltage vin ' from the power supply (not shown) and supply an output voltage ν_. To the electronic device (not shown). The sampling circuit 110 is composed of resistors R1 and r2 for obtaining a sampling voltage Vsp from the output voltage 乂_, and feeding the sampling voltage Vsp to the comparison amplifier 120 for comparison with a reference voltage VREF. After being amplified by the comparison amplifier 120, the voltage drop of the power amplifier 130 is controlled, thereby stabilizing the output voltage Vout. It is worth noting that some electronic products operate not only on a fixed power supply, but also between multiple power modes, and the power variation between them can be quite large. Take the computer host as an example, its common power modes include: work 97-〇〇7-NTC/0492A-A41968-TW/Finay 4 201035740 mode and power saving mode (even more subdivided into Hugh map for the computer host to switch to different power supply Mode, sleep mode). When the second high voltage power amplifier 21 is activated, the computer is intended. When the command is called, the test A) is operated in the working mode; when the high current is applied (for example, when the source amplifier 22 is used, the host computer is changed to the lower #A) to operate in the power saving mode to save power. The operating current of 1 °, in terms of the above LD〇1〇〇, often has different m between springs j, because the switching speed of the output control element including the power amplifier 13() is not as good as 'the output voltage v_ appears huge UX ) 100 damage and then cause the host to occur 'this easy to make the sample value private:, i - τα to solve this problem, although 2 can be used in the traditional practice, the configuration of the LD0 just round out to reduce this effect, however, not all electronic The products are all large capacitors. If this large capacitor is built in 1 (: It is now high in 1c. It will also increase the manufacturing cost when it is built on 1C. [Inventive content] ❹, 树明 provides a kind of power control device, Used to control - a 'power saving 安全 safe to enter a working mode, where the main ^ is about to enter the working mode to issue a power supply ° ° ": electronuclear - the position includes a voltage regulator and - control load The 3 2 == receive-input voltage 'and the - round output is used to provide - the wheel is discharged;: the machine; and the control load is used to receive the power switching signal = the output of the press is not taken - current, and after a given time ^ The host is notified to the host to enter the working mode. The present invention further provides a system capable of operating from a power saving mode security 97-007-NTC/0492A-A41%8-TW/Final/201035740. The system includes A host, one and one - virtual load. 苴 by the foreigner, °. The diameter of the circuit in mode 4 The province (four) cut will enter the working voltage, and the second (four) change signal; the regulator 11 is used to receive An input circuit for providing an output voltage to the host at the round output; the control circuit generates a control signal when the power is switched, and sends the start signal to the host at the work surface to notify the host to enter Cry, work, and the virtual load is coupled to the control circuit and the voltage regulator 接收 receiving the controllable control to increase the current of the % voltage readout to a fixed value within the predetermined time. The above and other objects, features and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A power control device according to an embodiment of the invention is illustrated The host 320 can be switched between a power saving mode (in this embodiment, a low current chirp mode) and an operating mode (in this embodiment, a normal current mode). • Cooked & The electric parking machine will be issued when switching the electric mode. The fl# informs its peripheral device. In this embodiment, when the host computer 32 is about to enter the working mode in the power saving mode, the power control device of the present invention will be A power switching signal p〇wer-Up ' is issued and the purpose of the power control I setting 310 of the present invention is to stably supply power to the host when the host 320 returns to the operating mode by the power saving mode and the current is sharply increased. 32〇. The power control device 31 of the present invention includes at least a voltage regulator 33 and a control load 340. For example, the voltage regulator 330 is in this embodiment 5>7-0〇7-NTC/〇492A-A41968-TWFina!/ 201035740 is a low dropout linear regulator 33〇 (referred to as Ld 〇 330), however, in other embodiments, other voltage regulators such as a DC-to-DC converter may be substituted, and those skilled in the art are not limited thereto. The LDO 330 is configured to receive an input voltage Vin from a voltage source (not shown) and provide an output voltage to the host 32A at an output terminal A. The control load 340 is coupled to the output terminal A of the LDO 330 and the host 320. When the control load 34 receives the power switching signal power-Up from the host 320, the output from the ld 330 is output. Terminal A draws a current' and the output current 1 of the LDO 330 is gradually increased. In addition, the control load 340 sends a start signal LDO_ready to the host 320 after a predetermined time to notify the host 320 that the operating mode can be safely entered. For example, if the host 32 is a digital device, the host 320 can initiate its operating mode by turning on a cl〇ck generator. By the delay of the timing of the present invention, the host 320 does not suddenly switch from the power saving mode to the working mode, which will prevent the LDO 330 from being damaged by the instantaneous voltage difference, thereby affecting the stability of the host 320. In a preferred embodiment, the control load 340 of the present invention further includes a control circuit 342 and a dummy load 346. The control circuit 340 is coupled to the host 320 for transmitting a control signal Crl to the virtual load 344 when receiving the power switching signal Power_up from the host 320, and sending the startup signal LD0_ready to the host after the predetermined time. 320. And the Dummy Load 346 is transferred between the control circuit 342 and the LDO 330 for receiving the control of the control signal Crl to increase the output current of the LDO 330 by 1 ¥0 within the predetermined time. 97-007-NTC/0492A-A41968-TW/Final/ 7 201035740 rose to a certain value. For example, the virtual load 346 can be controlled by the control signal Crl to cause the output current of the ld 330 to enter its saturation region within the predetermined time. The set value is the saturation current value of the virtual load 346. The characteristics of the virtual load 346 are a prior art and will not be described here. Figure 4 is a timing diagram of a power control device in accordance with the present invention. Please refer to the above examples. As can be seen from the figure, according to the present invention, the low level power switching signal P〇wer_up indicates that the host 320 is still in the power saving mode. The host 320 sends a power switching signal p〇wer_up (that is, the power switching signal P〇wer_up is switched from the low level to the high level). At this time, the host 320 will not directly enter the working mode, and instead, the present invention is Controlling the role of the path 342, the host 32 will enter the mode of operation after a predetermined time td. Within this predetermined time ^, the virtual load 346 draws current from the LDO 330 so that the output current Ivo of the LD 〇 33 ϋ is stepped up by the current value in the power saving mode, and then, for example, 'virtual The load 346 can be based on its own characteristics at time t2 such that the A current Iv is delivered. Do the saturation current value ib. After the predetermined time td, the host 320 will completely enter the working mode at time t3, at which time ld〇33〇 will not be destroyed by the high current of the working mode after the job has been achieved by the present invention. Finally, at time %, the control circuit (4) can turn off the function of taking the virtual load 346 & to save power, but the invention is not limited thereto. In addition, the skilled person can use the time interval of the predetermined time td according to the present invention (including the configuration to the appropriate postal mail. The above embodiment as a whole is a self-power saving mode safe entry-working mode system) 3ϋ〇αPlease (4) Figure 3, the system 3 pack 97-007-NTC/0492A-A41968-TW/Final/ 8 201035740 includes a host 320, an LDO 330, a control circuit 342, and a virtual load 346 The host 320 sends a power switching signal Power_up when the power saving mode is about to enter the working mode, and the LD0 330 is configured to receive an input voltage Vin and provide an output voltage v〇ut to the output terminal A. The host circuit 320. The control circuit 342 is configured to send a control signal Crl when receiving the power switching signal Power_up, and send the startup signal LD0_ready to the host 320 after a predetermined time to notify the host 320 to enter the operating mode. The virtual load 346 is consumed between the control circuit 342 and the LD0 330 for receiving the control of the control signal Crl to increase the output current ιν〇 of the LD0 330 to the predetermined time td. In the scope of the present invention, all the trimming and changing will be included, and will be protected by the following patent application. [Simplified Schematic] FIG. 1 is a schematic diagram of a low-dropout linear regulator of the prior art. Figure 2 is a schematic diagram of the computer host switching to different power modes;
Q 第3圖為依據本發明一實施例之電源控制裝置示意圖； 第4圖為依照本發明之電源控制裝置之時序圖。 【主要元件符號說明】 100〜LDO ; Vin〜輸入電壓；Vout〜輸出電壓；no〜取樣 電路；R〗〜電阻；R2〜電阻；Vsp〜取樣電壓；12〇〜比較放大 器；Vref〜參考電壓；130〜功率放大器；爪广指令；in2〜指 令；300〜系統；310〜電源控制裝置；320〜主機；330〜LDO ; 340〜控制負載；342〜控制電路；346〜虛擬負載；Power_up〜 97-007-NTC/0492A-A41968-TW/Final/ 9 201035740 電源切換訊號；Ivo〜輸出電流；LDO—ready〜啟動訊號；Crl〜 控制訊號；ib〜飽和電值；ia〜省電模式下之電流值；ti〜時間； 【2〜時間，〖3〜時間。Q is a schematic diagram of a power supply control apparatus according to an embodiment of the present invention; and FIG. 4 is a timing diagram of a power supply control apparatus according to the present invention. [Main component symbol description] 100 ~ LDO; Vin ~ input voltage; Vout ~ output voltage; no ~ sampling circuit; R 〗 〖 resistance; R2 ~ resistance; Vsp ~ sampling voltage; 12 〇 ~ comparison amplifier; Vref ~ reference voltage; 130 ~ power amplifier; claw wide command; in2 ~ command; 300 ~ system; 310 ~ power control device; 320 ~ host; 330 ~ LDO; 340 ~ control load; 342 ~ control circuit; 346 ~ virtual load; Power_up ~ 97- 007-NTC/0492A-A41968-TW/Final/ 9 201035740 power switching signal; Ivo~ output current; LDO_ready~ start signal; Crl~ control signal; ib~saturated value; ia~ current value in power saving mode ;ti~ time; [2~ time, 〖3~ time.
97-007-NTC/0492A-A41968-TW/Final/97-007-NTC/0492A-A41968-TW/Final/