TWI493202B - Chip testing structure, device and method - Google Patents

Description

Wafer test structure, device and method

The present invention relates to a test structure, apparatus and method, and more particularly to a wafer test structure, apparatus and method.

In recent years, due to the improvement of wafer processing technology, the speed of production has been effectively increased, and a large number of wafers have been rapidly manufactured. If there is no test process to screen defective wafers, it will bring great inconvenience to the application surface, accompanied by production. Accelerated and necessary evolutionary test technology has become the most desired task for wafer manufacturers.

Although the wafer production is carried out according to the standard process, everything is mechanized, but the 100% quality of the produced wafers cannot be guaranteed. There must be a certain percentage of defective products. If the defective products flow into the market or are mounted on high-precision instruments. This will cause great inconvenience to the user; therefore, it is necessary to perform quality testing on the produced wafers to screen out defective products; if the speed of the testing process can be effectively improved, the sales speed can be accelerated, and the wafer production can be further enhanced. The speed of the instrument.

The wafer test method is to transfer the electrical signal to the wafer to be tested, and then pass the signal back to the test system, so that the system can recognize the integrity of the signal, thereby judging whether the wafer is good or bad.

However, conventional test systems test only one wafer at a time. If there are multiple wafers to be tested, the test system needs to test the wafers to be tested in sequence, and the wafers cannot be tested at the same time; therefore, it takes a lot of time for the wafers to be tested to be tested. Furthermore, after the wafers are tested, the wafers must be removed from the test system before the next batch of wafers to be tested can be placed in the test system for testing; in other words, the next batch of wafers to be tested cannot be tested. It is placed in the test system for testing in a short time, but it is necessary to wait until the previous batch of wafers are taken out of the test system. In summary, the conventional wafer test system is not efficient in testing multiple or multiple batches of wafers.

In view of the above, it is an urgent problem to be solved in the industry to provide a wafer test structure, apparatus or method which can improve the above-mentioned defects.

It is an object of the present invention to provide a wafer test structure, apparatus and method that can improve the test efficiency of multiple or multiple batches of wafers.

To achieve the above objective, the wafer test structure disclosed in the present invention comprises a test component, a carrier component and a plurality of wafers. The test component has a first substrate, at least one first electrical connector, and a test module. The test module and the first electrical connector are disposed on the first substrate, and the first electrical connector is electrically connected to the test module. The carrier component has a second substrate, at least one second electrical connector, and a plurality of wafer carriers. The wafer carrier and the second electrical connector are disposed on the second substrate, and the second electrical connector is electrically connected. The wafer carriers are detachably disposed on the wafer carrier; the first electrical connector and the second electrical connector are electrically connected to enable the test module to detect the wafer carrier Some wafers.

In order to achieve the above object, a wafer testing apparatus according to the present invention includes: a housing having a first base and a second base, the first base and the second base each having a plurality of tracks. The first pedestal and the second pedestal are side by side; and at least one of the above wafer testing structures, wherein the test component of the wafer testing structure is disposed on one of the tracks of the first pedestal, the bearing The component is disposed on one of the tracks of the second base.

In order to achieve the above objective, the wafer testing method disclosed in the present invention comprises: disposing a plurality of wafers on a plurality of wafer carriers of a carrier member; electrically connecting the carrier components to a test component, such that the test components are a test module electrically connecting the wafer carriers and the wafers; and causing the test module to detect the wafers on the wafer carriers.

The above objects, technical features and advantages will be more apparent from the following description.

The present invention will be explained by the following examples, but the description of the embodiments is merely illustrative of the technical contents of the present invention and the purpose thereof, and is not intended to limit the present invention. It should be noted that in the following embodiments and the drawings, elements that are not directly related to the present invention have been omitted and are not shown; and the number, size, and relative positional relationship of the elements in the drawings are only used for illustration and understanding. Used to limit the number, proportion and size of components implemented.

Please refer to FIG. 1 and FIG. 2, which are respectively a schematic diagram of the wafer test structure and a schematic view of the wafer according to the first embodiment of the present invention. In the first embodiment of the present invention, a wafer test structure 1 is proposed, which comprises: a test component 10, a carrier component 20 and a plurality of wafers 30; the technical contents of each component are described below.

The test component 10 has a first substrate 11 , at least one first electrical connector 12 , and a test module 13 . The first substrate 11 is used to carry other objects (for example, the first electrical connector 12 and the test module 13), and can provide a current transfer medium between the objects, so the first substrate 11 can be a printed circuit board or a metal. A circuit board or the like having similar functions.

At least the first electrical connector 12 is inserted into the second electrical connector 22, which will be described later (or is connected to the connector 40 in the second embodiment shown in FIG. 3), so that the test component 10 is The generated test signal or data can be transmitted to the carrier component 20; the at least one first electrical connector 12 means that the number of the first electrical connectors 12 can be one or more, and in this embodiment, the first electrical connector The number of 12 is exemplified by three.

The test module 13 can provide test signals or data for testing the wafer, and can read and analyze the test signals or data to determine whether the performance of the test wafers is normal or not. The test module 13 can be composed of several electronic components (electronics, capacitors or inductors) and wafers, and different types of wafers are tested by test modules 13 of different functions. The test module 13 and the first electrical connector 12 are both disposed on the first substrate 11 , and the first electrical connector 12 is electrically connected to the test module 13 ; the first electrical connector 12 can also be located at the edge of the first substrate 11 . So as to be plugged into the second electrical connector 22.

The carrier component 20 has a second substrate 21, at least one second electrical connector 22, a plurality of wafer carriers 23, and a handle 24. The second substrate 21 functions like the first substrate 11, and can carry objects (such as the second electrical connector 22 and the wafer carrier 23) and can provide a current transfer medium between the objects.

The at least one second electrical connector 22 is disposed on the second substrate 21 and may be located at an edge of the second substrate 21 so as to be plugged into the first electrical connector 12 (or the second shown in FIG. 3). The connector 40 in the embodiment is plugged in). In addition, the first electrical connector 12 and the second electrical connector 22 are facing each other, and the first electrical connector 12 and the second electrical connector 22 are electrically connected after being inserted into each other. The number and specifications of the second electrical connectors 22 can correspond to the number and specifications of the first electrical connectors 12, respectively. Therefore, the number of the second electrical connectors 22 is also exemplified by three.

The chip carriers 23 are disposed on the second substrate 21 and electrically connected to the second electrical connector 22 . The wafer carrier 23 is used to carry and electrically connect the wafer 30. Therefore, the wafer carrier 23 has a socket or a connection pad for connecting the pins or connection pads of the wafer 30.

The handle 24 can be disposed on the second substrate 21 and the handle 24 is located at the other edge relative to the second electrical connector 22; in other words, the wafer carrier 23 is located between the handle 24 and the second electrical connector 22. The handle 24 facilitates the user to push and pull the carrier member 20 so that the user can conveniently insert the second electrical connector 22 of the carrier member 20 into the first electrical connector 12 of the test component 10, or from the first electrical connector 12. Pulled out.

It should be noted that the handle 24 can be omitted from the carrier member 20 if the carrier member 20 has other components or features that facilitate the user to push and pull it.

The wafers 30 are separately detachably disposed on the wafer carriers 23, that is, the wafers 30 are still detachable from the wafer carrier 23 after being disposed on the wafer carriers 23. The wafers 30 may be the same type or different types of wafers. In this embodiment, the wafers 30 are preferably the same type of wafers, and are all memory chips.

The above is a description of the technical contents of the components of the wafer test structure 1. The wafer test structure 1 can test a plurality of wafers 30 in a shorter time than the conventional test structure (not shown) because the carrier member 20 of the wafer test structure 1 can simultaneously Carrying a plurality of wafers 30 instead of only a single wafer, so that the latter wafer 30 can be disposed in the carrier member 20 without waiting for the previous wafer 30 to be removed from the carrier member 20; and, the test module 13 can be sequentially The plurality of wafers 30 disposed in the carrier member 20 are simultaneously or simultaneously detected; therefore, the time for the wafers 30 to wait for the test can be reduced.

In addition, the wafer test structure 1 can also test a plurality of batches of wafers 30 in a relatively short time because each batch of wafers 30 can be pre-loaded onto different carrier elements 20 when there are multiple batches of wafers 30 to be tested; Next, one of the carrier elements 20 is first electrically connected to the test component 10 such that the wafer 30 on the carrier component 20 (ie, the first batch of wafers) is tested by the test component 10; when the first batch of wafers 30 is tested, The carrier element 20 is separated from the test element 10, and then the next carrier element 20 can be immediately connected to the test element 10; thus, the next batch of wafers 30 can be tested by the test element 10 in a short time without waiting for the previous batch of wafers 30 to be loaded. The element 20 is separated.

Please refer to FIG. 3, which is an overall schematic view of a wafer test structure according to a second embodiment of the present invention. In a second embodiment of the invention, another wafer test structure 2 is proposed which is similar to the wafer test structure 1 except that the first electrical connector 12 of the wafer test structure 1 is directly coupled to the second The second connector 12 of the wafer test structure 2 is separated from the second electrical connector 22, and then the first electrical connector 12 and the second electrical connector 22 are mutually connected through a connector 40. Electrical connection.

In detail, the connecting member 40 can be a component for transmitting signals such as a printed circuit board or a flexible circuit board, and the two sides of the connecting member 40 can have electrical connectors (not shown) so that both sides of the connecting member 40 are provided. The first electrical connector 12 and the second electrical connector 22 can be electrically connected, respectively. The connecting member 40 can increase a distance between the first substrate 11 and the second substrate 21 so that the first substrate 11 and the second substrate 21 can be located in two spaced spaces.

Please refer to FIG. 4, which is a schematic overall view of a wafer testing apparatus according to a third embodiment of the present invention. In a third embodiment, a wafer testing device 3 is proposed. The wafer testing device 3 can include a housing 50 and at least one wafer testing structure.

The housing 50 can have a first base 51 and a second base 52. Referring to FIG. 5, the first base 51 has a plurality of vertically aligned rails 511. The second base 52 also has a plurality of vertically aligned rails 521. The number of the rails 511 and the rails 521 may be The first base 51 and the second base 52 are arranged side by side, and the first base 51 and the second base 52 are spaced apart from each other.

The at least one wafer test structure may be the wafer test structure 1 or 2 described in the first or second embodiment, and the third embodiment is exemplified by the wafer test structure 2. The test component 10 of the wafer test structure 2 may be disposed on one of the tracks 511 of the first pedestal 51, and the carrier component 20 of the wafer test structure 2 may be disposed on one of the tracks 521 of the second pedestal 52. The connector 40 is located between the first base 51 and the second base 52.

The carrier element 20 is preferably slidable on the track 521; the carrier element 20 can be coupled to the test element 10 when sliding toward the test element 10; the carrier element 20 can be separated from the test element 10 when sliding away from the test element 10 And further away from the second base 52.

Referring to FIG. 6, the wafer testing device 3 preferably includes a plurality of wafer testing structures (exemplified by two wafer testing structures, and the remaining wafer testing structures are not shown), and the test components 10 are different at this time. The carrier elements 20 are disposed on one of the tracks 521 of the second base 51; therefore, if the number of the tracks 511 and 521 is larger, the wafer The more wafer test structures the test apparatus 3 can include, such that the wafer test apparatus 3 can simultaneously test more or more batches of wafers 30.

When the number of wafer test structures is increased, only the height of the outer casing 50 is increased, and the width or length of the outer casing 50 is not increased; in other words, the area occupied by the outer casing 50 of the wafer testing device 3, even as the number of wafer test structures is increased. Will not increase in response to the situation.

Referring to FIG. 4, the wafer testing device 3 preferably includes a heater 60 that can be coupled to the housing 50 and that provides thermal energy to the second pedestal 52 such that the second pedestal 52 is The temperature of the wafer (not shown) on the carrier element 20 rises. After the temperature of the wafer rises, the wafer will age so that defects that may exist in the wafer can appear early.

While the heater 60 provides thermal energy into the second pedestal 52, the test component 10 can test the aged wafer to identify the defective wafer. Since "aging of the wafer" and "testing of the wafer" can be performed simultaneously, the overall time taken for both can be shortened.

Continuing to refer to FIG. 4, the outer casing 50 of the wafer testing device 3 preferably further has a partition 53 disposed between the first base 51 and the second base 52 to enable the first base. The seat 51 and the second base 52 are respectively located in the two-phase isolated space. As such, the thermal energy provided by the heater 60 to the second pedestal 52 is less transferred to the first pedestal 51, so that the temperature of the wafer in the second pedestal 52 can rise to a predetermined value relatively quickly, also making the heater The thermal energy of 60 does not affect the operation of test component 10.

Please refer to FIG. 7, which is a flow chart of a wafer testing method according to a fourth embodiment of the present invention. In the fourth embodiment, a wafer test method is proposed, which can be used as the operation method of the wafer test structures 1 and 2 or the wafer test device 3 of the foregoing embodiment, but is not limited thereto.

As shown in step S701, the wafer testing method firstly places a plurality of wafers 30 on the plurality of wafer carriers 23 of the carrier member 20, and the arrangement may be performed by the operator or the robot arm to insert the wafer 30 on the wafer carrier. On the seat 23. Then, as shown in step S703, the carrier component 20 is electrically connected to the test component 10 such that the test module 13 of the test component 10 is electrically connected to the wafer carrier 23 and the wafers 30. Then, as shown in step S705, the test module 13 is caused to start detecting the wafers 30 on the wafer carriers 23.

There are various ways in which the test module 13 detects the wafer 30, which can be determined depending on the type of the wafer 30. In this embodiment, the wafer 30 is a memory chip, so the test module 13 can detect the wafer 30 in the following manner: First, the test module 13 writes test data to the wafers 30 at a time instead of sequentially The chips 30 write test data, thereby saving the overall writing time; then, the test module 13 sequentially reads the test data of the wafers 30 to analyze whether the test data written into the wafer 30 is lost or moved. Therefore, it is judged whether or not the wafer 30 is abnormal.

Simultaneously with the execution of step S705, the wafer testing method optionally performs step S707, that is, the process of detecting the wafers 30 by the test module 13, providing thermal energy to the carrier member 20 such that the temperatures of the wafers 30 are increased. In this way, "aging of the wafer" and "testing of the wafer" can be performed simultaneously, thereby saving the overall time taken for the two steps.

In summary, the wafer test structure, apparatus and method of the present invention can reduce the test time of a plurality of wafers or a plurality of batches of wafers, thereby increasing the test rate. In addition, the wafer test apparatus can occupy only a certain area and then test a plurality of wafers or a plurality of batches of wafers.

The embodiments described above are only intended to illustrate the embodiments of the present invention, and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalents that can be easily made by those skilled in the art are within the scope of the invention. The scope of the invention should be determined by the scope of the claims.

1, 2. . . Wafer test structure

3. . . Wafer test device

10. . . Test component

11. . . First substrate

12. . . First electrical connector

13. . . Test module

20. . . Carrier element

twenty one. . . Second substrate

twenty two. . . Second electrical connector

twenty three. . . Wafer carrier

twenty four. . . handle

30. . . Wafer

40. . . Link

50. . . shell

51. . . First base

511. . . track

52. . . Second base

521. . . track

53. . . Partition

60. . . Heater

Figure 1 is a schematic illustration of a wafer test structure in accordance with a first embodiment of the present invention.

Figure 2 is a schematic diagram of the wafer and wafer carrier of the wafer test structure of Figure 1.

Figure 3 is a schematic illustration of a wafer test structure in accordance with a second embodiment of the present invention.

Figure 4 is a schematic view of a wafer testing apparatus in accordance with a third embodiment of the present invention.

Figure 5 is a schematic view of the susceptor of the wafer testing apparatus of Figure 4.

Figure 6 is a schematic view showing the test structure and the outer casing of the wafer test apparatus of Figure 4.

Figure 7 is a flow chart showing a wafer testing method in accordance with a fourth embodiment of the present invention.

1. . . Wafer test structure

10. . . Test component

11. . . First substrate

12. . . First electrical connector

13. . . Test module

20. . . Carrier element

twenty one. . . Second substrate

twenty two. . . Second electrical connector

twenty three. . . Wafer carrier

twenty four. . . handle

Claims (12)

A wafer test structure includes: a test component having a first substrate, at least one first electrical connector, and a test module, wherein the test module and the at least one first electrical connector are disposed on the first substrate And the at least one first electrical connector is electrically connected to the test module; a carrier component having a second substrate, at least one second electrical connector, and a plurality of wafer carriers, the wafer carrier and the The at least one second electrical connector is disposed on the second substrate, and the at least one second electrical connector is electrically connected to the chip carriers; and the plurality of wafers are separately detachably disposed on the wafer carriers The at least one first electrical connector and the at least one second electrical connector are facing each other such that the test component and the carrier component are detachably connected, and the at least one first electrical connector And electrically connecting the at least one second electrical connector to enable the test module to detect the wafers on the wafer carriers. The wafer test structure of claim 1, wherein the carrier member has a handle, the handle is disposed on the second substrate, and the wafer carrier is located between the handle and the at least one second electrical connector. The wafer test structure of claim 1 further includes a connector, and the two sides of the connector are electrically connected to the first electrical connector and the second electrical connector, respectively. The wafer test structure of claim 1 wherein the first electrical connector directly incorporates the second electrical connector. The wafer test structure of claim 1, wherein the wafers are all wafers of the same type. The wafer test structure of claim 1, wherein the chips are all a memory Wafer. A wafer testing device includes: a housing having a first base and a second base, the first base and the second base each having a plurality of tracks, the first base and the second The susceptor is side-by-side; and at least one of the wafer test structures of any one of claims 1 to 6, wherein the test component of the wafer test structure is disposed on one of the tracks of the first pedestal, The carrier element is disposed on one of the tracks of the second base. The wafer testing device of claim 7, wherein the outer casing further has a partition disposed between the first base and the second base to enable the first base and the second The pedestals are respectively located in two isolated spaces. The wafer testing apparatus of claim 7 further comprising a heater coupled to the outer casing to provide thermal energy to the second pedestal. A wafer testing method includes: disposing a plurality of wafers on a plurality of wafer carriers of a carrier component; electrically connecting the carrier components to a test component, such that a test module of the test component is electrically connected to the a wafer carrier and the wafers; causing the test module to detect the wafers on the wafer carriers; and separating the carrier member from the test component and electrically connecting the other carrier component to the test component, The test element is tested for a plurality of other wafers on the other carrier element. The wafer testing method of claim 10, wherein when the testing module detects the wafers, the testing module writes test data to the wafers at a time, and then The test module sequentially reads the test data of the wafers. The wafer testing method of claim 10, further comprising: providing thermal energy to the carrier component when the test module detects the wafers, such that the temperature of the wafers is increased.