TWI492548B - 二元資料之改錯和偵錯方法 - Google Patents
二元資料之改錯和偵錯方法 Download PDFInfo
- Publication number
- TWI492548B TWI492548B TW098132378A TW98132378A TWI492548B TW I492548 B TWI492548 B TW I492548B TW 098132378 A TW098132378 A TW 098132378A TW 98132378 A TW98132378 A TW 98132378A TW I492548 B TWI492548 B TW I492548B
- Authority
- TW
- Taiwan
- Prior art keywords
- matrix
- vector
- error
- sub
- symbol
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1162—Array based LDPC codes, e.g. array codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/17—Burst error correction, e.g. error trapping, Fire codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/43—Majority logic or threshold decoding
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Quality & Reliability (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Description
本發明係關於光學儲存系統用的改錯碼(ECC)之領域。可應用於磁性記錄儲存裝置、冗贅陣列獨立碟片(RAID)系統,和傳輸系統。
H.Fujita等人在〈在碟片陣列中容許及重碟片故障用之修正低密度MDS陣列碼〉(IEEE trans COMP-56,第563-566頁),展示一種在碟片陣列中容許双重碟片故障用之低密度MDS陣列碼新類別。擬議之MDS陣列碼,其編碼和解碼之複雜性,較Blaum等人的EVENODD碼為低。
可有效編碼的準循環改錯碼,以下稱為「z陣列碼」。z陣列碼係基於已知「陣列碼」,參見R.J.G.Smith所發表〈易解碼之有效自行直交段碼〉(Electronics Letters,第13卷第7期,173-174頁,1977)。z陣列碼以系統性方式,構成LDPC(低密度同位核對)型之ECC碼,一方面即使在大碼字組長度亦可有效解碼,另方面在使用訊文通過式演算解碼時,有優良效能。
z陣列碼之同位核對矩陣,是以下述步驟界定和發生:發生第一中間矩陣H1,包括方形之二橫行、相同尺寸的二元副矩陣,其中第一橫行包括尺寸p×p的p同等矩陣I,第二橫行包括尺寸p×p的循環移動矩陣σ之遞增功率σ u ,其中u=0,...,p-1。從第一中間矩陣H1發生第二中間矩陣H2,係從第一中間矩陣H1的各副矩陣除去m等距直行,在直行指數[r+2ri+i+q]模p,其中i,m,p,q係整數,i=0,...,m-1,而m,p,q,r預先界定,使p=m+2mr,又其中副矩陣內的直行指數,從0開始。以下σ u '指應用此直行除去至相當於σ u 的結果。由於除去步驟從第二中間矩陣H2,發生第三中間矩陣H3,是從第二中間矩陣H2的副矩陣第一橫行刪去只含零的那些矩陣橫行。此項刪除的結果,第三中間矩陣H3的第一橫行包括小
同等矩陣,尺寸(p-m)˙(p-m)。由第三中間矩陣H3發生z陣列碼之同等核對矩陣H,是預計具有權值2的高度2p-m之m-1直行向量,其中直行向量在那些橫行範圍的中間橫行內有"1"元件,其副矩陣[σ0σ1]的並置,具有橫行權值2。較後提到的二元直行向量一起稱為"z"矩陣,即為z陣列碼之名稱。
以下z陣列碼字組之「符號」,是指相當於在直行除去後含有循環移動副矩陣σ u 之一的直行在內之同等核對矩陣H直行的p-m位元元組。再者,「符號x」或「第x符號」係指元組之一,相當於σ(x-1)之直行。須知在此命名中,因其數目,m-1係碼字組之最左位元,相當於同位核對矩陣H之z矩陣部份,一般不視為符號。
z陣列碼勝過陣列碼之優點是:
●因直行係正規性,z陣列碼比直行不正規的陣列碼有更佳的訊文通過解碼效能。
●z陣列碼維持編碼時間,隨碼字組長度直線成長。
●z陣列容許同等位元發生(即編碼),分裂成可調節之獨立依序任務數,使編碼過程得以並式化。
z陣列碼是為有效編碼性和良好訊文通過式解碼效能而設計。惟只有錯誤是由所接收碼字組之位元可靠性低所反映,才能整補訊文通過式解碼。連群錯誤(或抹除以已知位置代表連群錯誤),或散射雜訊事件,則情況不然。以在同樣符號內包括複數敗壞位元之單一符號錯誤而言,訊文通過式解碼輕易找不到正確碼字組,尤其是若錯誤係由短錯誤連群之某些形式所造成。即可為潛在單一符號錯誤進行代數符號錯誤解碼。
單一改錯碼已載於M.Blaum的〈針對碟片陣列中双重碟片故障的復原用寫碼技術〉(1992),另分別參見US Pat.No.5,271,012或EP 0 519 069。此等電碼有至少距離3,故可改正任何單一符號錯誤。
Blaum的解碼方法已載於美國專利5,644,695號。有賴概
括化的陣列碼,如美國專利第5,351,246號所載,也包含美國專利第5,271,012號。
雖然z陣列碼的大部份碼字組具有最小距離3,有些具有最小距離2,故以z陣列寫碼時,並非全部單一符號錯誤均可改正。
關於z陣列寫碼資料之解碼:
●就隨機位元錯誤言,可有益使用訊文通過式解碼;
●至少對z陣列碼之副類,使用處理步驟之修飾,從z陣列編碼可改正單一或双重抹除(碼字組內於已知位置之有誤符號)。此舉開發副類之結構。
●為了短連群錯誤之情形,即當碼字組內未知位置之單一符號,有若干位元敗壞時,迄今缺乏有效解碼(即改正)方法。
從先前技術,即US5,271,012/EP0519669、US5,644,695和US5,351,246之解決方案,涉及不同電碼,並無容許並式化編碼之特點。
本發明提供一種化數單一符號改錯和偵錯方法。「代數解碼」一辭在改錯領域內,已知指一種解碼方法,其正確資料係從某些指定資料「計算」的,相對地,稱為「訊文通過式」的迭代方法,係把指定的有錯資料以非症候群的方式涵蓋入正確資料內。本發明擬議和記載,對z陣列寫碼資料,可有效使用先前技術已知之「多數邏輯解碼」修正方法,於下列任務:●改正碼字組內的單一符號錯誤(在未知位置);●識別碼字組內的複數符號在不能改正的敗壞情況;●識別碼字組內的單一符號在不能改正的(少數)情況。
本發明方法涉及如下步驟:●計算所接收字組之症候群;
●把症候群分裂成二部份;●核對從二症候群部份計算的3整數權值量;●把症候群轉換成與所接收位元相關的「直交位元錯誤權值」之整數向量;●捺跳所接收字組中相關「直交位元錯誤權值」在其可能數值範圍上半之位元。
優點是:
●補助為z陣列寫碼資料先前發明的其他解碼方法。一同使用時,此等解碼技術涵蓋實務上重要的許多(即使不是大多數解碼腳本)。
●此方法用於z陣列寫碼資料時,是US5,644,695號解碼方法之有益替代方式。
本發明解決z陣列碼字組內單一符號錯誤之改正問題。擬議在z陣列碼字組內單一符號之改錯方法。此方法使用延長之多數邏輯解碼過程。此外,複數符號錯誤和不可改正的符號錯誤,可識別和標誌為不可改正。
z陣列碼有最小符號距離dmin=2。所以,視符號內的有錯位元數,不能保證單一符號改錯,因為定符號錯誤位置,並非始終可行。所以,對至少識別全部不能改正的符號錯誤事件採取規約。顯示z陣列碼之上述設計參數"p",可用來降低此等事件之或然率。而且,可以識別大多數的複數符號錯誤。
本發明方法的優點有:
●以單一z陣列碼符號之複數位元已計算而言,本發明延長多數邏輯解碼方法之改錯或然率,遠較軟式決定訊文通過解碼為高。
●較之軟式決定訊文通過式解碼,本發明解碼方法較不複雜,因而所需處理資源較少。因其硬式決定的非迭代性質之故。
●與美國專利5,644,695號相反的是,本發明解碼方法明
白不能改正的符號錯誤事件。對最小符號距離為3的陣列碼而言,全部單一符號錯誤均可改正。z陣列碼勝過陣列碼的優點已在上述指出。
按照本發明,組織成字組的二元資料之改錯和偵錯,包括如下步驟:-從所接收字組r',計算二元症候群向量s;-把症候群向量s分裂成第一副向量s0和第二副向量s1;-從第一副向量s0計算第一錯誤權值ws0,並從第二副向量s1計算第二錯誤權值ws1和第三錯誤權值ws1';-把症候群向量s轉換成直交位元錯誤權值向量eow;-從直交位元錯誤權值向量eow,經由多數決定,衍生多數錯誤向量emaj;-從多數錯誤向量emaj,計算與所接收字組的符號相關之符號錯誤權值向量esym;-從符號錯誤權值向量esym,衍生潛在符號錯誤數nsym;-利用逐一位元XOR運算,以第一副向量s0,改正衍生nsym=1的所接收字組r'。
茲詳述本發明具體例如下。
把指數x=1,...,p的z陣列碼字組之符號,界定為元組,分別包括z陣列碼字組之那些p-m位元,即對同位核對而言,乘以副矩陣ls和σ(x-1)'者;以及z陣列碼之同位核對矩陣H。
z陣列碼在許多情況下,應用延長之多數邏輯解碼策略,得以改正單一符號錯誤。單一符號錯誤界定為,在符號的p-m位元至少1處敗壞。複數符號錯誤不能改正。假設此種錯誤事件,在解碼之前屬於未知。
為單一符號改錯之延長多數邏輯解碼
以下把迄今指明為"H"之z陣列碼的同位核對矩陣,標明為H mz。
■步驟1:在GF2內,從所接收向量(亦稱所接收字組)r',計算症候群。
■步驟2:核對症候群:若保持s=0,所接收向量r'即咸信等於發送之碼字組v;休息。須知對非零的症候群之情況,只能執行下列步驟。
■步驟3:從相當於H mz上部p-m橫行的s之p-m位元,摘取s0。從相當於下半p橫行的s之p位元,摘取s1,使s=[s 0 s 1]。
■步驟4:把s0和s1內的設定位元合計,計算整數值之錯誤權值w s0和w s1:
計算w s1',把s1內的設定位元合計,不管在步驟1內涉及的s1計算之諸元件,以及H mz的z矩陣部份內之"1"元件:
■步驟5:核對錯誤權值相等性:若w s0≠w s1,已偵知非單一符號錯誤;以下列選項休息:選項5a:若w s0=w s1'=0,表示在r'內,只有與H的z矩陣部份關聯之部份有錯,而資訊部份u'和r'之其他同位位元無錯誤。
在此情況,可能重構v par1,但有可能無益。
選項5b:否則,偵知不能改正之複數符號錯誤。
■步驟6:以習知(即非GF2)矩陣乘法,計算直交位元錯誤權值向量e ow:
e ow=sH mz e ow的維度和r'同。因為H mz的直行權值和非GF2乘法,e ow之元件係{0,1,2}。
■步驟7:把直交位元錯誤權值向量e ow的組份,多數解碼成多數錯誤向量e maj,假設最大直交錯誤數為J(直交性是按照Costello Lin在〈錯誤控制寫碼〉內第872頁的第17.6.1節定義)。意即就e ow的各元件1而言,若e ow(n)>[J/2],1被解碼,否則0被解碼。就z陣列碼而言,J=2時,多數錯誤向量即可寫成:
e maj的諸元件是{0,1}。
(步驟6和7是傳統眾所周知的多數邏輯解碼步驟,由此可將r=r'⊕e maj解碼)。
■步驟8:為各符號指數x=1,...,p計算p符號錯誤權值,計數各符號內多數錯誤向量之"1"元件:
此忽略來自e maj相當於H mz的z矩陣部份之z多數錯誤,因為不能界定明晰度之符號。
■步驟9:若e sym (x)=w s0,為各符號核對。錯誤權值w s0是會發生的最大符號錯誤權值。
e ws0(x)=1表示在符號指數x之潛在錯誤。
(此步驟可視為第二符號基礎之多數邏輯解碼步驟,但不能與傳統二步驟多數邏輯解碼器混淆)。
■步驟10:計數潛在符號錯誤數:
■步驟11:核對不能改正的單一或複數符號錯誤。
a.若n sym=0,已偵知複數符號錯誤。
所接收向量r'內之錯誤不能改正;休息!
b.若n sym>1,已偵知單一但不能改正的符號錯誤。
所接收向量r'內之錯誤不能改正;休息!
■步驟12:n sym=1。以s 0將所接收向量r'之有錯符號加以XOR,改正單一符號錯誤,相當於e ws0(x def)=1保持之符號指數x def,以接收r。
須知s 0=e maj((x def-1)(p-m)+z+1:x def(p-m)+z)保持。
(步驟8-12被視為延長步驟)。
本發明延長多數邏輯解碼,按照美國專利5,271,012號亦可應用於Blaum氏陣列碼,供單一符號改錯。於此,步驟5可略去,因為電碼無v par1部份。又,步驟11之選項b內之條件n sym>1從未保持,因為陣列碼未遭到不能改正的單一符號錯誤。
易言之,就代數單一符號改錯和偵錯而言,所擬方法達成:在碼字組內未知位置改正單一符號錯誤,識別碼字組內複數符號係不能改正敗壞之情況,和識別碼字組內單一符號係不能改正敗壞之情況。此方法包括步驟為,計算所接收字組之症候群,把症候群分裂為二部份,核對從二症候群計算之3整數權值量,把症候群轉換成與所接收位元關聯的整數值「直交位元錯誤權值」,並將所關聯「直交位元錯誤權值」在其可能數值範圍上半內的所接收字組之位元加以迭代。
Claims (2)
- 一種二元資料之改錯和偵錯方法,二元資料已經LDPC碼改錯編碼過,其同位核對矩陣等於下列步驟之結果:產生第一中間矩陣,包括二元副矩陣方形之二橫行,尺寸相同,第一橫行包括尺寸p×p之p同等矩陣,而第二橫行包括尺寸p×p的循環移動矩陣之遞增功率;從第一中間矩陣產生第二中間矩陣,係從第一中間矩陣之各副矩陣,在直行指數[r+2ri+i+q]模p除去m等距直行,其中i,m,p,q係整數,i=0,...,m-1,且其中m,p,q,r預先界定,使p=m+2mr,又其中直行指數在副矩陣內以0開始;從第二中間矩陣產生第三中間矩陣,係從第二中間矩陣的副矩陣的第一橫行,刪去僅含零矩陣橫行;於第三中間矩陣預計高度2p-m之m-1二元直行向量,在那些與移動矩陣的第1功率並列的移動矩陣的第0功率具有橫行權值2之橫行範圍,於中間橫行具有"1"元件;二元資料係組織成字組,字組包括符號,此方法具有如下步驟:-從所接收字組和LDPC碼的同位核對矩陣,計算二元症候群向量;-把症候群分裂成第一副向量和第二副向量;-從第一副向量計算第一錯誤重量,從第二副向量計算第二錯誤權值和第三錯誤權值;-把症候群向量轉換成直交位元錯誤權值向量;-從直交位元錯誤權值向量,經由多數決定衍生多數錯誤向量;-從多數錯誤向量計算與所接收字組關聯之符號錯誤權值向量;-從符號錯誤權值向量,衍生潛在符號錯誤數;-對潛在符號錯誤數衍生為1之所接收字組,利用位元逐一XOR運算,以第一副向量加以改正者。
- 如申請專利範圍第1項之方法,其中第一副向量包括症候群之p-m位元,而第二副向量包括p位元,又其中第三錯誤權值係藉計算其在元件2rj+j以外的設定位元,從第二副向量衍生者。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08305690A EP2178215A1 (en) | 2008-10-16 | 2008-10-16 | Method for error correction and error detection of modified array codes |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201018096A TW201018096A (en) | 2010-05-01 |
TWI492548B true TWI492548B (zh) | 2015-07-11 |
Family
ID=40386438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW098132378A TWI492548B (zh) | 2008-10-16 | 2009-09-25 | 二元資料之改錯和偵錯方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8245106B2 (zh) |
EP (2) | EP2178215A1 (zh) |
JP (1) | JP5543170B2 (zh) |
KR (1) | KR101562606B1 (zh) |
CN (1) | CN101729077B (zh) |
TW (1) | TWI492548B (zh) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102325003B (zh) * | 2011-07-14 | 2014-02-12 | 海能达通信股份有限公司 | 数据错误检测的方法及设备 |
DE102014118531B4 (de) * | 2014-12-12 | 2016-08-25 | Infineon Technologies Ag | Verfahren und Datenverarbeitungseinrichtung zum Ermitteln eines Fehlervektors in einem Datenwort |
US10552243B2 (en) | 2017-10-12 | 2020-02-04 | International Business Machines Corporation | Corrupt logical block addressing recovery scheme |
CN112003626B (zh) * | 2020-08-31 | 2023-11-10 | 武汉梦芯科技有限公司 | 一种基于导航电文已知比特的ldpc译码方法、系统和介质 |
CN114765055B (zh) * | 2021-01-14 | 2024-05-03 | 长鑫存储技术有限公司 | 纠错系统 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5271012A (en) * | 1991-02-11 | 1993-12-14 | International Business Machines Corporation | Method and means for encoding and rebuilding data contents of up to two unavailable DASDs in an array of DASDs |
US5644695A (en) * | 1994-01-03 | 1997-07-01 | International Business Machines Corporation | Array combinatorial decoding with multiple error and erasure detection and location using cyclic equivalence testing |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4556977A (en) | 1983-09-15 | 1985-12-03 | International Business Machines Corporation | Decoding of BCH double error correction - triple error detection (DEC-TED) codes |
EP0519669A3 (en) | 1991-06-21 | 1994-07-06 | Ibm | Encoding and rebuilding data for a dasd array |
JP3451221B2 (ja) * | 1999-07-22 | 2003-09-29 | 日本無線株式会社 | 誤り訂正符号化装置、方法及び媒体、並びに誤り訂正符号復号装置、方法及び媒体 |
US6961888B2 (en) * | 2002-08-20 | 2005-11-01 | Flarion Technologies, Inc. | Methods and apparatus for encoding LDPC codes |
KR100996029B1 (ko) * | 2003-04-29 | 2010-11-22 | 삼성전자주식회사 | 저밀도 패리티 검사 코드의 부호화 장치 및 방법 |
US7234098B2 (en) * | 2003-10-27 | 2007-06-19 | The Directv Group, Inc. | Method and apparatus for providing reduced memory low density parity check (LDPC) codes |
US7543212B2 (en) * | 2004-09-13 | 2009-06-02 | Idaho Research Foundation, Inc. | Low-density parity-check (LDPC) encoder |
KR100734262B1 (ko) | 2004-12-07 | 2007-07-02 | 삼성전자주식회사 | 광 저장 매체의 최적화된 결함 처리를 위한 결함 판단 장치 |
KR20060135451A (ko) * | 2005-06-25 | 2006-12-29 | 삼성전자주식회사 | 저밀도 패리티 검사 행렬 부호화 방법 및 장치 |
JP4662367B2 (ja) * | 2006-04-18 | 2011-03-30 | 共同印刷株式会社 | 情報シンボルの符号化方法及びその装置並びに情報シンボルの復号化方法及び復号化装置 |
US7831895B2 (en) * | 2006-07-25 | 2010-11-09 | Communications Coding Corporation | Universal error control coding system for digital communication and data storage systems |
US8065598B1 (en) * | 2007-02-08 | 2011-11-22 | Marvell International Ltd. | Low latency programmable encoder with outer systematic code and low-density parity-check code |
US8020063B2 (en) * | 2007-07-26 | 2011-09-13 | Harris Corporation | High rate, long block length, low density parity check encoder |
-
2008
- 2008-10-16 EP EP08305690A patent/EP2178215A1/en not_active Withdrawn
-
2009
- 2009-09-25 TW TW098132378A patent/TWI492548B/zh not_active IP Right Cessation
- 2009-10-07 US US12/587,419 patent/US8245106B2/en active Active
- 2009-10-08 KR KR1020090095595A patent/KR101562606B1/ko not_active IP Right Cessation
- 2009-10-09 EP EP09172674A patent/EP2178216A1/en not_active Withdrawn
- 2009-10-14 JP JP2009237428A patent/JP5543170B2/ja not_active Expired - Fee Related
- 2009-10-16 CN CN200910205192.9A patent/CN101729077B/zh not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5271012A (en) * | 1991-02-11 | 1993-12-14 | International Business Machines Corporation | Method and means for encoding and rebuilding data contents of up to two unavailable DASDs in an array of DASDs |
US5644695A (en) * | 1994-01-03 | 1997-07-01 | International Business Machines Corporation | Array combinatorial decoding with multiple error and erasure detection and location using cyclic equivalence testing |
Non-Patent Citations (1)
Title |
---|
HACHIRO FUJITA ET AL: "Modified Low-Density MDS Array Codes for Tolerating Double Disk Failures in Disk Arrays" IEEE TRANSACTIONS ON COMPUTERS, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, vol. 56, no. 4, 1 April 2007 (2007-04-01), pages 563-566 MARIO BLAUM ET AL: "MDS Array Codes with Independent Parity Symbols" IEEE TRANSACTIONS ON INFORMATION THEORY, IEEE, US, vol. 42, no. 2, 1 March 1996 * |
Also Published As
Publication number | Publication date |
---|---|
EP2178216A1 (en) | 2010-04-21 |
JP2010098735A (ja) | 2010-04-30 |
KR101562606B1 (ko) | 2015-10-23 |
CN101729077B (zh) | 2014-03-12 |
US8245106B2 (en) | 2012-08-14 |
TW201018096A (en) | 2010-05-01 |
CN101729077A (zh) | 2010-06-09 |
US20100269025A1 (en) | 2010-10-21 |
EP2178215A1 (en) | 2010-04-21 |
KR20100042589A (ko) | 2010-04-26 |
JP5543170B2 (ja) | 2014-07-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20200177208A1 (en) | Device, system and method of implementing product error correction codes for fast encoding and decoding | |
US10146618B2 (en) | Distributed data storage with reduced storage overhead using reduced-dependency erasure codes | |
US7956772B2 (en) | Methods and apparatus employing FEC codes with permanent inactivation of symbols for encoding and decoding processes | |
US8522122B2 (en) | Correcting memory device and memory channel failures in the presence of known memory device failures | |
US7447970B2 (en) | Soft-decision decoding using selective bit flipping | |
US8560930B2 (en) | Systems and methods for multi-level quasi-cyclic low density parity check codes | |
JP4651990B2 (ja) | 有限幾何学コードの受信ワードを復号化する方法 | |
US9654147B2 (en) | Concatenated error correction device | |
US8694872B2 (en) | Extended bidirectional hamming code for double-error correction and triple-error detection | |
US8806295B2 (en) | Mis-correction and no-correction rates for error control | |
TWI492548B (zh) | 二元資料之改錯和偵錯方法 | |
CN100428176C (zh) | 根据(18,9)dec-ted码从数据字生成码字、对其解码的方法和装置 | |
Huang et al. | XI-Code: a family of practical lowest density MDS array codes of distance 4 | |
US20200089417A1 (en) | Memory system | |
KR102007163B1 (ko) | 인코더, 디코더 및 이를 포함하는 반도체 장치 | |
Huang et al. | An improved decoding algorithm for generalized RDP codes | |
GB2531783A (en) | Method and device for removing error patterns in binary data | |
US20160043741A1 (en) | Coding method and device | |
He et al. | Outer Channel of DNA-Based Data Storage: Capacity and Efficient Coding Schemes | |
Surekha et al. | IMPLEMENTATION OF LOW-COMPLEXITY LDPC CODES FOR LOSSLESS APPLICATIONS | |
Sharath et al. | Error Locked Encoder and Decoder for Nanomemory Application | |
WO2010066777A1 (en) | Error correction method | |
HALIM | Contributions to the decoding of linear codes over Z4 | |
Eze et al. | Innovative Improvement of Data Storage Using Error Correction Codes |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |