US8065598B1  Low latency programmable encoder with outer systematic code and lowdensity paritycheck code  Google Patents
Low latency programmable encoder with outer systematic code and lowdensity paritycheck code Download PDFInfo
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 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
 H03M13/1102—Codes on graphs and decoding on graphs, e.g. lowdensity parity check [LDPC] codes
 H03M13/1148—Structural properties of the code paritycheck or generator matrix
 H03M13/116—Quasicyclic LDPC [QCLDPC] codes, i.e. the paritycheck matrix being composed of permutation or circulant submatrices

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
 H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
 H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/65—Purpose and implementation aspects
 H03M13/6561—Parallelized implementations

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/13—Linear codes
 H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, BoseChaudhuriHocquenghem [BCH] codes
 H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, BoseChaudhuriHocquenghem [BCH] codes using error location or error correction polynomials
 H03M13/152—BoseChaudhuriHocquenghem [BCH] codes
Abstract
Description
This claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Application No. 60/888,852 filed Feb. 8, 2007, which is hereby incorporated herein by reference in its entirety.
The disclosed technology relates generally to data processing, and more particularly to lowlatency programmable encoders.
With the continuing demand for highreliability transmission of information in digital communication and storage systems, and with the rapid increase in available computational power, various coding and decoding techniques have been investigated and applied to increase the fidelity of these systems. One such coding technique, lowdensity parity check (LDPC) coding, was first proposed in the 1960s, but was not used until the late 1990s when researchers began to investigate iterative coding and decoding techniques.
LDPC codes are among the few known error control coding techniques capable of transmitting information at a rate close to the Shannon limit or channelcapacity. Currently, LDPC codes are considered to be the nextgeneration communication system encoding standard. LDPC codes can be regular or irregular, have a linear or cyclic encoding matrix, and can be decoded in a myriad of ways, ranging in complexity and error performance. LDPC codes can also be encoded quite simply because LDPC coding and decoding are generally performed iteratively, reducing the memory requirements for an LDPC encoder. For example, an LDPC encoder is typically implemented using linear or cyclic shift registers, in which the results of the LDPC encoder block matrixvector multiplication are accumulated in a memory buffer at each calculation step. In particular, the encoding algorithm may be implemented on data processing circuitry, such as a fieldprogrammable gate array (FPGA) or application specific integrated circuit (ASIC). Thus, many LDPC encoders are also programmable, making it easy to change encoding parameters, such as block length or code rate, without having to redesign (or rebuild) the LPDC encoders.
However, there are a few concerns with LDPC codes. Lengthy LDPC codes may require large memory buffers and/or computational power, even when the paritycheck matrix may be sparse. In addition, the error floor of LDPC codes may be a concern; usually this error floor is high. It may be difficult to implement a low error floor LDPC code without making the code block length large. As mentioned above, if the code block length is large, the LDPC codes may require larger memory buffers. This may be especially true in devices with programmable encoders—e.g., encoders that are operable over a wide range of parameters such as block length, number of block rows, number of block columns, and code rate.
A possible solution for lowering the error floor of an LDPC code may be to use an outer systematic code, such as a ReedSolomon (RS) or BoseChaudhuriHocquenghem (BCH) code. However, such codes are typically implemented in a serial manner. For example, a message to be encoded may be first encoded with an outer BCH code, and the resulting code can then be encoded as an LDPC code. Such seriallyimplemented encoding systems, however, typically require multiple memory buffers and have high latency—e.g., the latency (or time delay in number of codewords) may be as high as 23 codewords.
In accordance with the principles of this invention, systems and methods for lowlatency programmable encoders which use LDPC codes in combination with an outer systematic code, for example an RS or BCH code, are provided. Generally, in one aspect, the encoder may be implemented in part of the resources or memory of a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).
In one embodiment of the present invention, an LDPC encoder may generate a codeword based on a suitable LDPC code. The codeword may have a message segment corresponding to the original message symbols, an outer code parity segment corresponding to the parity bits generated by an outer encoder (e.g., BCH encoder), and an LDPC parity segment that is generated by the LDPC encoder. The LDPC code used by the LDPC encoder can be associated with a parity check matrix that is decomposed into three portions: a corresponding message portion, outer code parity portion, and LDPC parity portion.
To produce the LDPC parity segment, the LDPC encoder can first process the message segment based on the message portion of the parity check matrix. For example, the LDPC encoder may perform a matrixvector multiplication with the message portion and the message segment. The LDPC encoder may then process the outer code parity segment based on the outer code parity portion subsequent to processing the message segment. For example, the LDPC encoder may perform a matrixvector multiplication with the outer code parity portion and the outer code parity segment.
The LDPC encoder can then generate the LDPC parity segment from the processed message segment and processed outer code parity segment based on the LDPC parity portion. In some embodiments, the LDPC encoder may combine the two matrixvector products to produce a complete matrixvector product that is representative of the entire data input portion of the parity check matrix. The LDPC parity segment may comprise a parity segment generated by the LDPC encoder that can be appended to the input message vector to obtain a systematic LDPC codeword.
In some embodiments of the present invention, the LDPC encoder may be programmable for any irregular circulantbased LDPC code. For example, the code profile, block length, number of block rows, and number of block columns can be programmable.
In some embodiments, the LDPC encoding and the outer systematic code encoding can proceed in a parallel manner, i.e., the LDPC encoding and outer system code encoding can occur simultaneously, instead of in a serial manner. This parallel processing may reduce the memory and latency requirements for system. In an exemplary embodiment of the system, such a parallel operability may be enabled by computational and memory update mechanisms for the block matrixvector multiplication in the LDPC encoder. That is, the LDPC encoder can operate initially without knowledge of the outer code parity bits (e.g., using only the message portion of the parity check matrix) and may add the outer code parity bits into the computation (e.g., using the outer code parity portion of the parity check matrix) once these bits are made available.
In an exemplary embodiment of the system, the LDPC encoder and outer systematic encoder can interface together without additional memory buffers or excessive latency as would be required if the two encoders were operating in a serial manner. Both the LDPC encoder and the outer systematic code encoder may read from the same input buffer, where both the LDPC encoder and outer systematic code encoder may begin operating on a stored message at the same time. The outer systematic code encoder may then store the outer code parity bits back into the input buffer upon completion of an encoding process so that the outer code parity bits can be made available to the LDPC encoder. In some embodiments, without the memory latency, the latency of the overall encoding process may be only one code word.
In some embodiments, an encoder for generating a codeword from message symbols based on a concatenated code is provided. This encoder may comprise an outer systematic code encoder for calculating a first set of parity symbols from the message symbols, an inner systematic code encoder for computing a second set of parity symbols from the message symbols and the first set of parity symbols, and an output unit which may generate the codeword from the first and second set of parity symbols. The inner systematic code encoder may operate based on the message symbols while the outer systematic code encoder generates the first set of parity symbols.
The outer systematic code encoder may be operable to encode the message symbols using a BoseChaudhuriHocquenghem (BCH) code, while the inner systematic code encoder may be operable to encode the message symbols and the first set of parity symbols using a lowdensity parity check (LDPC) code. In some embodiments, the inner systematic code encoder may have programmable code parameters, and the inner systematic code encoder may generate the second set of parity symbols based on a current setting of the code parameters. The code parameters of the inner systematic code encoder can include at least one of a block length, a number of block rows, a number of block columns, and a code rate.
In some exemplary embodiments, the encoder may include an input buffer for storing the message symbols such that the inner code encoder and the outer code encoder can be configured to read from the input buffer to obtain the message symbols. Optionally, the outer systematic code encoder may be configured to store the first set of parity symbols in the input buffer with the message symbols, and the inner systematic code encoder may be configured to read from the input buffer to obtain the first set of parity symbols. The output unit may be configured to obtain the first set of parity symbols and the message symbols from the input buffer, and may obtain the second set of parity symbols from the inner systematic code encoder.
In some embodiments, the inner systematic code encoder may include an inner code control ROM for storing one or more parity check matrices associated with the inner systematic code, an inner code control unit that may interface with the inner code control ROM, and an inner code computation unit for computing the second set of parity symbols. The inner code control unit may select portions of one of the one or more parity check matrices that the inner code computation unit can use to compute the second set of parity symbols.
The inner systematic code encoder may be associated with a parity check matrix having a data portion and an outer code parity portion. Optionally, the inner code encoder may be configured to compute a first vectormatrix multiplication between the data portion and a vector of the message symbols while the outer systematic code encoder generates the first set of parity symbols. The inner code encoder may then compute a second vectormatrix multiplication between the outer code parity portion and a vector of the first set of parity symbols.
In some embodiments, a method for generating a codeword from message symbols is provided. This method may comprise calculating a first set of parity symbols from the message symbols using an outer code in a first time interval and computing a second set of parity symbols from the message symbols and the first set of parity symbols using an inner code. In one embodiment, computing the second set may include computing intermediate symbols based on the message symbols during the first time interval, updating the intermediate symbols based on the first set of parity symbols in a second time interval subsequent to the first time interval, and generating the codeword from the first and second set of parity symbols. The updated set of intermediate symbols may be usable to produce the second set of parity symbols.
In some embodiments, the method for generating a codeword may involve computing the first set of parity symbols based on a BoseChaudhuriHocquenghem (BCH) code, and computing the second set of parity symbols based on a lowdensity parity check (LDPC) code.
In some embodiments, the method may involve storing the message symbols in an input buffer. In some embodiments, calculating the first set of parity symbols may comprise obtaining the message symbols from the input buffer, computing the first set of parity symbols from the obtained message symbols, and storing the first set of parity symbols in the input buffer with the message symbols. Optionally, computing the second set of parity symbols may comprise obtaining the message symbols from the input buffer, computing the intermediate symbols based on the obtained message symbols during the first time interval, obtaining the first set of parity symbols from the input buffer during the second time interval, and updating the intermediate symbols based on the obtained first set of parity symbols.
The inner code may be associated with a parity check matrix having a data portion and an outer code parity portion. In some embodiments, computing the intermediate symbols may include computing a first matrixvector multiplication of the data portion with a vector of the message symbols. Updating the intermediate symbols may comprise computing a second matrixvector multiplication of the outer code parity portion with a vector of the first set of parity symbols.
The above and other aspects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:
The systems and methods of the invention generally relate to lowlatency programmable encoders which use LDPC codes in combination with an outer systematic code. The LDPC and outersystematic codes may represent one class of codes, called errorcorrection codes (ECC), that may be used to detect and/or correct errors. Error correcting codes are often used to correct errors which may occur during transmission or storage. Thus, the disclosed encoders would be desirable in highreliability digital communication or storage systems in which lowlatency and low memory buffering are desired. As used herein, encoding may generally refer to the process of generating data in a manner that facilitates subsequent detection and/or correction of errors in the data, while decoding may generally refer to the counterpart process of detecting and/or correcting the errors.
Encoder 104 may encode user information 102 using lowdensity parity check (LDPC) codes with outer systematic codes. Thus, encoder 104 may be composed of two encoders: systematic encoder 105, which generates a systematic codeword 109 from user information 102, and LDPC encoder 107, which generates codeword 106 from systematic codeword 109. Thus, the ECC code employed by encoder 104 is an example of a concatenated code, i.e., a code which is generated from combining multiple codes. For a concatenated code based on two codes, such as the concatenated code employed by encoder 104, the two codes may be referred to as an outer code and an inner code. Systematic encoder 105 can employ the outer code, which is the first code applied to user information 102 (or the message vector), to produce outer systematic codeword 109, i.e., the outer codeword or outer codeword vector. LDPC encoder 107 can employ the inner code, which is the second code applied to user information 102, to produce codeword 106, i.e., the inner codeword (or inner codeword vector). For convenience, an outer codeword may sometimes be referred to by the symbol D, the length of an outer codeword (e.g., outer codeword 109) may be referred to by the symbol, n_{outer}, and the length of an inner codeword (e.g., codeword 106) may be referred to by the symbols, n_{inner }or n.
In some exemplary embodiments, systematic encoder 105 may encode user information 102 based on a BCH code, but systematic encoder 105 may instead encode user information 102 using any other systematic error correcting code. The result of encoding user information 102 is codeword 106. Codeword 106 may be of a predetermined length, which may be referred to as n.
In one implementation, codeword 106 is passed to a modulator 108. Modulator 108 prepares codeword 106 for transmission on channel 110. Modulator 108 may use phaseshift keying, frequencyshift keying, quadrature amplitude modulation, or any suitable modulation technique to modulate codeword 106 into one or more informationcarrying signals. Channel 110 may be an asymmetric or symmetric channel. Channel 110 may represent media through which the informationcarrying signals travel. For example, channel 110 may represent a wired or wireless medium in a communication system, or an electrical (e.g., RAM, ROM), magnetic (e.g., a hard disk), or optical (e.g., CD or DVD) storage medium in which the informationcarrying signals can be stored.
Received waveform 111 may be demodulated with demodulator 112. Demodulator 112 can demodulate received waveform 111 with filters, multiplication by periodic functions, or any suitable demodulation technique corresponding to the type of modulation used in modulator 108. Note that received waveform 111 may be subject to noise and, therefore, the resulting soft information 114 (or soft estimate of user information 102) may contain errors.
Resulting soft information 114 may be processed by decoder 116. Decoder 116 can be used to correct or detect errors in soft information 114. Decoder 116 may use iterative messagepassing decoding, syndrome decoding, or any suitable decoding technique corresponding to the errorcorrection code used in encoder 104. For example, as soft information 114 may correspond to data encoded by an outer systematic code and an inner LDPC code, decoder 116 can include a corresponding LDPC decoder and systematic code decoder that operate using any suitable decoding technique. For the LDPC decoder, decoder 116 may use belief propagation to decode soft information 114, for example. Once decoder 116 has decoded the soft information 114, decoder 116 outputs decoded information 118.
LDPC codeword vector 212 may include n data bits. LDPC codeword vector 212 may be constructed by multiplying generator matrix 214 by outer codeword vector 216. The resulting LDPC codeword vector 212 may be codeword 106 depicted in
LDPC codes are conventionally expressed in terms of a parity check matrix, H. Equation 220 illustrates parity check matrix 222 of the LDPC code employed by, for example, LDPC encoder 107 of
Parity check matrix 222 can be decomposed into two submatrices, as illustrated in equation 230, based on two subvectors of LDPC codeword vector 212. Equation 230 illustrates submatrices 232 and 234 of parity check matrix 222, and subvectors 236 and 238 of LDPC codeword vector 212, for an irregular lowdensity parity check code. Submatrix 232 may be referred to as the data portion of parity check matrix 222 (or matrix A), while submatrix 234 may be referred to as the parity portion of parity check matrix 222 (or matrix B). The data portion A of parity check matrix 222 is the portion of this matrix that, when performing LDPC encoding, multiplies the outer codeword subvector D within the codeword vector C. The parity portion B of the parity check matrix is the portion of this matrix that multiplies the parity subvector P within codeword C. The parity portion of submatrix 232 may be a matrix of size r by np (or equivalently, r by n_{outer}), where p is the number of parity bits in a row of the parity portion of parity check matrix 222. Submatrix 234 may be a matrix of size r by p. Subvector 236 is the outer codeword vector, D, and therefore may includes the same information as outer codeword vector 216, namely message vector U and the outer systematic parity bits P_{1}. Subvector 238 is the parity vector of the LDPC code, P. As is the case in Equation 220, when parity check matrix 222 is multiplied by LDPC codeword vector 212, the result is a zero vector 226 of size r.
C=GU (EQ. 1)
The product of paritycheck matrix H and codeword C is a zero vector as shown in EQ. 2:
HC=
Paritycheck matrix H can be partitioned into a data portion A and a parity portion B as follows:
H=[AB] (EQ. 3)
Codeword C can be partitioned into a message vector U, outer systematic parity bits P_{1}, which may be generated by the outer systematic encoder 105 of
The outer systematic code used by systematic encoder 105 may be an RS code, a BCH code, or any other systematic ECC. As mentioned above, the parity vector P_{2}, specified by the LDPC encoder 107 of
In this case, as described above, U is the message vector and P_{1 }is a vector of parity symbols specified by the outer systematic code, e.g., a BCH code.
Codeword C may be an example of codeword 106 generated by the encoder 104 of
AD=X (EQ. 6)
Equation 230 of
BP=X (EQ. 7)
Thus, the parity vector P (or P_{2 }in EQ. 4) can be obtained by multiplying X with the matrix inverse of B, inv(B), as shown in EQ. 8:
P=P _{2} =inv(B)X=B ^{−1} X=X/B (EQ. 8)
Thus, mathematically, LDPC encoder 107 of
In hardware implementations of lowdensity parity check codes, it may be computationally desirable to have quasicyclic code representations. LDPC encoder 107 of
A quasicyclic matrix can be composed of circular submatrices known as circulants. In some embodiments, the parity check matrix (e.g., parity check matrix 222 of
Circulant 300 of
In some embodiments, block matrix 305 may be thought of as having two parity check matrix portions: submatrix 306 and submatrix 308. Submatrix 306 is the data portion of block matrix 305 which multiplies the outer codeword vector, while submatrix 308 is the parity portion of block matrix 305. The data portion of block matrix 305 may correspond to the A matrix in EQS. 3 and 6, or submatrix 232 in
As described above in connection with EQS. 4 and 5, the LDPC codeword provided by, for example, LDPC encoder 107, includes three segments—the message vector U, the parity symbols produced by the outer systematic code, P_{1}, and the symbols produced by the LDPC encoder 107, P_{2 }or P. For example,
These three segments may be associated with the three portions of parity check matrix 410: portions 404, 405, and 406. Portion 404 may be referred to as a message portion and is the portion of the parity check matrix that is multiplied by message segment 401. Portion 405 may be referred to as the outer code portion and is the portion of the parity check matrix multiplied by BCH parity segment 402. As shown in
To generate a codeword 400 from an outer systematic codeword (e.g., a BCH codeword), BCH parity segment 402 of codeword 400 may be concatenated to message vector 401. Codeword 400 can then be created by appending the LDPC parity vector 403 to the resulting combination of message vector U or 401 and BCH parity bits P_{1 }or 402. This implementation may be carried out, e.g., in an FPGA or ASIC, in the manner described below.
Parity check matrix 410 of
During typical operation of BCHLDPC encoder 500, a message vector U is input into memory buffer 501. BCH encoder 502 may then append the BCH segment P_{1 }of the codeword to the message vector U. Once this process is complete, the message vector U with the BCH parity vector P_{1 }passes into LDPC encoder 504 via LDPC input memory buffer 503. LDPC encoder 504 outputs the LDPCBCH codeword C into the output memory buffer 505.
Memory buffers 501, 503 and 505 may be of different sizes. For example, for codeword 400 in
BCHLDPC encoder 500 performs BCH encoding and LDPC encoding in a serial manner. Thus, the latency of BCHLDPC encoder 500 may be up to at least three codewords. One of the reasons for this is the lack of parallelization of the encoding process, i.e., the inner BCH encoding is completed prior to starting the outer LDPC encoding. This may be necessary in LDPC encoding implementations that need the result of the outer codeword in order to operate. Also, as described above, the memory requirement of BCHLDPC encoder 500 may be up to eight times the size of an input message. For systems where high encoding speeds and low memory requirement are desirable, it may be advantageous to implement a BCHLDPC encoder (e.g., encoder 104 of
Accordingly, embodiments of the present invention provide approaches to encoding data based on an inner LDPC code and an outer systematic code that have lower latency and memory requirements. In particular,
The LDPC encoders illustrated in
In certain other embodiments, the LDPC encoders of
These implementation approaches are merely illustrative. The LDPC encoders of
In some embodiments, LDPC encoder 600 may be used to produce an quasicyclic lowdensity parity check (QCLDPC) codeword, such as codeword 400 in
LDPC encoder 600 processes input vector 610 and computes both X (labeled 640 in
Rather than computing the matrixvector multiplication with the entire A matrix in parallel, the multiplication may be broken up into two phases. The first phase may be associated with the message portion of the A matrix, such as with message portion 404 of
The second phase of the A matrix matrixvector multiplication may be associated with the outer code parity portion of the A matrix, and may involve performing a matrixvector multiplication between the outer code parity portion with the outer code parity segment P_{1 }of input vector 610. The matrixvector products produced by each phase, which may each be referred to as partial products, can be combined into a single, complete matrixvector product of the A matrix with input vector 610 (D).
Note that the first phase of the matrixvector multiplication does not require the value of the outer code parity segment of input vector D. Thus, serial block matrixvector multiplication module 602 may begin operating in the first phase before the values of the outer code parity bits are known. This approach advantageously allows inner LDPC encoder 600 to operate in parallel with an outer code encoder, i.e., a BCH encoder.
Serial block matrixvector multiplication module 602 may further break down each of the two phases into smaller computations that are performed in serial stages. In particular, serial block matrixvector multiplication module 602 may process each circulant of the A matrix separately, regardless of whether the circulant is in the message portion or the outer code parity portion of the A matrix, and can proceed either rowbyrow or columnbycolumn in the appropriate portion of the A matrix.
Using parity check matrix 410 and rowbyrow processing as an example, serial block matrixvector multiplication module 602 may first work with the message portion of the matrix 410, and can multiply a first block of input vector 610 (e.g., the first 16 bits for Z=16) by the upperleft 11valued circulant. Serial block matrixvector multiplication module 602 may then proceed to multiply that same block by −1, 8, and 13 (e.g., the remaining blocks in the first row of message portion 404), before moving to the next row of parity check matrix 410 and a second block of input vector 610 (e.g., the second 16 bits). Once the rows of the message portion have been processed, multiplication module 602 may apply the same rowbyrow approach to outer parity portion 405 of parity check matrix 410. For each row of the A matrix, a block of the X vector (e.g., a 16bit block referred to as X_{0}) can be produced by adding, modulo2, the result of the multiplications for that same row. The blocks of matrixvector product X (640) may then be stored in buffer 603.
From matrixvector product 640, parity vector 660 may be computed by the recursive back substitution module 604. Recursive back substitution module 604 may carry out the computation encompassed in EQS. 7 and 8. That is, recursive back substitution module 604 may multiply the matrixvector product X by the inverse of the parity portion B in the parity check matrix. Because X is an intermediate value used to compute the parity vector 660, X may sometimes be referred to as an intermediate vector. Recursive back substitution module 604 may compute parity vector 660 from the intermediate vector in two stages using a backsubstitution procedure. First, recursive back substitution module 604 may operate in a first mode to add the blocks of matrixvector product X together. This summation computation may be referred to as a sumX computation, for simplicity, and the resulting sum may be used to in a back substitution computation. The sumX operation and the back substitution operation together produce the sizeZ blocks of parity vector 660 in a serial manner. These two modes will be described in greater detail below in connection with
In some embodiments, recursive back substitution module 604 of LDPC encoder 600 uses one or more XOR gate arrays for computation of sumX and the back substitution procedure. Only one such XOR gate array of size Z may be needed if one entry in parity vector 660 is computed in one clock cycle of the FPGA or ASIC. Additionally, in some embodiments, the speed of encoding may be increased by using two or more size Z XOR gate arrays, since some of the recursive operations may be performed in parallel. In this case, two or more parity vector blocks may be computed in one clock cycle of the FPGA or ASIC. Such an implementation speeds up the encoding of the QCLDPC codeword 620.
Note that the matrixvector multiplication to serially obtain X and the sumX accumulation of the entries in X can operate based on sizeZ blocks and sizeZxZ circulants. That is, after each serial stage, serial block matrixvector multiplication module 602 can produce an entry of the X matrix. Therefore, serial block matrixvector multiplication module 602 does not need to compute the entire X vector in order for recursive back substitution module 604 to begin computing sumX.
Recursive back substitution module 604 may instead accumulate the blocks of X as they are being computed by serial block matrixvector multiplication module 602. That is, recursive back substitution module 604 can update the accumulated sum after each block of X is computed. This and other features can be more readily appreciated by the block diagram shown in
Each of the components of block serial LDPC encoder 700 may process M bits in parallel, where M is divisible by the length of inner codeword 710 and is usually a positive integer power of 2 (e.g., M=2^{m }where m is a positive integer). The value of M may sometimes be referred to as the parallelism of M. For example, if block serial LDPC encoder 700 is associated with a parity check matrix made up of circulants of size Z=16 (e.g., parity check matrix 410 of
During operation of block serial LDPC encoder 700, input vector 710 may be first stored in input memory buffer 701. In this exemplary embodiment, the word size of input memory buffer 701 may be M (the parallelism) and the depth may be given by n_{outer}/M. In certain embodiments, the input memory buffer 701 has two or three times the data storage capacity of the size of input vector 710. This triple buffering allows the encoder to accommodate the additional memory resources needed due to the requirements of the write channel on some implementations memory buffer 701. However, the size of input memory buffer 701 can be decreased to one or two times the size of input vector 710 for other buffer implementations that have lesser write channel requirements.
Block selector 702, data selector 703, and cyclic block shifter 704 may perform part of the vectormatrix multiplication described above in connection with serial matrixvector multiplication module 602 of
In one implementation, block serial LDPC encoder 700 includes block selector 702 and data selector 703 to identify which of the M×M blocks of a parity check matrix that cyclic block shifter 704 should currently be operating with. Block selector 702 may identify the appropriate circulant based on, for example, the previous circulant that was processed and whether the message or the outer code parity portions of the parity check matrix are being processed. Based on the current circulant, block selector 702 may identify Z bits of input vector 710 that correspond to the current circulant of the parity check matrix. For instance, if input vector 710 is 80 bits and Z=16, block selector 702 may keep track of which of the five 16bit blocks should be multiplied by the current circulant, and can provide the appropriate block of bits to data selector 703.
From the block of Z bits identified by block selector 702, data selector 703 may identify a current segment of M bits (e.g., 8 bits) in the block to pass to cyclic block shifter 704. Cyclic block shifter 704 may then multiply the supplied M bits of input vector 710 with the M×M portion of the current circulant to produce a partial matrixvector product for a portion of a block X.
Thus, (in one implementation) block selector 702, data selector 703, and cyclic block shifter 704 may be configured to compute the matrixvector product of a circulant in multiple cycles. The matrixvector product for one circulant may sometimes be referred to as a fractional matrixvector product, because this product is only part of the calculation to produce a block of matrixvector product X. As described above, block selector 702, data selector 703, and cyclic block shifter 704 may be configured to complete the fractional matrixvector product for a circulant (e.g., the topleft circulant with value 11 in
In one implementation, block serial LDPC encoder 700 is not restricted to cycling through the circulants of the parity check matrix in any particular order, and therefore block selector 702, data selector 703, and cyclic block shifter 704 may be configured to iterate through the circulants in the message portion of the parity check matrix (e.g., portion 404 in
The current segment of X, or X_{i } 708, may be input to logic block 760. In one implementation, logic block 760 includes size M XOR array 705. XOR array 705 can include an array of logic components configured to perform exclusiveor (XOR) bit operations. XOR array 705 can complete the matrixvector multiplication started by cyclic block shifter 704, perform the sumX computation to serially accumulate the entries of vector X, and perform the recursive backsubstitution computations to serially compute the blocks of parity vector P.
In one implementation, cyclic block shifter 704 provides fractional matrixvector products for a current row or column in different clock cycles. Thus, if block serial LDPC encoder 700 operates on the circulants rowbyrow, logic block 760 may receive all of the fractional matrixvector products for a given row of the data portion A in multiple clock cycles. Note that the cycles may not be consecutive, because the rows of the message portion of a parity check matrix and the rows of the outer code parity portion of the parity matrix are operated on separately. For example, referring briefly back to
Thus, logic block 760 may be operable to accumulate the fractional products as they are provided from cyclic block shifter 704. For example, the sum of the fractional products for a row computed thus far may be stored in X/P memory buffer 706. When a new fractional product for the same row of the data portion A is received, XOR array 705 may be configured to add the previous sum 750 obtained from X/P memory buffer 706 to the newly received fractional product to obtain an updated sum 740. The updated sum of fractional matrixvector products may be stored back into X/P memory buffer 706 by overwriting the previous sum. In this way, logic block 760 can act as an accumulator with an update mechanism that allows X/P memory buffer 706 to compute a block of X.
Because of this serial update mechanism, logic block 760 is fully customizable to any number of nonzero circulants in each row. That is, because the update mechanism involves only a modulo2 addition of a stored value and a new value, the implementation of logic block 760 does not depend on the number of fractional matrixvector products included in the summation. Therefore, block serial LDPC encoder 700 has the advantageous property of being capable of operating based on irregular codes regardless of the difference in weight between the rows or columns of the parity check matrix. In addition, block serial LDPC encoder 700 has the advantageous property of being programmable for any suitable code profile, block length, or any other code characteristic.
While modules 702, 703, and 760 compute the blocks of the matrixvector product X, logic block 760 may additionally compute the sum of all of the X matrixvector products, or sumX, in parallel. In order to have the resources to complete these operations concurrently, XOR array M may include 2M XOR components—M for computing X and another M for computing sumX. X/P memory buffer 706 may include storage space to store both of these values. The sum of the X matrixvector products may be used to recursively compute the LDPC parity vector 730, as described herein using the parity check matrix specified in the IEEE 802.11n standard as an example. The contents of the IEEE 802.11n standard is hereby incorporated by reference herein in its entirety.
In some embodiments, the parity check matrix used by block serial LDPC encoder 700 may correspond to the parity check matrix specified in the 802.11n standard. In these embodiments, the parity portion B of the parity check matrix used by recursive back substitution module 604 is a dual diagonal block matrix. Given matrixvector product X and parity portion B of the parity check matrix H, the entries of parity vector P may be computed by recursive back substitution module 604 using EQ. 9:
Note that I denotes a block identity matrix, I^{c }denotes a cyclic shift of c rows or columns of the identity matrix I, and I^{d }denotes a cyclic shift of d rows or columns of the identity matrix I. Parity vector P includes entries p_{0}, p_{1}, . . . , p_{q1}, whereas the X vector includes entries x_{0}, x_{1}, . . . , x_{q1}. The nonnegative integer indices i, j, and q are reference symbols for the entries of vectors X and/or P, where q refers to the number of blocks in the parity vector 730 and may be given by, n_{outer}/Z.
Matrixvector EQ. 9 can be rewritten as the following series of equations:
p _{0} ^{c}+p_{1} =x _{0} (EQ. 10)
p _{i} +p _{i+1} =x _{i} ,i≠0,i≠q−1,i≠j−1 (EQ. 11)
p _{0} ^{d}+p_{j1} +p _{j} =x _{j1} (EQ. 12)
p _{0} ^{c}+p_{n1} =x _{q1} (EQ. 13)
from which it is clear the dual diagonal structure of matrix B has been exploited. That is, it is clear that the structure of matrix B results in EQS. 1013, which can be solved recursively by, for example, logic block 760 using the serial update mechanism or recursive back substitution module 604 of
Since the cyclic shifts c and d are known, the first entry of the parity vector (e.g., parity vector 660), p_{0 }can easily be obtained from p_{0} ^{d}. The value of p_{0} ^{c }may be obtained easily as well. EQ. 14 illustrates the sumX computation performed by logic block 760. Therefore, the sumX computation can be thought of as part of the calculation to obtain parity vector X. Because EQ. 14 can be computed in parallel with the summations to compute blocks of P, in these embodiments, logic block 760 is effectively able to compute the entries of the X vector and the entries of the P vector in parallel. This can advantageously allow block serial LDPC encoder 700 to have a reduced encoding latency, and is part of the reason that the latency can be reduced to, for example, one codeword.
Once logic block 760 has computed all of the entries of matrixvector product X and logic block 760 has obtained the first entry of parity vector P from EQ. 14, logic block 760 may compute the remaining blocks of parity vector P. That is, the other blocks in the recursively by logic block 760. For example, logic block 760 may use the update mechanism described above, and can utilize the recursive accumulation equations of EQ. 13 and EQ. 14 to compute p_{1 }using p_{0}, then p_{2 }using p_{1 }and p_{0}, etc., until all the blocks of parity vector P have been computed.
In one embodiment, p_{1 }and p_{q1 }are computed by logic block 760 or recursive back substitution module 604 (
p _{i} =p _{i−1} +x _{i−1, 2} ≦i≦j−1 (EQ. 15)
p _{i} =p _{i+1} x _{i} , j≦i≦q−2 (EQ. 16)
In this embodiment, the computations of the respective parity vector entries in EQS. 15 and 16 may be performed in parallel by recursive back substitution module 604. For instance, p_{2 }and p_{n2 }may be computed at the same time and then p_{3 }and p_{n3 }may be computed at the same time. Such computation allows for a blocklevel parallelization of the recursive backsubstitution process within logic block 760 or recursive back substitution module 604, which reduces the required number of computation cycles for the parity vector P by at least one half of the required number if blocklevel parallelization was not used. To implement this parallelization, logic block 760 (for example) may use M XOR components of XOR array 705 and M other XOR components of XOR array 705 to compute EQ. 15 and EQ. 16, respectively.
In some embodiments, the recursive back substitution module 604 may compute the respective parity vector blocks or entries in EQS. 15 and 16 in parallel. In one embodiment, one parity vector entry or block in the parity vector P may be computed in one clock cycle of the FPGA or ASIC. Note that the size of each parity vector block or entry may be equal to the size of the circulant Z, because block serial LDPC encoder 700 is configured to operate on each circulant individually. In other embodiments, a number 1 parity vector entries or blocks may be computed in one clock cycle of the FPGA or ASIC. That is, multiple recursions of EQ. 15 and/or EQ. 16 may be carried out in a single clock cycle. However, if this parallelization is carried out, the length of the clock cycle may increase by, for example, a factor of
In another embodiment, logic block 760 can implement a different accumulation process to compute the entries of the parity vector P. First, p_{1 }may be computed by recursive back substitution module 604 using p_{0} ^{c }and x_{0 }(in EQ. 10). The rest of the entries of the parity vector P are then computed by logic block 760 or recursive back substitution module 604 using the recursion equations EQ. 17 and EQ 18:
p _{i} =p _{i−1} +x _{i−1},2≦i≦j (EQ. 17)
p _{j} =p _{0} +p _{j1} +x _{j1} (EQ. 18)
Overall, using the update mechanism and the recursion equations derived from EQS. 1013, in some embodiments, entries of the parity vector P and entries of the matrixvector product X may be computed in parallel by recursive back substitution module 604 (
Output unit 707 produces codeword 770 by processing the outputs produced by logic block 760, i.e., P, and, the outer systematic codeword 720, i.e., D (given by U and P_{1}). In certain embodiments, outer systematic codeword is a BCH or RS codeword, similar to those contained in segments 401 and 402 of codeword 400 in
Assuming the number of circulants in the data portion A of the parity check matrix H to be N_{cd}, the size of the circulant to be Z, the number of block rows in matrix H to be N_{b}, and the size of the XOR array to be M, the number of cycles required for encoding, referred to by the symbol N_{e}, may be given by:
where ┌x┐ denotes the mathematical operation of computing the ceiling of x, i.e., the closest integer that is greater than or equal to x. Note that M may be referred to as the level of encoder parallelization.
During typical operation, a message vector U (810) may be input into input memory buffer control unit 803. Input memory buffer control unit 803 may then store message vector 810 into input memory buffer 801. BCH encoder 802 computes the BCH parity segment of codeword 820 based on message vector 810 obtained from input memory buffer 801. This parity segment may then be stored in input memory buffer 801, which may be controlled by input memory buffer control unit 803. Input memory buffer 801 may then contain all of the information of a BCH outer codeword, i.e., U and P_{1}. In some embodiments, the computation of the BCH parity segment of codeword 820 proceeds in parallel to the computation of the LDPC parity portion of codeword 820—i.e., BCH encoder 802 and LDPC encoder 804 can operate in parallel. BCH encoder 802 and LDPC encoder 804 can both read from input memory buffer 801 to obtain the value of message vector 810, and can both generate their respective parity vectors from message vector 810 simultaneously.
BCH encoder 802 and LDPC encoder 804 are capable of operating on the input message vector 810 independently. As previously described, one of the reasons for this capability is that BCH encoder 802 is a systematic code encoder, and therefore BCH encoder 802 produces a BCH outer codeword that includes message vector 810. In particular, BCH encoder 802 can generate a BCH parity vector and can concatenate the BCH parity vector to message vector 810. Because part of the outer codeword provided to LDPC encoder 804 includes the message vector 810, LDPC encoder 804 does not need to wait for BCH encoder 802 to produce the outer codeword before starting operation, and can instead begin immediately to encode message vector 810 stored in input memory buffer 801.
LDPC encoder 804 can operate on the outer codeword vector D. LDPC encoder 804 may generate the LDPC code bits using EQ. 6 (AD=X). For example, assuming a parity check matrix 410 in
In one implementation, output unit 805 produces codeword 820 by concatenating the message vector U and the BCH parity portion P_{1 }as obtained from input memory buffer 801, with the LDPC parity portion P_{2}=P, which are all parts of the codeword 820. In this exemplary embodiment, the implementation may include computational units typically found in FPGAs or ASICs.
In some embodiments, LDPC encoding computation unit 905 may have the features and functionalities of LDPC encoder 600 in
During typical operation, message vector U (910) may be input into input memory buffer control unit 902. BCH encoding computation unit 903 computes the BCH parity portion of codeword 980. In one implementation, BCH encoding control unit 904 controls the operation of BCH encoding computation unit 903. BCH parity portion of codeword 980 may then be stored in input memory buffer 901, which may be controlled by input memory buffer control unit 902. In some embodiments, the computation of the BCH parity portion of codeword 980 proceeds in parallel to the computation of the LDPC portion of codeword 980
The LDPC encoding functionality of LDPC encoder 804 is embodied in BCHLDPC encoder 900 by LDPC encoding computation unit 905, LDPC encoding control unit 906, LDPC control ROM 907, X/P buffer control units 908, and X/P memory buffers 909. Any of these components may correspond to the components of block serial LDPC encoder 700 of
In one implementation, LDPC encoding control unit 906 communicates with LDPC ReadOnly Memory (ROM) 907 to effectively control LDPC encoding control unit 906. In some embodiments, LDPC control ROM 907 may store the parity check matrix associated with the LDPC code. In some embodiments, in order to enable LDPC code programmability, LDPC control ROM 907 may store the parity check matrix for different LDPC codes (e.g., of different correction capabilities, different sizes, different irregularities, etc.), and LDPC encoding control unit 906 can select one of the parity check matrices to use in encoding a current outer codeword. Thus, LDPC encoding control unit 906 effectively controls, among other things, the LDPC code profile, code rate, parity check matrix block length, number of parity check matrix block rows, and number of parity check matrix block columns. As described above, because of the circulant representation of the parity check matrices, each of the parity check matrices stored in LDPC control ROM can be stored in a compact manner. Thus, the amount of storage space needed in LDPC control ROM 907 for storing parity check matrices may advantageously be small.
LDPC encoding control unit 906 may also control LDPC encoding computation unit 905 such that the appropriate circulant of a parity check matrix is being utilized at any given time. LDPC encoding control unit 906, for example, may control LDPC encoding computation unit 905 based on the size of the data portion A and the size of the BCH parity portion B of the LDPC code's parity check matrix. In these embodiments, LDPC encoding control unit 906 may embody the control functions described above in connection with block selector 702 and data selector 703 of
BCHLDPC encoder 900 can include only two memory buffers, as opposed to three in other BCHLDPC encoder implementations, such as the serial BCHLDPC encoder 500 in
Computation of the entries of the X vector in the LDPC codeword can proceed serially in computation stages 1001 for x_{0}, 1002 for x_{1 } 1003 for x_{2}, . . . , 1005 for x_{Nb2}, and 1006 for x_{Nb1}. N_{b }is the number of block rows in the parity check matrix that correspond to the data portion A. Note that these entries include only partial matrixvector products, as the BCH parity segment has not been considered. Computation of the first entry, p_{0}, in the parity vector P can proceed in parallel (with a one block timedelay) to the computation of the entries of the X vector in stages 1010, 1012, . . . , 1014, and 1016. The first entry, p_{0}, may be computed based on the sum of all of the entries of X, i.e., sumX. Thus, stages 1010, 1012, etc. correspond to the retrieveaddstore update mechanism that computes the sum of the entries of X as these entries are made available. For example, the computation performed at stage 1012 can involve adding the M bits of the second entry of X (as computed in stage 1002) with the M bits of the first entry of X (as previously computed in stage 1001). The sumX computations performed in stages 1010, 1012, . . . , 1014, however, does not produce the complete sumX value, as the BCH parity segment has not been considered.
Computation of the BCH parity vector proceeds in parallel with LDPC encoding in stage 1004. Note that, in the illustrated operating scenario, all of the blocks in X (for the message segment of the codeword) may be computed while BCH encoding is performed is stage 1004. Similarly, most of the sumX computation can be completed in this time. These computations may not need any of the parity bits computed in stage 1004 to operate, and therefore the parallel nature of the computation may drastically decrease the latency for the LDPCBCH encoding.
Once BCH encoding in stage 1004 is complete, LDPC encoding can begin processing the BCH parity portion of its parity check matrix. The parity portion processing of the LDPC encoding can proceed in stage 1007. During stage 1007, all of the X entries computed in stages 1001, . . . , 1006 may be updated to reflect the values of the BCH parity segment. Thus, once stage 1007 is complete, all of the entries in the matrixvector product X may be completely computed. Stage 1009 is a transition stage which marks the point in time at which the sumX computation has been completed. During stage 1009, any values that are needed in the back substitution operation to obtain parity vector P may be computed. For example, the result of the sumX computation may be updated based on the BCH parity segment, and can be used to obtain the value of p_{0}, as specified in EQ. 14. Also, if EQS. 15 and 16 are used for the recursion, stage 1016 may additionally involve the computation of p_{q1}, as specified by in EQ. 13. Note that stages 1007 and 1009 may proceed concurrently. This may be beneficial for minimizing latency, as both the entries of X (as completed in stage 1007) and the initial values for the recursion (e.g., p_{0 }and p_{q1}, as computed in stage 1009) may be needed before the back substitution operation can begin in stage 1008. Stage 1008 is the recursive backsubstitution stage which results in the generation of the parity vector P, and subsequently, the codeword C.
When all the computations are complete, the BCHLDPC codeword is generated. In the exemplary embodiments of
Referring now to
Referring now to
The HDD 1100 may communicate with a host device (not shown) such as a computer, mobile computing devices such as personal digital assistants, cellular phones, media or MP3 players and the like, and/or other devices via one or more wired or wireless communication links 1108. The HDD 1100 may be connected to memory 1109 such as random access memory (RAM), nonvolatile memory such as flash memory, read only memory (ROM) and/or other suitable electronic data storage.
Referring now to
The DVD drive 1210 may communicate with an output device (not shown) such as a computer, television or other device via one or more wired or wireless communication links 1217. The DVD drive 1210 may communicate with mass data storage 1218 that stores data in a nonvolatile manner. The mass data storage 1218 may include a hard disk drive (HDD). The HDD may have the configuration shown in
Referring now to
The HDTV 1320 may communicate with mass data storage 1327 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices for example hard disk drives and/or DVD drives. At least one HDD may have the configuration shown in
Referring now to
The present invention may also be implemented in other control systems 1440 of the vehicle 1430. The control system 1440 may likewise receive signals from input sensors 1442 and/or output control signals to one or more output devices 1444. In some implementations, the control system 1440 may be part of an antilock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc and the like. Still other implementations are contemplated.
Powertrain control system 1432 may communicate with mass data storage 1446 that stores data in a nonvolatile manner. The mass data storage 1446 may include optical and/or magnetic storage devices for example hard disk drives and/or DVD drives. At least one HDD may have the configuration shown in
Referring now to
The cellular phone 1550 may communicate with mass data storage 1564 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices for example hard disk drives and/or DVD drives. At least one HDD may have the configuration shown in
Referring now to
Set top box 1680 may communicate with mass data storage 1690 that stores data in a nonvolatile manner. The mass data storage 1690 may include optical and/or magnetic storage devices for example hard disk drives and/or DVD drives. At least one HDD may have the configuration shown in
Referring now to
Media player 1700 may communicate with mass data storage 1710 that stores data such as compressed audio and/or video content in a nonvolatile manner. In some implementations, the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices for example hard disk drives and/or DVD drives. At least one HDD may have the configuration shown in
The foregoing describes systems and methods for lowlatency programmable encoders which use lowdensity parity check (LDPC) codes in combination with an outer systematic code, for example a BoseChaudhuriHocquenghem (BCH) code. Those skilled in the art will appreciate that the invention can be practiced by other than the described embodiments, which are presented for the purpose of illustration rather than of limitation.
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