TWI492079B - Method and apparatus for reducing random yield defects - Google Patents

Description

Method and device for reducing random yield defects

The present invention relates to a method and apparatus for reducing random yield defects, and more particularly to a method and apparatus for reducing random yield defects by wire spreading and wire widening.

The most common failure modes for random yield defects are open and short circuits, which are caused by accidentally falling particles in the semiconductor process. Although the semiconductor clean room or machine has removed the fine particles exceeding the specification as much as possible, when the nano-scale advanced process is introduced, the circuit will still be ineffective due to improper adhesion of the fine particles to the integrated circuit chip.

In general, if the non-conductive particles are dropped directly in the middle of a predetermined path of a metal line, it is likely to cause an open circuit (or an open circuit), and the probability of occurrence occurs depending on the position and diameter of the non-conductive particles. And set. If the conductive particles fall into the gap between the predetermined paths of the two metal lines, it is likely to cause a short circuit, and the probability of occurrence also depends on the position of the conductive particles and the diameter thereof. If the semiconductor clean room or machine is required to improve its cleanliness, it seems that the above-mentioned open circuit and short circuit failure problems can be improved, but it will inevitably lead to a substantial increase in manufacturing costs. If the potential generation of such problems can be considered in the circuit design process, the probability of subsequent random yield defects can be effectively reduced, and even the cost of the cleanliness requirements of the semiconductor manufacturing industry can be reduced.

In order to consider the random yield defect in advance in the circuit design process, a Critical Area Analysis (CAA) method has been proposed, which can be post-routing through the analysis in the circuit design flow. Layout) of the line pattern, and effectively predict the probability of occurrence of the above random yield defect. For a line that is likely to create an open or short circuit, the critical area of the open or short circuit can be obtained according to the method. In order to reduce the short-circuit critical area obtained by the analysis, a correction step of the line extension is often adopted to reduce the effective existence range of the short-circuit caused by the random particles. Similarly, in order to reduce the critical area of the open circuit obtained by the analysis, a correction step of line widening is often adopted to reduce the effective existence range of the open circuit caused by the random particles.

Figure 1 is a schematic diagram of a conventional step of extending the line to reduce the critical area of the short circuit. In the figure, the line 11 and the line 12 are adjacent to each other, so if the random conductive particles of appropriate diameter fall within the short-circuit critical area CAs, the line 11 will short-circuit with the line 12. Therefore, one of the line segments 111 of the line 11 can be extended to the left, whereby the short circuit critical area CAs can be reduced. The extended line segment 111' of the line 11 obviously increases the path length, i.e., the open critical area CAo will increase relative to the path length.

When the line extension step is performed, a line widening correction step is then taken to further reduce the critical area of the open circuit. However, when the line length of the extended line segment 111' is widened, it is likely to increase the critical area of the short circuit again. Therefore, the minimization method of the traditional critical area successively performs the steps of line extension and line widening, and obviously cannot obtain an optimal balance point for the critical area of the open circuit and the critical area of the short circuit, but needs to go through multiple errors. And trial and error can have better results.

In view of this, the Electronic Design Automation industry needs an automatic and efficient method to reduce random yield defects in order to solve the problems encountered in current circuit design.

It is an object of the present invention to provide a method and apparatus for reducing random yield defects.

According to an embodiment of the method for reducing random yield defects, the method comprises the steps of: providing a design layout and a plurality of weight numbers; and performing critical area analysis according to the design layout to obtain an open critical area and a short circuit critical area of each line to be corrected; Multiplying the open critical area and the short-circuit critical area of each of the to-corrected lines by a weight number and summing them to obtain a total value; and simultaneously adjusting the line extension and the line widening for each of the lines to be corrected The summed value is changed to obtain an optimized correction combination of the line extension and the line widening of the lines to be corrected.

The apparatus for reducing random yield defects of the present embodiment further includes a step of correcting the line extension and line widening of the lines to be corrected in accordance with the obtained optimization correction combination.

Another apparatus for reducing random yield defects includes: a critical area analysis unit that performs a critical area analysis of a design layout of a wafer to obtain an open critical area and a short circuit critical area of a plurality of lines to be corrected, respectively; The area summing unit multiplies the critical area of the open circuit and the critical area of the short circuit of each line to be corrected by a weight number and adds a total value; a line adjusting unit simultaneously performs line extension and line for each line to be corrected a different adjustment amount of the widening, wherein the critical area analysis unit receives the different adjustment amounts and sequentially calculates the open critical area and the short circuit critical area of each of the to-corrected lines, and the critical area summing unit accepts the adjustment The open critical area and the short circuit critical area are sequentially obtained by a plurality of adjusted total values; and a comparison unit compares the plurality of adjusted total values to determine line extension and line widening of each of the lines to be corrected The best combination of adjustments.

The apparatus for reducing the random yield defect of the embodiment further includes a correction unit for performing correction of the optimum adjustment amount combination of the line extension and the line widening for each of the lines to be corrected.

The invention discussed herein is a method and apparatus for reducing random yield defects. In order to thoroughly understand the present invention, detailed steps and compositions will be set forth in the following description. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the circuit design. On the other hand, well-known components or steps are not described in detail to avoid unnecessarily limiting the invention. The preferred embodiments of the present invention are described in detail below, but the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited by the scope of the following patents. .

2 is a flow diagram of a method of reducing random yield defects in accordance with an embodiment of the present invention. After the placement and routing steps of the electronic design automation, the designer will obtain an IC design layout as shown in step S21. In addition, the wafer manufacturer needs to provide a pair of weights to give different or the same weighting values W _open and W _{short for} the occurrence of open and short circuits in random yield defects. The pair of weights may be based on the ratio of the presence of conductive microparticles and non-conductive microparticles at the wafer fabrication facility, or the relative impact of process yield loss.

Then, as shown in step S22, the critical area analysis is performed according to the design layout to obtain the open critical area and the short circuit critical area of each line to be corrected. In order to reduce the amount of calculation, the critical area analysis can be a simplified analysis process, that is, a fast analysis mode is established to estimate the critical area of the open circuit and the critical area of the short circuit. The open critical area CAo and the short circuit critical area CAs of each of the lines to be corrected are respectively multiplied by the weight number and added to obtain a total value CA, as shown in step S23.

As shown in step S24, a combination of different adjustment amounts of line extension and line widening is simultaneously performed for each of the to-be-corrected lines, for example, changing the lateral direction (vertical line diameter direction) extension amount WS_amount of the local line and changing the line of the local line. Wide WW_amount. As shown in step S25, if the adjustment amount does not reach the limit, for example, the adjustment amount does not exceed the limit of the Design Rule Check (DRC), then return to step 22 and step 23 to perform the combination of the above different adjustment amounts. Area analysis (open critical area CAo and short circuit critical area CAs) and calculation of the total value CA. If the adjustment amount has reached the limit, step S26 is performed to compare the calculated total value CA, thereby obtaining an optimized correction combination of the line extension and the line widening of the lines to be corrected. For example, the smallest sum total value CA is found, and the adjustment of the line extension and the line widening corresponding to the minimum total value CA is used as the optimal correction combination of the to-corrected line. Finally, the line extension and line widening correction of the lines to be corrected may be performed according to the obtained optimization correction combination, as shown in step S27.

According to the above steps, the total value CA can be expressed by the following formula:

CA=W _short ×CAs(WW_amount,WS_amount)+W _open ×CAo(WW_amount,WS_amount) (1)

CAs (WW_amount, WS_amount) represent CAs as functions of WW_amount and WS_amount; CAo(WW_amount, WS_amount) represents CAo as a function of WW_amount and WS_amount.

The CA of the above formula (1) is also a function of WW_amount and WS_amount, so the optimal value of CA can be obtained by changing WW_amount and WS_amount. The optimal value of this embodiment is the minimum value, that is, the weight ratio of the open circuit and the short circuit in the random yield defect is considered, and the sum total value of the critical area of the open circuit and the critical area of the short circuit is obtained.

3 is a schematic diagram of line correction for line extension and line widening in accordance with an embodiment of the present invention. In the figure, the line 31 and the line 32 are adjacent to each other. Therefore, if the random conductive particles of a proper diameter fall within the short-circuit critical area 33, the line 31 will be short-circuited with the line 32. Therefore, one line segment 311 of the line 31 can be extended to the left, whereby the short circuit critical area CAs can be reduced. The extended line segment 311' of the line 31 obviously increases the path length, that is, the open critical area CAo is relatively increased due to the length of the path, so it is necessary to simultaneously consider the correction of the line widening. From the steps shown in FIG. 2 and the calculated value of the optimization formula (1), the extension WS_amount of the line segment 311 protruding to the left by S can be obtained, and the portion of the extended line segment 311' needs to be increased by the original line width W. WW_amount is W'. The combination of the extension WS_amount and the line width WW_amount, S and W', is an optimized correction combination that allows circuit designers and wafer fabs to get the most correct corrections.

4 is a block diagram of a device for reducing random yield defects in accordance with an embodiment of the present invention. The device 40 for reducing random yield defects includes a critical area analyzing unit 41, a critical area summing unit 42, a line adjusting unit 43, a comparing unit 44, and a correcting unit 45. The critical area analysis unit 41 performs a critical area analysis of the design layout of a wafer, and can respectively obtain an open critical area CAo and a short circuit critical area CAs of a plurality of lines to be corrected. Then, the critical area summing unit 42 multiplies the open critical area CAo and the short circuit critical area CAs of each of the to-corrected lines by the weight numbers W _open and W _short , respectively, and adds a total value CA. The line adjusting unit changes the different adjustment amounts of the line extension and the line widening for each of the lines to be corrected, and then the critical area analyzing unit 41 accepts the different adjustment amounts, and sequentially calculates the adjusted lines to be corrected. The open critical area CAo ₁ , ... CAo _N and the short circuit critical area CAs ₁ , ... CAs _N , and the critical area adding unit 42 accepts the adjusted open critical areas CAo ₁ , ... CAo _N and the short circuit critical area CAs ₁ , ... CAs _N sequentially obtains a plurality of adjusted total values CA ₁ , ... CA _N . The comparing unit 44 compares the magnitudes of the plurality of adjusted summed values CA ₁ , . . . , CA _N to determine the optimal adjustment amount combinations CAo _X and CAs _{X for} each of the line extension and line widening of the line to be corrected. Then, the correction unit 45 performs a correction of the optimum adjustment amount combinations CAo _X and CAs _X corresponding to the line extension and the line widening for each of the lines to be corrected. In this way, the line to be corrected will be adjusted with the best line extension and line widening value, and the problem of random yield defects will be greatly reduced. Obviously, the device 40 can automatically and efficiently reduce the incidence of random yield defects, and can solve the related problems encountered in current circuit design.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

11. . . line

12. . . line

31. . . line

32. . . line

33. . . Short circuit critical area

40. . . Device

41. . . Critical area analysis unit

42. . . Critical area summing unit

43. . . Line adjustment unit

44. . . Comparison unit

45. . . Correction unit

111. . . Line segment

111'. . . Extended line segment

311. . . Line segment

311'. . . Extended line segment

CAo. . . Open circuit critical area

CAs. . . Short circuit critical area

1 is a schematic diagram of a conventional step of taking a line extension to reduce a critical area of a short circuit;

2 is a flow chart of a method for reducing random yield defects according to an embodiment of the present invention;

3 is a schematic diagram of line correction for line extension and line widening in accordance with an embodiment of the present invention;

4 is a block diagram of a device for reducing random yield defects in accordance with an embodiment of the present invention.

S21～S27. . . step

Claims (16)

A method for reducing random yield defects includes: performing critical area analysis according to a design layout, and obtaining an open critical area and a short circuit critical area of each line to be corrected; and an open critical area and a short circuit criticality of each of the lines to be corrected The areas are respectively calculated and summed to obtain a total value; and the different adjustments are made for each line to be corrected and the line extension and the line widening are simultaneously changed, thereby obtaining the line extension and the line of the line to be corrected. A widened optimization correction combination. According to the method of claim 1, the method further comprises the step of performing line extension and line widening correction for each of the lines to be corrected in accordance with the obtained optimized correction combination. According to the method of claim 1, wherein the minimum value of the total value is found by simultaneously adjusting the line extension and the line widening for each line to be corrected, and the minimum value of the added value corresponds to the adjustment amount of the line extension. And the adjustment amount of the line widening is an optimized correction combination of each of the lines to be corrected. According to the method of claim 1, the method further comprises the step of providing a plurality of weight numbers, wherein the open critical area and the short circuit critical area of each of the lines to be corrected are multiplied by a weight number and added to obtain the total value. The method of claim 4, wherein the plurality of weight numbers determine a value based on an occurrence probability of an open circuit and a short circuit in the random yield defect. The method of claim 4, wherein the plurality of weights are determined according to a ratio of the presence of conductive fine particles and non-conductive fine particles of the wafer fabrication facility. According to the method of claim 1, wherein the design layout is a post-winding layout. According to the method of claim 1, wherein the critical area analysis is a fast analysis mode for estimating an open circuit critical area and a short circuit critical area. A device for reducing random yield defects, comprising: a critical area analysis unit, performing critical area analysis of a design layout of a chip to obtain an open critical area and a short circuit critical area of a plurality of lines to be corrected respectively; a critical area summing unit Calculating and summing the critical area of the open circuit and the critical area of the short circuit of each line to be corrected to obtain a total value; a line adjusting unit performs different adjustments of line extension and line widening for each line to be corrected, The critical area analysis unit receives the different adjustment amounts and sequentially calculates the open critical area and the short circuit critical area of each of the to-corrected lines, and the critical area adding unit accepts the adjusted open critical area and short circuit. The critical area sequentially obtains a plurality of adjusted sum values; and a comparing unit compares the plurality of adjusted sum values to determine an optimal adjustment amount combination of line extension and line widening of each line to be corrected. The apparatus of claim 9, further comprising a correction unit that performs corrections for the respective adjustments of the line extension and line widening for each of the lines to be corrected. The apparatus of claim 9, wherein the critical area summing unit accepts a plurality of weight numbers, and multiplies each of the open critical area and the short circuit critical area of each line to be corrected by a weight number and adds the total value. . The apparatus of claim 9, wherein the comparing unit compares the plurality of adjusted sum values to find a minimum value of the summed values, the minimum value of the summed values corresponding to the line extension adjustment amount and the line The adjustment of the widening is a combination of optimization corrections for each of the lines to be corrected. The apparatus of claim 11, wherein the plurality of weights determine a value according to an occurrence probability of an open circuit and a short circuit in the random yield defect. The device of claim 11, wherein the plurality of weights are determined according to a ratio of the presence of conductive fine particles and non-conductive fine particles of the wafer fabrication facility. The device of claim 11, wherein the design layout is a post-wrap layout. The apparatus of claim 11, wherein the critical area analysis is a fast analysis mode for estimating an open circuit critical area and a short circuit critical area.