TWI491040B - Active component array substrate and manufacturing method thereof - Google Patents

Description

Active device array substrate and manufacturing method thereof

The present invention relates to an active device array substrate and a method of fabricating the same.

The Electro-Phoretic Display (EPD) was originally developed in the 1970s and features a charged ball. One side of the ball is white and the other side is black. When the electric field changes, the ball will rotate up and down to present a different color. The second generation of electrophoretic displays was developed in the 1990s and features microcapsules instead of conventional pellets, and filled with colored oil and charged white particles. The white particles are moved up or down by the control of the external electric field, wherein the white particles appear white when they are up (close to the reader's direction), and when the white particles are down (away from the reader) The color of the oil.

In general, electrophoretic displays are mostly made of glass as the material of their active device array substrate. Although such an electrophoretic display has a preferable hardness, the weight is too heavy to be carried, and it is not resistant to collision and is liable to cause chipping.

Recently, the industry has introduced an electrophoretic display using a plastic material as an active device array substrate material. The electrophoretic display itself has a certain degree of flexibility and can be used to replace conventional paper or advertising billboards. Since the material of the active device array substrate is plastic, in order to facilitate the process, the manufacturer needs to fix the active device array substrate on the glass carrier to be suitable for the existing machine. However, since the thermal expansion coefficient of the plastic and the thermal expansion coefficient of the glass carrier plate are even different from the thermal expansion coefficients of the inorganic dielectric layer (for example, the gate dielectric layer and the protective layer) on the active device array substrate, during the thermal process It is easy to cause stress accumulation in the active device array substrate and the glass carrier, and the active device array substrate and the glass carrier plate are deformed to cause poor adsorption of the bumper or the machine.

One aspect of the present invention provides an active device array substrate having a thin dielectric layer in a light transmissive region, thereby reducing the active device array substrate and the glass carrier in the process while providing sufficient protection. The amount of deformation.

According to an embodiment of the invention, an active device array substrate includes a flexible substrate, a gate, a dielectric layer, a channel layer, a source, a drain, and a pixel electrode. A transistor region and a light transmitting region are defined on the flexible substrate. The transistor region is adjacent to the light transmitting region. The gate is located on a flexible substrate in the transistor region. The dielectric layer covers the gate and the flexible substrate. A portion of the dielectric layer above the gate has a first thickness. A portion of the dielectric layer on the flexible substrate at the center of the light transmissive region has a second thickness. The second thickness is less than the first thickness. The channel layer, the source and the drain are both on the dielectric layer of the transistor region. The channel layer is above the gate. The source and the drain are located on both sides of the channel layer and are electrically connected to the channel layer. The pixel electrode is located on the dielectric layer of the light transmissive region. This pixel electrode is electrically connected to the drain.

In one or more embodiments of the present invention, the material of the flexible substrate comprises plastic.

In one or more embodiments of the present invention, the material of the flexible substrate comprises polyimide (PI), polyethylene terephthalate (PET), poly 2,6-naphthalene Polyethylene Naphthalate (PEN) or any combination of the above.

In one or more embodiments of the present invention, the material of the dielectric layer comprises tantalum nitride, cerium oxide, cerium oxynitride or any combination thereof.

In one or more embodiments of the present invention, the active device array substrate further includes a storage capacitor. The storage capacitor is located on a flexible substrate, and the storage capacitor includes a lower electrode, a capacitor dielectric layer and an upper electrode.

In one or more embodiments of the present invention, the capacitor dielectric layer is a part of a dielectric layer.

In one or more embodiments of the present invention, the active device array substrate further includes a connection pad. The connection pad is located on a flexible substrate, and the connection pad comprises a lower connection pad and an upper connection pad.

In one or more embodiments of the present invention, the material of the channel layer includes an amorphous germanium, a germanium germanium, an oxide semiconductor, or any combination thereof.

In one or more embodiments of the present invention, the active device array substrate further includes a protective layer. This protective layer covers the channel layer, the source and the drain.

In one or more embodiments of the present invention, the material of the pixel electrode includes indium tin oxide, indium zinc oxide, aluminum zinc oxide, or any combination thereof.

In one or more embodiments of the present invention, the active device array substrate further includes a metal oxide dielectric layer. The metal oxide dielectric layer is between the dielectric layer and the flexible substrate.

In one or more embodiments of the present invention, the metal oxide dielectric layer is further disposed between the dielectric layer and the gate.

In one or more embodiments of the present invention, the material of the metal oxide dielectric layer comprises indium oxide, zinc oxide, gallium oxide, or any combination thereof.

Another aspect of the present invention provides a method of manufacturing the above-described active device array substrate.

According to an embodiment of the present invention, a method for manufacturing an active device array substrate includes the following steps (it should be understood that the steps mentioned in the present embodiment can be adjusted according to actual needs unless otherwise specified. Its order can be executed simultaneously or partially simultaneously):

(1) A flexible substrate is provided, on which a transistor region and a light transmitting region are defined.

(2) Forming a gate on the transistor region of the flexible substrate.

(3) Forming a dielectric layer and a semiconductor layer in sequence, the dielectric layer and the semiconductor layer covering the gate and the flexible substrate.

(4) removing a portion of the semiconductor layer to form a channel layer over the gate, and simultaneously removing a portion of the thickness of the dielectric layer located in the light-transmitting region, so that a portion of the dielectric layer above the gate has a first thickness, located at A portion of the dielectric layer on the flexible substrate at the center of the light transmissive region has a second thickness, wherein the second thickness is less than the first thickness.

(5) Forming source and drain electrodes respectively on both sides of the channel layer, and electrically connecting the channel layers respectively.

(6) Forming a protective layer covering the channel layer, the source, the drain, and the dielectric layer.

(7) Forming a transistor contact hole in the protective layer to expose the drain, respectively, and simultaneously removing the protective layer located in the light-transmitting region to expose the dielectric layer located in the light-transmitting region.

(8) A pixel electrode is formed on the dielectric layer located in the light-transmitting region, and the pixel electrode is electrically connected to the drain through the contact hole of the transistor.

In one or more embodiments of the present invention, the material of the flexible substrate comprises plastic.

In one or more embodiments of the present invention, the material of the flexible substrate comprises polyimide (PI), polyethylene terephthalate (PET), poly 2,6-naphthalene Polyethylene Naphthalate (PEN) or any combination of the above.

In one or more embodiments of the present invention, the material of the dielectric layer comprises tantalum nitride, cerium oxide, cerium oxynitride or any combination thereof.

In one or more embodiments of the present invention, the above step (2) further comprises:

(2.1) Form the lower electrode on the flexible substrate.

In one or more embodiments of the present invention, the above step (4) comprises:

(4.1) A photoresist layer is formed to cover the semiconductor layer.

(4.2) The photoresist layer is patterned by a halftone mask process to form a patterned photoresist layer.

(4.3) The patterned photoresist layer is used as a mask to remove the exposed semiconductor layer in the light-transmitting region while removing a portion of the photoresist layer above the lower electrode.

(4.4) With the remaining patterned photoresist layer as a mask, a portion of the dielectric layer of the light-transmitting region is removed, so that the dielectric layer of the light-transmitting region has a second thickness while removing a portion of the semiconductor layer on the lower electrode.

In one or more embodiments of the present invention, the above step (5) further comprises:

(5.1) The upper electrode is formed on the dielectric layer and above the lower electrode.

In one or more embodiments of the present invention, the above step (2) further comprises:

(2.2) Form the lower connection pad on the flexible substrate.

In one or more embodiments of the present invention, the above step (8) further includes:

(8.1) Form the upper connection pad on the lower connection pad.

According to another embodiment of the present invention, a method for manufacturing an active device array substrate includes the following steps (it should be understood that the steps mentioned in the present embodiment can be implemented according to actual needs unless otherwise specified. Adjust the order before and after, even at the same time or partially):

(a) A flexible substrate is provided, on which a transistor region and a light-transmissive region are defined.

(b) Forming a gate on the transistor region of the flexible substrate.

(c) Forming a dielectric layer covering the gate and the flexible substrate.

(d) forming a channel layer, a source and a drain on the dielectric layer, the source and the drain are respectively formed on both sides of the channel layer, and are electrically connected to the channel layer, respectively.

(e) Forming a protective layer covering the channel layer, source, drain and dielectric layers.

(f) forming a transistor contact hole in the protective layer to expose the drain, respectively, and simultaneously removing the protective layer located in the transparent region and the dielectric layer in the transparent region to provide a portion of the dielectric layer above the gate A portion of the dielectric layer having a first thickness on the flexible substrate at the center of the light transmissive region has a second thickness, wherein the second thickness is less than the first thickness.

(g) forming a pixel electrode on the dielectric layer located in the light-transmitting region, the pixel electrode being electrically connected to the drain through the contact hole of the transistor.

In one or more embodiments of the present invention, the method for fabricating the active device array substrate further includes: (h) forming a metal oxide dielectric layer over the gate after forming the gate and before forming the dielectric layer And a flexible substrate such that after forming the dielectric layer, the metal oxide dielectric layer is between the gate and the flexible substrate and the dielectric layer.

In one or more embodiments of the present invention, the material of the metal oxide dielectric layer comprises indium oxide, zinc oxide, gallium oxide, or any combination thereof.

In one or more embodiments of the present invention, the method for fabricating the active device array substrate further includes: (i) forming a metal oxide dielectric layer over the flexible substrate before forming the gate, so that after the gate is formed, A metal oxide dielectric layer is between the gate and the flexible substrate.

In one or more embodiments of the present invention, the step (b) includes: (b1) forming a first conductive layer covering the metal oxide dielectric layer; (b2) removing the first conductive layer located in the light transmitting region, and And removing a portion of the thickness of the metal oxide dielectric layer located in the transparent region; and (b3) removing the first conductive layer located in the transistor region to form a gate.

In one or more embodiments of the present invention, the material of the metal oxide dielectric layer comprises indium oxide, zinc oxide, gallium oxide, or any combination thereof.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

First embodiment

1 to 9 are cross-sectional views showing a manufacturing process of an active device array substrate according to a first embodiment of the present invention. Figure 46 is a top plan view showing an active device array substrate according to the first, second, third and fourth embodiments of the present invention. In Figures 1-9, the II area shows the section along line I of Figure 46, the II-II area shows the section along line II of Figure 46, and the III-III area shows the line along section 46. Section III. The top view design of the active device array substrate of the present invention is for illustrative purposes only, and is not limited to the above-described drawings, and those skilled in the art can appropriately change the design according to requirements.

Please refer to Figure 1 first. As shown in the figure, the manufacturer can provide the flexible substrate 110 at this time. The flexible substrate 110 preferably has flexibility, and the display panel which is subsequently fabricated is also flexible. The flexible substrate 110 may be defined with an adjacent transistor region 112, a light transmitting region 113, a capacitor region 114 and a connection pad region 116. In one or more embodiments of the present invention, in order to facilitate the subsequent process operation, the manufacturer may first set the flexible substrate 110 on the glass carrier to perform the process. After the active device array substrate is manufactured, the flexible substrate 110 is removed from the glass. The carrier plate was peeled off and removed. In this embodiment, the material of the flexible substrate 110 may include plastics, such as polyimide (PI), polyethylene terephthalate (PET), poly 2,6-naphthalene. Polyethylene Naphthalate (PEN) or any combination of the above, or other copolymer plastic materials. It should be understood that the materials of the soft substrate 110 are merely illustrative and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains, the material of the flexible substrate 110 should be elastically selected according to actual needs.

Then, the manufacturer can form a patterned first conductive layer on the flexible substrate 110, for example, first forming a first conductive layer, and then patterning the first conductive layer by a lithography and etching process, thereby using the soft substrate. Forming a patterned first conductive layer on 110, at least comprising forming a gate 122 on the transistor region 112, and patterning the first conductive layer further includes a gate line connecting the gate 122, and a capacitance region 114 of the flexible substrate 110 A lower electrode 124 and a lower connection pad 126 are formed on the connection pad region 116, respectively. In this embodiment, the material of the first conductive layer (ie, the gate 122, the lower electrode 124, and the lower connection pad 126) may include any of the foregoing, such as titanium, molybdenum, chromium, niobium, aluminum, copper, silver, gold, and the like. The combination or alloy may be formed by physical vapor deposition, such as sputtering or chemical vapor deposition, and the method of patterning the first conductive layer may be lithography and etching.

Please refer to Figure 2 below. As shown, the manufacturer can sequentially form the dielectric layer 130, the semiconductor layer 140, and the ohmic contact layer 150. The dielectric layer 130, the semiconductor layer 140, and the ohmic contact layer 150 cover the gate 122, the lower electrode 124, the lower connection pad 126, and the flexible substrate 110. The material of the dielectric layer 130 may include tantalum nitride, hafnium oxide, tantalum oxynitride or any combination thereof. The material of the semiconductor layer 140 may include amorphous germanium, a germanium oxide, an oxide semiconductor, or any combination thereof. The material of the ohmic contact layer 150 may include an N-type doped amorphous germanium or a P-type doped amorphous germanium or the like.

Then, a manufacturer may form a photoresist layer on the ohmic contact layer 150, the photoresist layer covering the ohmic contact layer 150 and the semiconductor layer 140 under the ohmic contact layer 150. Next, the manufacturer can pattern the photoresist layer by a halftone mask process to form a patterned photoresist layer. The patterned photoresist layer described above may include a thick photoresist layer 162 and a thin photoresist layer 164. The thick photoresist layer 162 is located above the transistor region 112 of the flexible substrate 110, and the thin photoresist layer 164 is located above the capacitor region 114 and the connection pad region 116 of the flexible substrate 110, respectively. As for the light-transmissive region 113 of the flexible substrate 110, there is no photoresist layer protection.

Please refer to Figure 3 below. As shown, the manufacturer can pattern the photoresist layer (including the thick photoresist layer 162 and the thin photoresist layer 164) as a mask to remove the exposed semiconductor layer 140 and the ohmic contact layer 150 over the transparent region 113, and A portion of the thickness of the exposed dielectric layer 130 above the light transmissive region 113 is also removed. In the present embodiment, the specific manner of removing the semiconductor layer 140, the ohmic contact layer 150 and the dielectric layer 130 may be, for example, dry etching or wet etching.

Next, referring to FIG. 4, as shown, the manufacturer can remove a portion of the photoresist layer above the lower electrode 124 and the lower connection pad 126. More specifically, the manufacturer can remove the thin photoresist layer 164 at this time while thinning the thick photoresist layer 162. In the present embodiment, the method of removing the thin photoresist layer 164 and thinning the thick photoresist layer 162 may be ashing.

Please refer to Figure 5 below. As shown, the photoresist layer (ie, the thinned photoresist layer 162 after thinning) that the manufacturer can leave at this time is used as a mask to remove a portion of the dielectric layer 130 of the transparent region 113. The dielectric layer 130 of the light transmissive region 113 has a second thickness T2 and simultaneously removes a portion of the semiconductor layer 140 and the ohmic contact layer 150 over the lower electrode 124 and the lower connection pad 126. In the present embodiment, the specific manner of removing the semiconductor layer 140, the ohmic contact layer 150 and the dielectric layer 130 may be, for example, dry etching or wet etching. In addition, after this step is completed, the manufacturer can strip the remaining patterned photoresist layer (ie, the thinned photoresist layer 162 after thinning).

In the present embodiment, the dielectric layer 130 above the light transmissive region 113 is etched in two stages. In the first stage illustrated in FIG. 3, the dielectric layer 130 above the light transmissive region 113 is initially thinned. In the second stage illustrated in FIG. 5, since the dielectric layer 130 is also etched onto the transparent region 113 when the semiconductor layer 140 and the ohmic contact layer 150 are etched, the dielectric layer above the transparent region 113 is formed. 130 will also be further thinned to a second thickness T2.

It should be understood that although the present embodiment uses a halftone mask process in the processes of FIGS. 2 to 5 in order to reduce the number of use of the mask, the present invention is not limited thereto, and those having ordinary knowledge in the technical field to which the present invention pertains Alternatively, a mask process may be used to remove a portion of the dielectric layer 130 of the transparent region 113, and another mask process may be used to remove portions of the semiconductor layer 140 and ohms above the lower electrode 124 and the lower connection pad 126. Contact layer 150.

After the process of FIG. 5, a channel layer 142 composed of a semiconductor layer 140 is formed over the gate 122, and a portion of the dielectric layer 130 above the gate 122 has a first thickness T1 at the center of the light-transmissive region 113. A portion of the dielectric layer 130 on the flexible substrate 110 has a second thickness T2. The second thickness T2 is smaller than the first thickness T1, and the ratio of the second thickness T2 to the first thickness T1 is between 0.05 and 0.95, and preferably between 0.1 and 0.8, and more preferably between Between 0.3 and 0.6. In addition, since in FIG. 4, the ashing thick photoresist layer 162 and the thin photoresist layer 164 will inevitably cause the thick photoresist layer 162 to be retracted (as indicated by the arrow S), the subsequent etching process will injure the electricity. The dielectric layer 130 above the edge of the crystal region 112 is such that the dielectric layer 130 over the edge of the transistor region 112 has a third thickness T3 that is less than the thickness of the dielectric layer 130 above the center of the transistor region 112 (eg, : First thickness T1). In addition, if the flexible substrate 110 has a metal oxide dielectric layer, the metal oxide dielectric layer may also be damaged by a subsequent etching process, so that the thickness of the metal oxide dielectric layer is different.

Please refer to Figure 6 below. As shown in the figure, the manufacturer can form a source 172 and a drain 174 on both sides of the channel layer 142 at this time, and form a data line connecting the source 172 and the upper electrode 176 on the dielectric layer 130. The upper electrode 176 is located above the lower electrode 124. The source 172 and the drain 174 are electrically connected to the channel layer 142, respectively. Specifically, the manufacturer may first form a second conductive layer over the flexible substrate 110, and the second conductive layer covers all the structures on the flexible substrate 110. Then, the manufacturer can pattern the second conductive layer, thereby forming a source 172 and a drain 174 on both sides of the channel layer 142, and forming an upper electrode 176 on the dielectric layer 130 above the lower electrode 124. In the process of patterning the second conductive layer, the manufacturer may select the ohmic contact layer 150 between the source 172 and the drain 174 to be etched down, such that the ohmic contact layer 150 is broken to form the source ohmic contact layer 152. Contact layer 154 with the drain ohms. The above embodiment is described by taking a source 172 and a drain 174 covering a portion of the channel layer 142. In a variant embodiment, the channel layer 142 may also cover part of the source 172 and the drain 174, and only need to adjust the process sequence. And using two masks to define their respective patterns, which are well known to those of ordinary skill in the art, and therefore will not be described again.

In this embodiment, the material of the second conductive layer (ie, the source 172, the drain 174, and the upper electrode 176) may include any combination of the foregoing, such as titanium, molybdenum, chromium, niobium, aluminum, copper, silver, gold, and the like. Or an alloy, which may be formed by physical vapor deposition, such as sputtering or chemical vapor deposition, and the method of patterning the second conductive layer may be lithography and etching.

After the process of FIG. 6, the gate 122, the dielectric layer 130 on the gate 122 (ie, the gate dielectric layer), the channel layer 142, the source ohmic contact layer 152, the drain ohmic contact layer 154, and the source The pole 172 and the drain 174 will constitute a thin film transistor, and the dielectric layer 130 (i.e., the capacitor dielectric layer) and the upper electrode 176 on the lower electrode 124 and the lower electrode 124 will constitute a storage capacitor. It should be understood that although the source 172 and the drain 174 disclosed in the embodiment are stacked above the channel layer 142, those skilled in the art can adjust the implementation of the thin film transistor according to actual conditions. For example, in some embodiments of the present invention, the channel layer may also be stacked above the source and the drain to form a thin film transistor.

Please refer to Figure 7 below. As shown, the manufacturer can form a protective layer 180 at this time, which covers the source 172, the channel layer 142, the drain 174, the dielectric layer 130, and the upper electrode 176. In the present embodiment, the material of the protective layer 180 may include tantalum nitride, cerium oxide, cerium oxynitride or any combination thereof.

Please refer to Figure 8 below. As shown, the manufacturer can form a transistor contact hole 182, a capacitor contact hole 184 and a connection pad contact hole 186 in the protective layer 180 to expose the drain 174, the upper electrode 176 and the lower connection pad 126, respectively. And simultaneously removing the protective layer 180 located in the transparent region 113 to expose the dielectric layer 130 located in the transparent region 113. In the present embodiment, the method of forming the transistor contact hole 182, the capacitor contact hole 184, and the connection pad contact hole 186 and removing the protective layer 180 located in the light transmitting region 113 may be a lithography and etching method.

Please refer to Figure 9 below. As shown, the manufacturer can form a pixel electrode 192 on the dielectric layer 130 on the light transmissive region 113 at this time. The pixel electrodes 192 are electrically connected to the drain electrodes 174 and the upper electrodes 176 through the transistor contact holes 182 and the capacitor contact holes 184, respectively. At the same time, the manufacturer can also form the upper connection pads 194 on the lower connection pads 126. Specifically, the manufacturer may first form a transparent conductive layer over the flexible substrate 110, and the transparent conductive layer covers all the structures on the flexible substrate 110. Next, the manufacturer can pattern the transparent conductive layer, thereby forming the pixel electrode 192 and the upper layer connection pad 194. In the present embodiment, the material of the transparent conductive layer (that is, the pixel electrode 192 and the upper layer connection pad 194) may include indium tin oxide, indium zinc oxide, aluminum zinc oxide, or any combination thereof. After the process of FIG. 9, the lower connection pad 126 and the upper connection pad 194 will constitute a connection pad which is located on the connection pad region 116 of the flexible substrate 110 for connecting an external circuit.

In the first embodiment, the dielectric layer 130 at the center of the light transmitting region 113 Since the second thickness T2 is thin, the influence of the stress accumulation of the dielectric layer 130 in the thermal process can be reduced, and the amount of deformation of the soft substrate 110 and the glass carrier of the boarding flexible substrate 110 can be further reduced. In addition, since the dielectric layer 130 is still present on the transparent region 113, the present embodiment can still provide sufficient protection for the active device array substrate. In the subsequent semiconductor process of the dielectric layer 130, there is still a part of the upper portion of the transparent region 113. The electric layer 130 exists, so that the soft substrate 110 can be prevented from being damaged by the subsequent semiconductor process, causing surface roughening and degrading display quality. Furthermore, since the present embodiment uses the halftone mask process to reduce the amount of use of the mask, the manufacturer can reduce the influence of the stress accumulation of the dielectric layer 130 without significantly increasing the manufacturing cost.

Second embodiment

10 to 20 are cross-sectional views showing a manufacturing process of an active device array substrate according to a second embodiment of the present invention. Figure 46 is a top plan view showing an active device array substrate according to the first, second, third and fourth embodiments of the present invention. In Figures 10-20, the II area shows the section along line I of Figure 46, the II-II area shows the section along line II of Figure 46, and the III-III area shows the line along section 46. Section III.

Please refer to Figure 10 first. As shown in the figure, the manufacturer can provide the flexible substrate 110 at this time. The flexible substrate 110 preferably has flexibility, and the display panel which is subsequently fabricated is also flexible. The flexible substrate 110 may be defined with an adjacent transistor region 112, a light transmitting region 113, a capacitor region 114 and a connection pad region 116. In one or more embodiments of the present invention, in order to facilitate the subsequent process operation, the manufacturer may first set the flexible substrate 110 on the glass carrier to perform the process, and then, after the active device array substrate is manufactured, the soft substrate 110 is removed from the glass. The carrier plate was peeled off and removed. In this embodiment, the material of the flexible substrate 110 may include plastics, such as polyimide (PI), polyethylene terephthalate (PET), poly 2,6-naphthalene. Polyethylene Naphthalate (PEN) or any combination of the above, or other copolymer plastic materials. It should be understood that the materials of the soft substrate 110 are merely illustrative and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains, the material of the flexible substrate 110 should be elastically selected according to actual needs.

Then, the manufacturer can form a patterned first conductive layer on the flexible substrate 110. For example, the first conductive layer can be formed first, and then the first conductive layer is patterned by a lithography and etching process, whereby the flexible substrate 110 is formed on the flexible substrate 110. Forming a patterned first conductive layer thereon, at least comprising forming a gate 122 on the transistor region 112, and patterning the first conductive layer further comprises a gate line connecting the gate 122, and connecting the capacitor region 114 of the flexible substrate 110 A lower electrode 124 and a lower connection pad 126 are formed on the pad region 116, respectively. In this embodiment, the material of the first conductive layer (ie, the gate 122, the lower electrode 124, and the lower connection pad 126) may include any of the foregoing, such as titanium, molybdenum, chromium, niobium, aluminum, copper, silver, gold, and the like. The combination or alloy may be formed by physical vapor deposition, such as sputtering or chemical vapor deposition, and the method of patterning the first conductive layer may be lithography and etching.

Please refer to Figure 11 below. As shown, the manufacturer can sequentially form the dielectric layer 130, the semiconductor layer 140, and the ohmic contact layer 150. The dielectric layer 130, the semiconductor layer 140, and the ohmic contact layer 150 cover the gate 122, the lower electrode 124, the lower connection pad 126, and the flexible substrate 110. The material of the dielectric layer 130 may include tantalum nitride, hafnium oxide, tantalum oxynitride or any combination thereof. The material of the semiconductor layer 140 may include amorphous germanium, a germanium oxide, an oxide semiconductor, or any combination thereof. The material of the ohmic contact layer 150 may include an N-type doped amorphous germanium or a P-type doped amorphous germanium or the like.

Please refer to Figure 12 below. As shown, the manufacturer can pattern the semiconductor layer 140 and the ohmic contact layer 150 at this time to remove the transparent region 113, the capacitor region 114 and the semiconductor layer 140 and the ohmic contact layer 150 over the connection pad region 116, and only The semiconductor layer 140 over the transistor region 112 and the ohmic contact layer 150 are left, with the semiconductor layer 140 above the transistor region 112 being used as the channel layer 142. In the present embodiment, the method of patterning the semiconductor layer 140 and the ohmic contact layer 150 may be lithography and etching.

Please refer to Figure 13 below. As shown, the manufacturer can form a source 172 and a drain 174 on both sides of the channel layer 142, and form an upper electrode 176 on the dielectric layer 130. The upper electrode 176 is located above the lower electrode 124. . The source 172 and the drain 174 are electrically connected to the channel layer 142, respectively. Specifically, the manufacturer may first form a second conductive layer over the flexible substrate 110, and the second conductive layer covers all the structures on the flexible substrate 110. Then, the second conductive layer can be patterned by the manufacturer, thereby forming a source 172 and a drain 174 on both sides of the channel layer 142, and forming a data line connecting the source 172 on the dielectric layer 130 and underlying An upper electrode 176 is formed on the dielectric layer 130 above the electrode 124. In the process of patterning the second conductive layer, the manufacturer may select the ohmic contact layer 150 between the source 172 and the drain 174 to be etched down, such that the ohmic contact layer 150 is broken to form the source ohmic contact layer 152. Contact layer 154 with the drain ohms. The above embodiment is described by taking a source 172 and a drain 174 covering a portion of the channel layer 142. In a variant embodiment, the channel layer 142 may also cover part of the source 172 and the drain 174, and only need to adjust the process sequence. And using two masks to define their respective patterns, which are well known to those of ordinary skill in the art, and therefore will not be described again.

In this embodiment, the material of the second conductive layer (ie, the source 172, the drain 174, and the upper electrode 176) may include any combination of the foregoing, such as titanium, molybdenum, chromium, niobium, aluminum, copper, silver, gold, and the like. Or an alloy, which may be formed by physical vapor deposition, such as sputtering or chemical vapor deposition, and the method of patterning the second conductive layer may be lithography and etching.

After the process of FIG. 13, since the channel layer 142, the source 172 and the drain 174 are formed on the dielectric layer 130, the gate 122 and the dielectric layer 130 on the gate 122 (ie, the gate dielectric) Layer), channel layer 142, source ohmic contact layer 152, drain ohmic contact layer 154, source 172 and drain 174 will form a thin film transistor, and lower electrode 124, dielectric layer 130 on lower electrode 124 (also That is, the capacitor dielectric layer) and the upper electrode 176 will constitute a storage capacitor. It should be understood that although the source 172 and the drain 174 disclosed in the embodiment are stacked above the channel layer 142, those skilled in the art can adjust the implementation of the thin film transistor according to actual conditions. For example, in some embodiments of the present invention, the channel layer may also be stacked above the source and the drain to form a thin film transistor.

Please refer to Figure 14 below. As shown, the manufacturer can form a protective layer 180 at this time, which covers the source 172, the channel layer 142, the drain 174, the dielectric layer 130, and the upper electrode 176. In the present embodiment, the material of the protective layer 180 may include tantalum nitride, cerium oxide, cerium oxynitride or any combination thereof.

Please refer to Figure 15 below. A photoresist layer may be formed on the protective layer 180 by the manufacturer, and the photoresist layer covers the protective layer 180. Next, the manufacturer can pattern the photoresist layer by a halftone mask process to form a patterned photoresist layer. The patterned photoresist layer described above may include a thick photoresist layer 162 and a thin photoresist layer 164. The thick photoresist layers 162 are respectively located above the transistor region 112 of the flexible substrate 110, the capacitor region 114 and the connection pad region 116, and the thin photoresist layer 164 is located above the transparent region 113 of the flexible substrate 110. In addition, a photoresist etching hole 166, a capacitor etching hole 167 and a connection pad etching hole 168 are formed in the thick photoresist layer 162, respectively exposing the protective layer 180 above the drain 174, the protective layer 180 above the upper electrode 176, and the lower layer. A protective layer 180 over the pad 126 is attached.

Please refer to Figure 16 below. As shown, the manufacturer can pattern the photoresist layer (including the thick photoresist layer 162 and the thin photoresist layer 164) as a mask, and form a transistor contact hole 182, a capacitor contact hole 184, and a connection in the protective layer 180. The pad contacts the hole 186 to expose the drain 174, the upper electrode 176 and the lower connection pad 126, respectively. In the present embodiment, a specific manner of forming the transistor contact hole 182, the capacitor contact hole 184, and the connection pad contact hole 186 may be, for example, dry etching or wet etching.

Next, referring to FIG. 17, as shown, the manufacturer can remove the thin photoresist layer 164 and simultaneously thin the thick photoresist layer 162 to expose the protective layer 180 above the light-transmissive region 113. In the present embodiment, the method of removing the thin photoresist layer 164 and thinning the thick photoresist layer 162 may be ashing.

Please refer to Figure 18 below. As shown, the remaining patterned patterned photoresist layer (ie, the thinned photoresist layer 162) is used as a mask to remove the protective layer 180 located in the transparent region 113 and The dielectric layer 130 of the optical region 113 has a portion of the dielectric layer 130 above the gate 122 having a first thickness T1, and a portion of the dielectric layer 130 on the flexible substrate 110 at the center of the transparent region 113 has a second thickness T2. The second thickness T2 is smaller than the first thickness T1, and the ratio of the second thickness T2 to the first thickness T1 is between 0.05 and 0.95, and preferably between 0.1 and 0.8, and more preferably between Between 0.3 and 0.6. In the present embodiment, the specific manner of removing the protective layer 180 and the dielectric layer 130 may be, for example, dry etching or wet etching.

It should be understood that although the present embodiment uses a halftone mask process in the process of FIGS. 15-18 in order to reduce the number of use of the mask, the present invention is not limited thereto, and those having ordinary knowledge in the technical field to which the present invention pertains Alternatively, a photomask process can be used to form the transistor contact hole 182, the capacitor contact hole 184 and the connection pad contact hole 186, and another mask process is used to remove the protective layer 180 located in the transparent region 113. And a dielectric layer 130 of the light transmissive region 113.

In addition, since in FIG. 17, the ashing thick photoresist layer 162 and the thin photoresist layer 164 will inevitably cause the thick photoresist layer 162 to be retracted (as indicated by the arrow S), the subsequent etching process will injure the electricity. The protective layer 180 over the edge of the crystal region 112 is such that the protective layer 180 over the edge of the transistor region 112 has a fourth thickness T4 that is less than the thickness of the protective layer 180 above the center of the transistor region 112 (eg, third Thickness T3). In addition, if the flexible substrate 110 has a metal oxide dielectric layer, the metal oxide dielectric layer may also be damaged by a subsequent etching process, so that the thickness of the metal oxide dielectric layer is different.

Please refer to Figure 19 below. As shown, the manufacturer can peel at this time The remaining patterned photoresist layer (i.e., the thinned photoresist layer 162) is removed by a stripper.

Please refer to Figure 20 below. As shown, the manufacturer can form a pixel electrode 192 on the dielectric layer 130 on the light transmissive region 113 at this time. The pixel electrodes 192 are electrically connected to the drain electrodes 174 and the upper electrodes 176 through the transistor contact holes 182 and the capacitor contact holes 184, respectively. At the same time, the manufacturer can also form the upper connection pads 194 on the lower connection pads 126. Specifically, the manufacturer may first form a transparent conductive layer over the flexible substrate 110, and the transparent conductive layer covers all the structures on the flexible substrate 110. Next, the manufacturer can pattern the transparent conductive layer, thereby forming the pixel electrode 192 and the upper layer connection pad 194. In the present embodiment, the material of the transparent conductive layer (that is, the pixel electrode 192 and the upper layer connection pad 194) may include indium tin oxide, indium zinc oxide, aluminum zinc oxide, or any combination thereof. After the process of FIG. 20, the lower connection pad 126 and the upper connection pad 194 will constitute a connection pad which is located on the connection pad region 116 of the flexible substrate 110 for connecting an external circuit.

Similarly, in the second embodiment, since the second thickness T2 of the dielectric layer 130 at the center of the light-transmitting region 113 is thin, the influence of the stress accumulation of the dielectric layer 130 in the thermal process can be reduced, and further reduced. The amount of deformation of the flexible substrate 110 and the glass carrier plate on which the flexible substrate 110 is mounted. In addition, since the dielectric layer 130 is still present on the transparent region 113, the present embodiment can still provide sufficient protection for the active device array substrate. In the subsequent semiconductor process of the dielectric layer 130, there is still a part of the upper portion of the transparent region 113. The electric layer 130 exists, so that the soft substrate 110 can be prevented from being damaged by the subsequent semiconductor process, causing surface roughening and degrading display quality. Again, because In the present embodiment, the halftone mask process is used to reduce the amount of use of the photomask, so that the manufacturer can reduce the influence of the stress accumulation of the dielectric layer 130 without significantly increasing the manufacturing cost.

Third embodiment

21 to 31 are cross-sectional views showing the manufacturing process of the active device array substrate in accordance with the third embodiment of the present invention. Figure 46 is a top plan view showing an active device array substrate according to the first, second, third and fourth embodiments of the present invention. In the 21st to 31st, the II area shows the section along the line I of Fig. 46, the II-II area shows the section along the line II of Fig. 46, and the III-III area shows the line along the line 46. Section III. The top view design of the active device array substrate of the present invention is for illustrative purposes only, and is not limited to the above-described drawings, and those skilled in the art can appropriately change the design according to requirements.

Please refer to Figure 21 first. As shown in the figure, the manufacturer can provide the flexible substrate 110 at this time. The flexible substrate 110 preferably has flexibility, and the display panel which is subsequently fabricated is also flexible. The flexible substrate 110 may be defined with an adjacent transistor region 112, a light transmitting region 113, a capacitor region 114 and a connection pad region 116. In one or more embodiments of the present invention, in order to facilitate the subsequent process operation, the manufacturer may first set the flexible substrate 110 on the glass carrier to perform the process. After the active device array substrate is manufactured, the flexible substrate 110 is removed from the glass. The carrier plate was peeled off and removed. In this embodiment, the material of the flexible substrate 110 may include plastics, such as polyimide (PI), polyethylene terephthalate (PET), poly 2,6-naphthalene. Polyethylene Naphthalate (PEN) or any combination of the above, or other copolymer plastic materials. It should be understood that the materials of the soft substrate 110 are merely illustrative and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains, the material of the flexible substrate 110 should be elastically selected according to actual needs.

Then, the manufacturer can form a patterned first conductive layer on the flexible substrate 110. For example, the first conductive layer can be formed first, and then the first conductive layer is patterned by a lithography and etching process, whereby the flexible substrate 110 is formed on the flexible substrate 110. Forming a patterned first conductive layer thereon, at least comprising forming a gate 122 on the transistor region 112, and patterning the first conductive layer further comprises a gate line connecting the gate 122, and connecting the capacitor region 114 of the flexible substrate 110 A lower electrode 124 and a lower connection pad 126 are formed on the pad region 116, respectively. In this embodiment, the material of the first conductive layer (ie, the gate 122, the lower electrode 124, and the lower connection pad 126) may include any of the foregoing, such as titanium, molybdenum, chromium, niobium, aluminum, copper, silver, gold, and the like. The combination or alloy may be formed by physical vapor deposition, such as sputtering or chemical vapor deposition, and the method of patterning the first conductive layer may be lithography and etching.

Please refer to Figure 22 below. As shown, the manufacturer can sequentially form the metal oxide dielectric layer 135, the dielectric layer 130, the semiconductor layer 140, and the ohmic contact layer 150. The metal oxide dielectric layer 135, the dielectric layer 130, the semiconductor layer 140, and the ohmic contact layer 150 cover the gate 122, the lower electrode 124, the lower connection pad 126, and the flexible substrate 110. The material of the metal oxide dielectric layer 135 may include indium oxide, zinc oxide, gallium oxide or any combination thereof. The material of the dielectric layer 130 may include tantalum nitride, hafnium oxide, tantalum oxynitride or any combination thereof. The material of the semiconductor layer 140 may include amorphous germanium, a germanium oxide, an oxide semiconductor, or any combination thereof. The material of the ohmic contact layer 150 may include an N-type doped amorphous germanium or a P-type doped amorphous germanium or the like.

Please refer to Figure 23 below. As shown, the manufacturer can pattern the semiconductor layer 140 and the ohmic contact layer 150 at this time to remove the transparent region 113, the capacitor region 114 and the semiconductor layer 140 and the ohmic contact layer 150 over the connection pad region 116, and only The semiconductor layer 140 over the transistor region 112 and the ohmic contact layer 150 are left, with the semiconductor layer 140 above the transistor region 112 being used as the channel layer 142. In the present embodiment, the method of patterning the semiconductor layer 140 and the ohmic contact layer 150 may be lithography and etching.

Please refer to Figure 24 below. As shown, the manufacturer can form a source 172 and a drain 174 on both sides of the channel layer 142, and form an upper electrode 176 on the dielectric layer 130. The upper electrode 176 is located above the lower electrode 124. . The source 172 and the drain 174 are electrically connected to the channel layer 142, respectively. Specifically, the manufacturer may first form a second conductive layer over the flexible substrate 110, and the second conductive layer covers all the structures on the flexible substrate 110. Then, the second conductive layer can be patterned by the manufacturer, thereby forming a source 172 and a drain 174 on both sides of the channel layer 142, and forming a data line connecting the source 172 on the dielectric layer 130 and underlying An upper electrode 176 is formed on the dielectric layer 130 above the electrode 124. In the process of patterning the second conductive layer, the manufacturer may select the ohmic contact layer 150 between the source 172 and the drain 174 to be etched down, such that the ohmic contact layer 150 is broken to form the source ohmic contact layer 152. Contact layer 154 with the drain ohms. The above embodiment is described by taking a source 172 and a drain 174 covering a portion of the channel layer 142. In a variant embodiment, the channel layer 142 may also cover part of the source 172 and the drain 174, and only need to adjust the process sequence. And using two masks to define their respective patterns, which are well known to those of ordinary skill in the art, and therefore will not be described again.

In this embodiment, the material of the second conductive layer (ie, the source 172, the drain 174, and the upper electrode 176) may include any combination of the foregoing, such as titanium, molybdenum, chromium, niobium, aluminum, copper, silver, gold, and the like. Or an alloy, which may be formed by physical vapor deposition, such as sputtering or chemical vapor deposition, and the method of patterning the second conductive layer may be lithography and etching.

After the process of FIG. 24, since the channel layer 142, the source 172 and the drain 174 are formed on the dielectric layer 130, the gate electrode 122, the metal oxide dielectric layer 135 on the gate 122, and the dielectric layer are formed. 130 (ie, gate dielectric layer), channel layer 142, source ohmic contact layer 152, drain ohmic contact layer 154, source 172 and drain 174 will form a thin film transistor, while lower electrode 124, lower electrode 124 The upper metal oxide dielectric layer 135, the dielectric layer 130 (ie, the capacitor dielectric layer) and the upper electrode 176 will constitute a storage capacitor. It should be understood that although the source 172 and the drain 174 disclosed in the embodiment are stacked above the channel layer 142, those skilled in the art can adjust the implementation of the thin film transistor according to actual conditions. For example, in some embodiments of the present invention, the channel layer may also be stacked above the source and the drain to form a thin film transistor.

Please refer to Figure 25 below. As shown, the manufacturer can form a protective layer 180 at this time, which covers the source 172, the channel layer 142, the drain 174, the dielectric layer 130, and the upper electrode 176. In the present embodiment, the material of the protective layer 180 may include tantalum nitride, cerium oxide, cerium oxynitride or any combination thereof.

Then, referring to FIG. 26, the manufacturer can form a photoresist layer on the protective layer 180, and the photoresist layer covers the protective layer 180. Next, the manufacturer can pattern the photoresist layer by a halftone mask process to form a patterned photoresist layer. The patterned photoresist layer described above may include a thick photoresist layer 162 and a thin photoresist layer 164. The thick photoresist layers 162 are respectively located above the transistor region 112 of the flexible substrate 110, the capacitor region 114 and the connection pad region 116, and the thin photoresist layer 164 is located above the transparent region 113 of the flexible substrate 110. In addition, a photoresist etching hole 166, a capacitor etching hole 167 and a connection pad etching hole 168 are formed in the thick photoresist layer 162, respectively exposing the protective layer 180 above the drain 174, the protective layer 180 above the upper electrode 176, and the lower layer. A protective layer 180 over the pad 126 is attached.

Please refer to Figure 27 below. As shown, the manufacturer can pattern the photoresist layer (including the thick photoresist layer 162 and the thin photoresist layer 164) as a mask, and form a transistor contact hole 182, a capacitor contact hole 184, and a connection in the protective layer 180. The pad contacts the hole 186 to expose the drain 174, the upper electrode 176 and the lower connection pad 126, respectively. In the present embodiment, a specific manner of forming the transistor contact hole 182, the capacitor contact hole 184, and the connection pad contact hole 186 may be, for example, dry etching or wet etching.

Referring to FIG. 28, as shown, the manufacturer can remove the thin photoresist layer 164 and simultaneously thin the thick photoresist layer 162 to expose the protective layer 180 over the light-transmissive region 113. In the present embodiment, the method of removing the thin photoresist layer 164 and thinning the thick photoresist layer 162 may be ashing.

Please refer to Figure 29 below. As shown, the remaining patterned patterned photoresist layer (ie, the thinned photoresist layer 162) is used as a mask to remove the protective layer 180 located in the transparent region 113 and The dielectric layer 130 of the optical region 113 has a portion of the dielectric layer 130 above the gate 122 having a first thickness T1, and a portion of the dielectric substrate 130 located at the center of the transparent region 113. The electrical layer 130 has a second thickness T2. The second thickness T2 is smaller than the first thickness T1, and the ratio of the second thickness T2 to the first thickness T1 is between 0.05 and 0.95, and preferably between 0.1 and 0.8, and more preferably between Between 0.3 and 0.6. In the present embodiment, the specific manner of removing the protective layer 180 and the dielectric layer 130 may be, for example, dry etching or wet etching.

It should be understood that although the present embodiment uses a halftone mask process in the process of FIGS. 26-29 to reduce the number of use of the mask, the present invention is not limited thereto, and those having ordinary knowledge in the technical field to which the present invention pertains Alternatively, a photomask process can be used to form the transistor contact hole 182, the capacitor contact hole 184 and the connection pad contact hole 186, and another mask process is used to remove the protective layer 180 located in the transparent region 113. And a dielectric layer 130 of the light transmissive region 113.

In addition, since in FIG. 28, the ashing thick photoresist layer 162 and the thin photoresist layer 164 will inevitably cause the thick photoresist layer 162 to be retracted (as indicated by the arrow S), the subsequent etching process will injure the electricity. The protective layer 180 over the edge of the crystal region 112 is such that the protective layer 180 over the edge of the transistor region 112 has a fourth thickness T4 that is less than the thickness of the protective layer 180 above the center of the transistor region 112 (eg, third Thickness T3).

Please refer to Figure 30. As shown, the manufacturer can now remove the remaining patterned photoresist layer (i.e., the thinned photoresist layer 162) by a stripper.

Please refer to Figure 31. As shown, the manufacturer can form a pixel electrode 192 on the dielectric layer 130 on the light transmissive region 113 at this time. The pixel electrodes 192 are electrically connected to the drain electrodes 174 and the upper electrodes 176 through the transistor contact holes 182 and the capacitor contact holes 184, respectively. At the same time, the manufacturer can also An upper connection pad 194 is formed on the lower connection pad 126. Specifically, the manufacturer may first form a transparent conductive layer over the flexible substrate 110, and the transparent conductive layer covers all the structures on the flexible substrate 110. Next, the manufacturer can pattern the transparent conductive layer, thereby forming the pixel electrode 192 and the upper layer connection pad 194. In the present embodiment, the material of the transparent conductive layer (that is, the pixel electrode 192 and the upper layer connection pad 194) may include indium tin oxide, indium zinc oxide, aluminum zinc oxide, or any combination thereof. After the process of FIG. 31, the lower connection pad 126 and the upper connection pad 194 will constitute a connection pad which is located on the connection pad region 116 of the flexible substrate 110 for connecting an external circuit.

Similarly, in the third embodiment, since the second thickness T2 of the dielectric layer 130 at the center of the light-transmitting region 113 is thin, the influence of the stress accumulation of the dielectric layer 130 in the thermal process can be reduced, and further reduced. The amount of deformation of the flexible substrate 110 and the glass carrier plate on which the flexible substrate 110 is mounted. On the other hand, since the metal oxide dielectric layer 135 exists between the dielectric layer 130 and the flexible substrate 110, the adhesion of the structure on the flexible substrate 110 to the flexible substrate 110 is increased, thereby reducing the peeling of the two in the process. opportunity. In addition, since the dielectric layer 130 is still present on the transparent region 113, the present embodiment can still provide sufficient protection for the active device array substrate. In the subsequent semiconductor process of the dielectric layer 130, there is still a part of the upper portion of the transparent region 113. The electric layer 130 exists, so that the soft substrate 110 can be prevented from being damaged by the subsequent semiconductor process, causing surface roughening and degrading display quality. Furthermore, since the present embodiment uses the halftone mask process to reduce the amount of use of the mask, the manufacturer can reduce the influence of the stress accumulation of the dielectric layer 130 without significantly increasing the manufacturing cost.

Fourth embodiment

32 to 45 are cross-sectional views showing the manufacturing process of the active device array substrate in accordance with the fourth embodiment of the present invention. Figure 46 is a top plan view showing an active device array substrate according to the first, second, third and fourth embodiments of the present invention. In the 32nd to 45th drawings, the II area shows the section along the line I of Fig. 46, the II-II area shows the section along the line II of Fig. 46, and the III-III area shows the line along the line 46. Section III.

Please refer to Figure 32 first. As shown in the figure, the manufacturer can provide the flexible substrate 110 at this time. The flexible substrate 110 preferably has flexibility, and the display panel which is subsequently fabricated is also flexible. The flexible substrate 110 may be defined with an adjacent transistor region 112, a light transmitting region 113, a capacitor region 114 and a connection pad region 116. In one or more embodiments of the present invention, in order to facilitate the subsequent process operation, the manufacturer may first set the flexible substrate 110 on the glass carrier to perform the process. After the active device array substrate is manufactured, the flexible substrate 110 is removed from the glass. The carrier plate was peeled off and removed. In this embodiment, the material of the flexible substrate 110 may include plastics, such as polyimide (PI), polyethylene terephthalate (PET), poly 2,6-naphthalene. Polyethylene Naphthalate (PEN) or any combination of the above, or other copolymer plastic materials. It should be understood that the materials of the soft substrate 110 are merely illustrative and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains, the material of the flexible substrate 110 should be elastically selected according to actual needs.

Next, the manufacturer can sequentially form the metal oxide dielectric layer 135 and the first conductive layer 120 on the flexible substrate 110. In the present embodiment, the material of the metal oxide dielectric layer 135 may include indium oxide, zinc oxide, gallium oxide, or any combination thereof. The material of the first conductive layer 120 may include any combination or alloy of titanium, molybdenum, chromium, niobium, aluminum, copper, silver, gold, etc., and may be formed by physical vapor deposition, such as sputtering, or Chemical vapor deposition.

The manufacturer may form a photoresist layer on the first conductive layer 120, the photoresist layer covering the first conductive layer 120. Next, the manufacturer can pattern the photoresist layer by a halftone mask process to form a patterned photoresist layer. The patterned photoresist layer may include a thick photoresist layer 161 and a thin photoresist layer 163. The thick photoresist layers 161 are respectively located above the positions where the gate 122, the lower electrode 124 and the lower connection pad 126 (shown in FIGS. 35-45) are formed, and the thin photoresist layer 163 is disposed adjacent to the thick photoresist layer 161 and exposed. The first conductive layer 120 of the light transmitting region 113.

Then, as shown in FIG. 33, the manufacturer can pattern the photoresist layer (including the thick photoresist layer 161 and the thin photoresist layer 163) as a mask to remove the first conductive layer 120 located in the transparent region 113, and together A portion of the thickness of the metal oxide dielectric layer 135 located in the light transmissive region 113 is removed. In this embodiment, a specific manner of removing a portion of the first conductive layer 120 and the metal oxide dielectric layer 135 may be, for example, dry etching or wet etching.

Referring to FIG. 34, as shown, the manufacturer can remove the thin photoresist layer 163 and simultaneously thin the thick photoresist layer 161. In the present embodiment, the method of removing the thin photoresist layer 163 and thinning the thick photoresist layer 161 may be ashing.

Next, as shown in FIG. 35, the patterned photoresist layer (ie, the thinned photoresist layer 161 after thinning) which the manufacturer can leave at this time is a mask, and the removed portion is located in the transistor region 112, The capacitor region 114 and the first conductive layer 120 of the pad region 116 are formed to form a gate 122, a gate line connecting the gate 122, a lower electrode 124 and a lower connection pad 126.

It should be understood that although the present embodiment uses a halftone mask process in the processes of FIGS. 32-35 to reduce the number of use of the mask, the present invention is not limited thereto, and those having ordinary knowledge in the technical field to which the present invention pertains Alternatively, a reticle process may be used to form the structure illustrated in FIG. 33, and another reticle process may be used to form the structure illustrated in FIG.

Please refer to Figure 36 below. As shown, the manufacturer can first remove the remaining patterned photoresist layer (i.e., the thinned photoresist layer 161 after thinning) with a stripper. Next, the manufacturer can sequentially form the dielectric layer 130, the semiconductor layer 140, and the ohmic contact layer 150. The dielectric layer 130, the semiconductor layer 140, and the ohmic contact layer 150 cover the gate 122, the lower electrode 124, the lower connection pad 126, the metal oxide dielectric layer 135, and the flexible substrate 110. The material of the dielectric layer 130 may include tantalum nitride, hafnium oxide, tantalum oxynitride or any combination thereof. The material of the semiconductor layer 140 may include amorphous germanium, a germanium oxide, an oxide semiconductor, or any combination thereof. The material of the ohmic contact layer 150 may include an N-type doped amorphous germanium or a P-type doped amorphous germanium or the like.

Please refer to Figure 37. As shown, the manufacturer can pattern the semiconductor layer 140 and the ohmic contact layer 150 at this time to remove the transparent region 113, the capacitor region 114 and the semiconductor layer 140 and the ohmic contact layer 150 over the connection pad region 116, and only The semiconductor layer 140 over the transistor region 112 and the ohmic contact layer 150 are left, with the semiconductor layer 140 above the transistor region 112 being used as the channel layer 142. In the present embodiment, the method of patterning the semiconductor layer 140 and the ohmic contact layer 150 may be lithography and etching.

Please refer to Figure 38. As shown, the manufacturer can form a source 172 and a drain 174 on both sides of the channel layer 142, and form an upper electrode 176 on the dielectric layer 130. The upper electrode 176 is located above the lower electrode 124. . The source 172 and the drain 174 are electrically connected to the channel layer 142, respectively. Specifically, the manufacturer may first form a second conductive layer over the flexible substrate 110, and the second conductive layer covers all the structures on the flexible substrate 110. Then, the second conductive layer can be patterned by the manufacturer, thereby forming a source 172 and a drain 174 on both sides of the channel layer 142, and forming a data line connecting the source 172 on the dielectric layer 130 and underlying An upper electrode 176 is formed on the dielectric layer 130 above the electrode 124. In the process of patterning the second conductive layer, the manufacturer may select the ohmic contact layer 150 between the source 172 and the drain 174 to be etched down, such that the ohmic contact layer 150 is broken to form the source ohmic contact layer 152. Contact layer 154 with the drain ohms. The above embodiment is described by taking a source 172 and a drain 174 covering a portion of the channel layer 142. In a variant embodiment, the channel layer 142 may also cover part of the source 172 and the drain 174, and only need to adjust the process sequence. And using two masks to define their respective patterns, which are well known to those of ordinary skill in the art, and therefore will not be described again.

In this embodiment, the material of the second conductive layer (ie, the source 172, the drain 174, and the upper electrode 176) may include any combination of the foregoing, such as titanium, molybdenum, chromium, niobium, aluminum, copper, silver, gold, and the like. Or an alloy, which may be formed by physical vapor deposition, such as sputtering or chemical vapor deposition, and the method of patterning the second conductive layer may be lithography and etching.

After the process of FIG. 38, since the channel layer 142, the source 172 and the drain 174 are formed on the dielectric layer 130, the gate 122 and the dielectric layer 130 on the gate 122 (ie, the gate dielectric) Layer), channel layer 142, source ohmic contact layer 152, drain ohmic contact layer 154, source 172 and drain 174 will form a thin film transistor, and lower electrode 124, dielectric layer 130 on lower electrode 124 (also That is, the capacitor dielectric layer) and the upper electrode 176 will constitute a storage capacitor. It should be understood that although the source 172 and the drain 174 disclosed in the embodiment are stacked above the channel layer 142, those skilled in the art can adjust the implementation of the thin film transistor according to actual conditions. For example, in some embodiments of the present invention, the channel layer may also be stacked above the source and the drain to form a thin film transistor.

Please refer to Figure 39 below. As shown, the manufacturer can form a protective layer 180 at this time, which covers the source 172, the channel layer 142, the drain 174, the dielectric layer 130, and the upper electrode 176. In the present embodiment, the material of the protective layer 180 may include tantalum nitride, cerium oxide, cerium oxynitride or any combination thereof.

Then, please refer to Figure 40. A photoresist layer may be formed on the protective layer 180 by the manufacturer, and the photoresist layer covers the protective layer 180. Next, the manufacturer can pattern the photoresist layer by a halftone mask process to form a patterned photoresist layer. The patterned photoresist layer described above may include a thick photoresist layer 162 and a thin photoresist layer 164. The thick photoresist layers 162 are respectively located above the transistor region 112 of the flexible substrate 110, the capacitor region 114 and the connection pad region 116, and the thin photoresist layer 164 is located above the transparent region 113 of the flexible substrate 110. In addition, a photoresist etching hole 166, a capacitor etching hole 167 and a connection pad etching hole 168 are formed in the thick photoresist layer 162, respectively exposing the protective layer 180 above the drain 174, the protective layer 180 above the upper electrode 176, and the lower layer. A protective layer 180 over the pad 126 is attached.

Please refer to Figure 41 below. As shown, the manufacturer can pattern the photoresist layer (including the thick photoresist layer 162 and the thin photoresist layer 164) as a mask, and form a transistor contact hole 182, a capacitor contact hole 184, and a connection in the protective layer 180. The pad contacts the hole 186 to expose the drain 174, the upper electrode 176 and the lower connection pad 126, respectively. In the present embodiment, a specific manner of forming the transistor contact hole 182, the capacitor contact hole 184, and the connection pad contact hole 186 may be, for example, dry etching or wet etching.

Next, referring to FIG. 42, as shown, the manufacturer can remove the thin photoresist layer 164 and simultaneously thin the thick photoresist layer 162 to expose the protective layer 180 above the light transmissive region 113. In the present embodiment, the method of removing the thin photoresist layer 164 and thinning the thick photoresist layer 162 may be ashing.

Please refer to Figure 43 below. As shown, the remaining patterned patterned photoresist layer (ie, the thinned photoresist layer 162) is used as a mask to remove the protective layer 180 located in the transparent region 113 and The dielectric layer 130 of the optical region 113 has a portion of the dielectric layer 130 above the gate 122 having a first thickness T1, and a portion of the dielectric layer 130 on the flexible substrate 110 at the center of the transparent region 113 has a second thickness T2. The second thickness T2 is smaller than the first thickness T1, and the ratio of the second thickness T2 to the first thickness T1 is between 0.05 and 0.95, and preferably between 0.1 and 0.8, and more preferably between Between 0.3 and 0.6. In the present embodiment, the specific manner of removing the protective layer 180 and the dielectric layer 130 may be, for example, dry etching or wet etching.

It should be understood that although the present embodiment uses a halftone mask process in the process of FIGS. 40 to 43 in order to reduce the number of use of the mask, the present invention is not limited thereto, and those having ordinary knowledge in the technical field to which the present invention pertains Alternatively, a photomask process can be used to form the transistor contact hole 182, the capacitor contact hole 184 and the connection pad contact hole 186, and another mask process is used to remove the protective layer 180 located in the transparent region 113. And a dielectric layer 130 of the light transmissive region 113.

In addition, since in FIG. 42, the ashing thick photoresist layer 162 and the thin photoresist layer 164 will inevitably cause the thick photoresist layer 162 to be retracted (as indicated by the arrow S), the subsequent etching process will injure the electricity. The protective layer 180 over the edge of the crystal region 112 is such that the protective layer 180 over the edge of the transistor region 112 has a fourth thickness T4 that is less than the thickness of the protective layer 180 above the center of the transistor region 112 (eg, third Thickness T3). In addition, in some embodiments, the metal oxide dielectric layer 135 may also be damaged by an etching process, such that the thickness of the metal oxide dielectric layer 135 is different.

Please refer to Figure 44 below. As shown, the manufacturer can now remove the remaining patterned photoresist layer (i.e., the thinned photoresist layer 162) by a stripper.

Please refer to Figure 45 below. As shown, the manufacturer can form a pixel electrode 192 on the dielectric layer 130 on the light transmissive region 113 at this time. The pixel electrodes 192 are electrically connected to the drain electrodes 174 and the upper electrodes 176 through the transistor contact holes 182 and the capacitor contact holes 184, respectively. At the same time, the manufacturer can also form the upper connection pads 194 on the lower connection pads 126. Specifically, the manufacturer may first form a transparent conductive layer over the flexible substrate 110, and the transparent conductive layer covers all the structures on the flexible substrate 110. Next, the manufacturer can pattern the transparent conductive layer, thereby forming the pixel electrode 192 and the upper layer connection pad 194. In the present embodiment, the material of the transparent conductive layer (that is, the pixel electrode 192 and the upper layer connection pad 194) may include indium tin oxide, indium zinc oxide, aluminum zinc oxide, or any combination thereof. After the process of FIG. 45, the lower connection pad 126 and the upper connection pad 194 will constitute a connection pad which is located on the connection pad region 116 of the flexible substrate 110 for connecting an external circuit.

Similarly, in the fourth embodiment, since the second thickness T2 of the dielectric layer 130 at the center of the light-transmitting region 113 is thin, the influence of the stress accumulation of the dielectric layer 130 in the thermal process can be reduced, and further reduced. The amount of deformation of the flexible substrate 110 and the glass carrier plate on which the flexible substrate 110 is mounted. On the other hand, since the metal oxide dielectric layer 135 exists between the dielectric layer 130 and the flexible substrate 110, the adhesion of the structure on the flexible substrate 110 to the flexible substrate 110 is increased, thereby reducing the peeling of the two in the process. opportunity. In addition, since the dielectric layer 130 is still present on the transparent region 113, the present embodiment can still provide sufficient protection for the active device array substrate. In the subsequent semiconductor process of the dielectric layer 130, there is still a part of the upper portion of the transparent region 113. The electric layer 130 exists, so that the soft substrate 110 can be prevented from being damaged by the subsequent semiconductor process, causing surface roughening and degrading display quality. Furthermore, since the present embodiment uses the halftone mask process to reduce the amount of use of the mask, the manufacturer can reduce the influence of the stress accumulation of the dielectric layer 130 without significantly increasing the manufacturing cost.

The active device array substrate of the present invention can provide a flexible substrate, which can be subsequently fabricated into various flat displays such as liquid crystal displays, organic light emitting displays, electrophoretic displays and the like. The above-mentioned flat panel display can also have flexible characteristics, which enhances the application range of the flat panel display.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

110. . . Flexible substrate

112. . . Transistor region

113. . . Light transmission area

114. . . Capacitor zone

116. . . Connection pad area

120. . . First conductive layer

122. . . Gate

124. . . Lower electrode

126. . . Lower connection pad

130. . . Dielectric layer

135. . . Metal oxide dielectric layer

140. . . Semiconductor layer

142. . . Channel layer

150. . . Ohmic contact layer

152. . . Source ohmic contact layer

154. . . Bungee ohmic contact layer

161. . . Thick photoresist layer

162. . . Thick photoresist layer

163. . . Thin photoresist layer

164. . . Thin photoresist layer

166. . . Transistor etched hole

167. . . Capacitor etched hole

168. . . Connection pad etching hole

172. . . Source

174. . . Bungee

176. . . Upper electrode

180. . . The protective layer

182. . . Transistor contact hole

184. . . Capacitor contact hole

186. . . Connection pad contact hole

192. . . Pixel electrode

194. . . Upper connection pad

T1. . . First thickness

T2. . . Second thickness

T3. . . Third thickness

T4. . . Fourth thickness

S. . . arrow

I-I. . . region

II-II. . . region

III-III. . . region

I. . . Line segment

II. . . Line segment

III. . . Line segment

1 to 9 are cross-sectional views showing a manufacturing process of an active device array substrate according to a first embodiment of the present invention.

10 to 20 are cross-sectional views showing the manufacturing process of the active device array substrate according to the second embodiment of the present invention.

21 to 31 are cross-sectional views showing the manufacturing process of the active device array substrate in accordance with the third embodiment of the present invention.

32 to 45 are cross-sectional views showing the manufacturing process of the active device array substrate in accordance with the fourth embodiment of the present invention.

Figure 46 is a top plan view showing an active device array substrate according to the first, second, third and fourth embodiments of the present invention.

110. . . Flexible substrate

112. . . Transistor region

113. . . Light transmission area

114. . . Capacitor zone

116. . . Connection pad area

122. . . Gate

124. . . Lower electrode

126. . . Lower connection pad

130. . . Dielectric layer

142. . . Channel layer

152. . . Source ohmic contact layer

154. . . Bungee ohmic contact layer

172. . . Source

174. . . Bungee

176. . . Upper electrode

180. . . The protective layer

182. . . Transistor contact hole

184. . . Capacitor contact hole

186. . . Connection pad contact hole

192. . . Pixel electrode

194. . . Upper connection pad

T1. . . First thickness

T2. . . Second thickness

T3. . . Third thickness

I-I. . . region

II-II. . . region

III-III. . . region

Claims (29)

An active device array substrate comprising: a flexible substrate having at least one transistor region and at least one light transmissive region defined thereon, the transistor region being adjacent to the light transmissive region; and a gate located at the transistor a soft substrate on the soft substrate; a dielectric layer covering the gate and the flexible substrate; a portion of the dielectric layer above the gate having a first thickness, located on the flexible substrate at the center of the light transmissive region Part of the dielectric layer has a second thickness, wherein the second thickness is smaller than the first thickness; a channel layer, a source and a drain are located on the dielectric layer of the transistor region, the channel layer is located Above the gate, the source and the drain are located on both sides of the channel layer and electrically connected to the channel layer respectively; and a pixel electrode is disposed on the dielectric layer of the light transmissive region, the pixel electrode Electrically connected to the bungee. The active device array substrate according to claim 1, wherein the material of the flexible substrate comprises plastic. The active device array substrate according to claim 1, wherein the material of the flexible substrate comprises polyimide (PI), polyethylene terephthalate (PET), poly 2,6-naphthalene. Polyethylene Naphthalate (PEN) or any combination of the above. The active device array substrate according to claim 1, wherein the material of the dielectric layer comprises tantalum nitride, hafnium oxide, tantalum oxynitride or any combination thereof. The active device array substrate of claim 1, further comprising at least one storage capacitor, the storage capacitor being located on the flexible substrate, the storage capacitor comprising a lower electrode, a capacitor dielectric layer and an upper electrode. The active device array substrate of claim 5, wherein the capacitive dielectric layer is part of the dielectric layer. The active device array substrate of claim 1, further comprising at least one connection pad, the connection pad being located on the flexible substrate, the connection pad comprising a lower layer connection pad and an upper layer connection pad. The active device array substrate according to claim 1, wherein the material of the channel layer comprises an amorphous germanium, a germanium germanium, an oxide semiconductor or any combination thereof. The active device array substrate of claim 1, further comprising a protective layer covering the channel layer, the source and the drain. The active device array substrate according to claim 1, wherein the material of the pixel electrode comprises indium tin oxide, indium zinc oxide, aluminum zinc oxide Or any combination of the above. The active device array substrate of claim 1 further comprising a metal oxide dielectric layer between the flexible substrate and the dielectric layer. The active device array substrate of claim 11, wherein the metal oxide dielectric layer is further located between the flexible substrate and the gate. The active device array substrate of claim 11, wherein the metal oxide dielectric layer is further located between the dielectric layer and the gate. The active device array substrate according to claim 11, wherein the material of the metal oxide dielectric layer comprises indium oxide, zinc oxide, gallium oxide or any combination thereof. A method for manufacturing an active device array substrate, comprising the steps of: providing a soft substrate having at least one transistor region and at least one light transmissive region defined thereon; forming a gate on the transistor region of the flexible substrate Forming a dielectric layer and a semiconductor layer, the dielectric layer and the semiconductor layer covering the gate and the flexible substrate; removing a portion of the semiconductor layer to form a channel above the gate And removing a portion of the thickness of the dielectric layer located in the transparent region, such that a portion of the dielectric layer above the gate has a first thickness on the flexible substrate at the center of the transparent region The portion of the dielectric layer has a second thickness, wherein the second thickness is smaller than the first thickness; a source and a drain are respectively formed on two sides of the channel layer, and the channel layer is electrically connected to each other; a protective layer covering the channel layer, the source, the drain, and the dielectric layer; forming a transistor contact hole in the protective layer to expose the drain, respectively, and simultaneously removing the The protective layer of the light transmissive region exposes the dielectric layer located in the light transmissive region; and a pixel electrode is formed on the dielectric layer on the light transmissive region, the pixel electrode is in contact through the transistor The hole is electrically connected to the drain. The method of manufacturing an active device array substrate according to claim 15, wherein the material of the flexible substrate comprises plastic. The method of manufacturing an active device array substrate according to claim 15, wherein the material of the flexible substrate comprises polyimide (PI), polyethylene terephthalate (PET), poly 2, Polyethylene Naphthalate (PEN) or any combination of the above. The manufacturer of the active device array substrate as described in claim 15 The method, wherein the material of the dielectric layer comprises tantalum nitride, hafnium oxide, niobium oxynitride or any combination thereof. The method of manufacturing an active device array substrate according to claim 15, wherein the step of forming the gate on the transistor region of the flexible substrate further comprises forming a lower electrode on the flexible substrate. The method for fabricating an active device array substrate according to claim 19, wherein the step of removing a portion of the semiconductor layer and the dielectric layer comprises: forming a photoresist layer covering the semiconductor layer; and using a halftone mask process, Patterning the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask to remove the exposed semiconductor layer of the transparent region while removing a portion of the photoresist layer above the lower electrode And removing the portion of the dielectric layer by using the remaining patterned photoresist layer as a mask, so that the dielectric layer of the transparent region has the second thickness while removing the lower electrode Part of the semiconductor layer. The method of manufacturing an active device array substrate according to claim 19, wherein the step of forming the source and the drain on each side of the channel layer further comprises forming an upper electrode on the dielectric layer and located Above the lower electrode. The manufacturer of the active device array substrate as described in claim 15 The method of forming the gate on the transistor region of the flexible substrate further comprises forming a lower layer connection pad on the flexible substrate. The method of fabricating an active device array substrate according to claim 22, wherein the step of forming the pixel electrode on the dielectric layer of the light transmissive region further comprises forming an upper layer connection pad on the lower layer connection pad. A method for manufacturing an active device array substrate, comprising the steps of: providing a soft substrate having at least one transistor region and at least one light transmissive region defined thereon; forming a gate on the transistor region of the flexible substrate Forming a dielectric layer covering the gate and the flexible substrate; forming a channel layer, a source and a drain on the dielectric layer, wherein the source and the drain are respectively formed on the channel layer Side, and electrically connected to the channel layer; forming a protective layer covering the channel layer, the source, the drain and the dielectric layer; forming a transistor contact hole in the protective layer, Exposing the drain separately, and simultaneously removing the protective layer located in the transparent region, and the dielectric layer of the transparent region, such that a portion of the dielectric layer above the gate has a first thickness, located at a portion of the dielectric layer on the flexible substrate at the center of the light transmissive region has a second thickness, wherein the second thickness is less than the first thickness; A pixel electrode is formed on the dielectric layer located in the transparent region, and the pixel electrode is electrically connected to the drain through the contact hole of the transistor. The method for fabricating an active device array substrate according to claim 24, further comprising: after forming the gate, and forming a metal oxide dielectric layer covering the gate and the flexible substrate before forming the dielectric layer After the dielectric layer is formed, the metal oxide dielectric layer is between the gate and the flexible substrate and the dielectric layer. The method of fabricating an active device array substrate according to claim 25, wherein the material of the metal oxide dielectric layer comprises indium oxide, zinc oxide, gallium oxide or any combination thereof. The method for fabricating an active device array substrate according to claim 24, further comprising: forming a metal oxide dielectric layer covering the flexible substrate before forming the gate, so that the metal oxide is formed after the gate is formed A dielectric layer is between the gate and the flexible substrate. The method of fabricating an active device array substrate according to claim 27, wherein the step of forming the gate comprises: forming a first conductive layer covering the metal oxide dielectric layer; and removing the first conductive layer located in the transparent region Layer and remove it at the same time a portion of the thickness of the metal oxide dielectric layer of the light transmissive region; and removing the first conductive layer located in the transistor region to form the gate. The method of fabricating an active device array substrate according to claim 27, wherein the material of the metal oxide dielectric layer comprises indium oxide, zinc oxide, gallium oxide or any combination thereof.