CN102496617A - Active element array substrate and manufacturing method thereof - Google Patents
Active element array substrate and manufacturing method thereof Download PDFInfo
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- CN102496617A CN102496617A CN2011103789519A CN201110378951A CN102496617A CN 102496617 A CN102496617 A CN 102496617A CN 2011103789519 A CN2011103789519 A CN 2011103789519A CN 201110378951 A CN201110378951 A CN 201110378951A CN 102496617 A CN102496617 A CN 102496617A
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Images
Abstract
An active element array substrate comprises a soft substrate, a grid, a dielectric layer, a channel layer, a source electrode, a drain electrode and a pixel electrode. A transistor region and a light-transmitting region are defined on the flexible substrate. The transistor region is adjacent to the light-transmitting region. The grid is positioned on the soft substrate in the transistor area. The dielectric layer covers the gate and the flexible substrate. The part of the dielectric layer above the grid electrode has a first thickness. The part of the dielectric layer on the soft substrate in the light-transmitting area has a second thickness. The second thickness is less than the first thickness. The channel layer, the source electrode and the drain electrode are all positioned on the dielectric layer of the transistor area. The channel layer is positioned above the grid electrode. The source and the drain are located on two sides of the channel layer and are respectively electrically connected with the channel layer. The pixel electrode is positioned on the dielectric layer of the light-transmitting area. The pixel electrode is electrically connected with the drain electrode.
Description
Technical field
The invention relates to a kind of active component array base board and manufacturing approach thereof.
Background technology
Electrophoretic display device (EPD) (Electro-Phoretic Display; EPD) initial development is in the 1970's, and its characteristic is to comprise charged bead.The one side of this ball is a white, and another side then is a black.When electric field changed, club rotated up and down, and presented different colours.The electrophoretic display device (EPD) of the second generation is to be developed in generation nineteen ninety, and its characteristic is to replace traditional bead with microcapsules, and in capsule the oil (oil) and charged white particle of filling color.Make white particle up or move down via the control of external electric field, wherein when white particle up (near reader's direction time) then demonstrate white, when white particle down time the (away from reader's direction time) then shows fuel-displaced color.
In general, electrophoretic display device (EPD) is with the material of glass as its active component array base board mostly.Though this electrophoretic display device (EPD) has preferable hardness, weight lays particular stress on not portable, and the easy chipping problem of not anti-collision.
Recently, industry has been released with the electrophoretic display device (EPD) of plastic material as the active component array base board material, and this electrophoretic display device (EPD) itself has pliability to a certain degree, therefore can be used to replace traditional paper or advertisement plate.Because the material of active component array base board is a plastic cement, therefore technology is carried out for ease, and the producer need be fixed on the glass support plate active component array base board to be applicable to existing board.Yet; Because the thermal coefficient of expansion of plastic cement and the thermal coefficient of expansion of glass support plate; Even all differ very big with the thermal coefficient of expansion of inorganic dielectric layer (for example: gate dielectric layer, protective layer) on the active component array base board; Therefore when thermal process, cause the cumulative stress in active component array base board and the glass support plate easily, make active component array base board and glass support plate be out of shape and cause hitting sheet or board adsorbs the facts such as bad.
Summary of the invention
The present invention is providing a kind of active component array base board, and therefore the thinner thickness of the dielectric layer of its transparent area can provide under the prerequisite of enough protections, the deflection of active component array base board and glass support plate in the reduction technology.
According to an embodiment of the present invention, a kind of active component array base board comprises soft substrate plate, grid, dielectric layer, channel layer, source electrode, drain electrode and pixel electrode.Definition has transistor area and transparent area on the soft substrate plate.Transistor area is adjoined with transparent area mutually.Grid is positioned on the soft substrate plate of transistor area.Dielectric layer cover gate and soft substrate plate.The part dielectric layer that is positioned at the grid top has first thickness.The part dielectric layer that is positioned on the soft substrate plate of transparent area has second thickness.Second thickness is less than first thickness.Channel layer, source electrode and drain electrode all are positioned on the dielectric layer of transistor area.Channel layer is positioned at the top of grid.Source electrode and drain electrode are positioned at the channel layer both sides and electrically connect channel layer respectively.Pixel electrode is positioned on the dielectric layer of transparent area.This pixel electrode electrically connects drain electrode.
In one or more execution mode of the present invention, the material of above-mentioned soft substrate plate comprises plastic cement.
In one or more execution mode of the present invention, the material of above-mentioned soft substrate plate comprises polyimides (Polyimide; PI), PET (Polyethylene terephthalate; PET), gather 2,6-naphthalene diacid glycol ester (Polyethylene Naphthalate; PEN) or above-mentioned combination in any.
In one or more execution mode of the present invention, the material of above-mentioned dielectric layer comprises silicon nitride, silica, silicon oxynitride or above-mentioned combination in any.
In one or more execution mode of the present invention, said active element array substrate more comprises storage capacitors.Above-mentioned storage capacitors is positioned on the soft substrate plate, and this storage capacitors comprises bottom electrode, capacitance dielectric layer and top electrode.
In one or more execution mode of the present invention, above-mentioned capacitance dielectric layer is the part of dielectric layer.
In one or more execution mode of the present invention, said active element array substrate more comprises connection gasket.Above-mentioned connection gasket is positioned on the soft substrate plate, and this connection gasket comprises lower floor's connection gasket and upper strata connection gasket.
In one or more execution mode of the present invention, the material of above-mentioned channel layer comprises amorphous silicon, polysilicon, oxide semiconductor or above-mentioned combination in any.
In one or more execution mode of the present invention, said active element array substrate more comprises protective layer.This protective layer covers channel layer, source electrode and drain electrode.
In one or more execution mode of the present invention, the material of above-mentioned pixel electrode comprises indium tin oxide, indium-zinc oxide, aluminium zinc oxide or above-mentioned combination in any.
Another technological aspect of the present invention is that the manufacturing approach of said active element array substrate is being provided.
According to an embodiment of the present invention, a kind of manufacturing approach of active component array base board comprises the following steps (to should be appreciated that; Mentioned step in this execution mode; Except that chatting bright its order person especially, all can adjust its front and back order, even can carry out simultaneously simultaneously or partly according to actual needs):
(1) soft substrate plate is provided, definition has transistor area and transparent area on this soft substrate plate.
(2) on the transistor area of soft substrate plate, form grid.
(3) form dielectric layer and semiconductor layer in regular turn, this dielectric layer and semiconductor layer cover gate and soft substrate plate.
(4) remove the part semiconductor layer; To form channel layer in the grid top; And remove the part thickness of the dielectric layer be positioned at transparent area in the lump; Make the part dielectric layer that is positioned at grid top have first thickness, the part dielectric layer that is positioned on the soft substrate plate of transparent area has second thickness, and wherein second thickness is less than first thickness.
(5) form source electrode and drain electrode respectively in the both sides of channel layer, and electrically connect channel layer respectively.
(6) form protective layer, this protective layer covers channel layer, source electrode, drain electrode and dielectric layer.
(7) in protective layer, form the transistor contacts hole, exposing drain electrode respectively, and remove the protective layer that is positioned at transparent area simultaneously, to expose the dielectric layer that is positioned at transparent area.
(8) form pixel electrode being positioned on the dielectric layer of transparent area, this pixel electrode sees through the transistor contacts hole and electrically connects drain electrode.
In one or more execution mode of the present invention, the material of above-mentioned soft substrate plate comprises plastic cement.
In one or more execution mode of the present invention, the material of above-mentioned soft substrate plate comprises polyimides (Polyimide; PI), PET (Polyethylene terephthalate; PET), gather 2,6-naphthalene diacid glycol ester (Polyethylene Naphthalate; PEN) or above-mentioned combination in any.
In one or more execution mode of the present invention, the material of above-mentioned dielectric layer comprises silicon nitride, silica, silicon oxynitride or above-mentioned combination in any.
In one or more execution mode of the present invention, above-mentioned step (2) more comprises:
(2.1) form bottom electrode on soft substrate plate.
In one or more execution mode of the present invention, above-mentioned step (4) comprising:
(4.1) form photoresist layer, cover semiconductor layer.
(4.2) with halftoning light shield technology, make the photoresist layer patterning, form the patterning photoresist layer.
(4.3) serve as the cover curtain with the patterning photoresist layer, remove the semiconductor layer that transparent area exposes, remove the part photoresist layer of bottom electrode top simultaneously.
(4.4) serve as the cover curtain with remaining patterning photoresist layer, remove the part dielectric layer of transparent area, make the dielectric layer of transparent area have second thickness, remove the part semiconductor layer on the bottom electrode simultaneously.
In one or more execution mode of the present invention, above-mentioned step (5) more comprises:
(5.1) form top electrode on dielectric layer, and be positioned at the top of bottom electrode.
In one or more execution mode of the present invention, above-mentioned step (2) more comprises:
(2.2) form lower floor's connection gasket on soft substrate plate.
In one or more execution mode of the present invention, above-mentioned step (8) more comprises:
(8.1) form the upper strata connection gasket on lower floor's connection gasket.
Another execution mode according to the present invention; A kind of manufacturing approach of active component array base board; Comprise the following steps (to should be appreciated that mentioned step in this execution mode is except that chatting bright its order person especially; All can adjust its front and back order, even can carry out simultaneously simultaneously or partly according to actual needs):
(a) soft substrate plate is provided, definition has transistor area and transparent area on the soft substrate plate.
(b) on the transistor area of soft substrate plate, form grid.
(c) form dielectric layer, cover gate and soft substrate plate.
(d) on dielectric layer, form channel layer, source electrode and drain electrode, source electrode is formed at the both sides of channel layer respectively with drain electrode, and electrically connects channel layer respectively.
(e) form protective layer, protective layer covers channel layer, source electrode, drain electrode and dielectric layer.
(f) in protective layer, form the transistor contacts hole; To expose drain electrode respectively; And remove the protective layer that is positioned at transparent area simultaneously, and the dielectric layer of transparent area, make the part dielectric layer that is positioned at the grid top have first thickness; The part dielectric layer that is positioned on the soft substrate plate of transparent area has second thickness, and wherein second thickness is less than first thickness.
(g) form pixel electrode being positioned on the dielectric layer of transparent area, this pixel electrode sees through the transistor contacts hole and electrically connects drain electrode.
Description of drawings
For letting above-mentioned and other purposes of the present invention, characteristic, advantage and the embodiment can be more obviously understandable, appended graphic detailed description be following:
Fig. 1～9th is according to the manufacturing process profile of the active component array base board of first embodiment of the invention.
Figure 10～20th is according to the manufacturing process profile of the active component array base board of second embodiment of the invention.
Figure 21 illustrates the schematic top plan view according to the active component array base board of first and second execution mode of the present invention.
Description of reference numerals
110: soft substrate plate 112: transistor area
113: transparent area 114: capacitive region
116: connection gasket district 122: grid
124: bottom electrode 126: lower floor's connection gasket
130: dielectric layer 140: semiconductor layer
142: channel layer 150: ohmic contact layer
152: source electrode ohmic contact layer 154: the drain electrode ohmic contact layer
162: thick photoresist layer 164: thin photoresist layer
166: transistor etch-hole 167: the electric capacity etch-hole
168: connection gasket etch-hole 172: source electrode
174: drain electrode 176: top electrode
180: protective layer 182: the transistor contacts hole
184: electric capacity contact hole 186: the connection gasket contact hole
192: pixel electrode 194: the upper strata connection gasket
T1: 2: the second thickness of first thickness T
T3: 4: the four thickness of the 3rd thickness T
S: arrow I-I: zone
II-II: area I II-III: zone
I: line segment II: line segment
III: line segment
The practical implementation method
Below will disclose a plurality of execution mode of the present invention with graphic, for the purpose of offering some clarification on, the details on many practices will explanation in the lump in following narration.Yet, should be appreciated that the details on these practices is not used with restriction the present invention.That is to say that in part execution mode of the present invention, the details on these practices is inessential.In addition, for the purpose of simplicity of illustration, structure that some conventions are habitual and element will illustrate with the mode of simple signal in graphic.
First execution mode
The 1st～9 figure illustrates the manufacturing process profile according to the active component array base board of first embodiment of the invention.Figure 21 illustrates the schematic top plan view according to the active component array base board of first and second execution mode of the present invention.In the 1st～9 figure, the I-I zone illustrates along the section of the line segment I of Figure 21, and the II-II zone illustrates along the section of the line segment II of Figure 21, and the III-III zone illustrates along the section of the line segment III of Figure 21.Active component array base board of the present invention overlook design only in order to explanation, be not limited to above-mentioned graphicly, this field knows that usually the knowledgeable can suitably change design according to demand.
Please earlier with reference to Fig. 1.As shown in the figure, the producer can provide soft substrate plate 110 earlier at this moment, and this soft substrate plate 110 is preferably has pliability (flexible), makes the follow-up display floater that completes also have pliability.Can define transistor area 112, transparent area 113, the capacitive region 114 and connection gasket district 116 of adjoining mutually on this soft substrate plate 110 in advance.In one or more execution mode of the present invention; Subsequent technique operation for ease; The producer can be arranged at soft substrate plate 110 earlier and carry out technology on the glass support plate, treat that the active component array base board manufacturing is accomplished after, soft substrate plate 110 is peeled off from glass support plate taken off again.In this execution mode, the material of above-mentioned soft substrate plate 110 can comprise plastic cement, for example: polyimides (Polyimide; PI), PET (Polyethylene terephthalate; PET), gather 2,6-naphthalene diacid glycol ester (Polyethylene Naphthalate; Or other copolymer plastic materials PEN) or above-mentioned combination in any.Should be appreciated that, more than the material of the soft substrate plate 110 lifted all be merely illustration, be not in order to restriction the present invention, have common knowledge the knowledgeable in the technical field under the present invention, should look actual needs, elasticity is selected the material of soft substrate plate 110.
Then; The producer can form a patterning first conductive layer on soft substrate plate 110; For example be to form one first conductive layer earlier; With with little shadow and this first conductive layer of etch process patterning, on soft substrate plate 110, form patterning first conductive layer by this, comprise at least forming grid 122 on the transistor area 112; And patterning first conductive layer more comprises the gate line that connects grid 122, and in the capacitive region of soft substrate plate 110 114 and connection gasket district 116, forms bottom electrode 124 and lower floor's connection gasket 126 respectively.In this execution mode; First conductive layer (that is; Grid 122, bottom electrode 124 and lower floor's connection gasket 126) material can comprise above-mentioned combination in any or alloys such as titanium, molybdenum, chromium, iridium, aluminium, copper, silver, gold, its formation method can be physical vaporous deposition, like sputtering method; Or chemical vapour deposition technique, the method for patterning first conductive layer then can be little shadow and etching method.
Then please with reference to Fig. 2.As shown in the figure, the producer can form dielectric layer 130, semiconductor layer 140 and ohmic contact layer 150 at this moment in regular turn.Above-mentioned dielectric layer 130, semiconductor layer 140 and ohmic contact layer 150 cover gate 122, bottom electrode 124, lower floor's connection gasket 126 and soft substrate plate 110.The material of above-mentioned dielectric layer 130 can comprise silicon nitride, silica, silicon oxynitride or above-mentioned combination in any.The material of above-mentioned semiconductor layer 140 can comprise amorphous silicon, polysilicon, oxide semiconductor (oxide semiconductor) or above-mentioned combination in any.The material of above-mentioned ohmic contact layer 150 can comprise N type doped amorphous silicon or P type doped amorphous silicon etc.
Then, the producer can form photoresist layer on ohmic contact layer 150, and this photoresist layer covers ohmic contact layer 150 and is positioned at the semiconductor layer 140 under the ohmic contact layer 150.Then, the producer can halftoning light shield technology, makes the photoresist layer patterning, to form the patterning photoresist layer.Above-mentioned patterning photoresist layer can comprise thick photoresist layer 162 and thin photoresist layer 164.Thick photoresist layer 162 is positioned at transistor area 112 tops of soft substrate plate 110, and thin photoresist layer 164 lays respectively at the capacitive region 114 and 116 tops, connection gasket district of soft substrate plate 110.Transparent area 113 tops as for soft substrate plate 110 then are not have the photoresist layer protection.
Then please with reference to Fig. 3.As shown in the figure; The producer can be the cover curtain by patterning photoresist layer (comprising thick photoresist layer 162 and thin photoresist layer 164) at this moment; Remove semiconductor layer 140 and ohmic contact layer 150 that transparent area 113 tops expose, and remove the part thickness of the dielectric layer 130 of transparent area 113 tops exposure in the lump.In this execution mode, the concrete mode of removing semiconductor layer 140, ohmic contact layer 150 and dielectric layer 130 for example can be dry-etching or Wet-type etching.
Then please with reference to Fig. 4, as shown in the figure, the producer can remove the part photoresist layer of bottom electrode 124 and lower floor's connection gasket 126 tops at this moment.More particularly, the producer can remove thin photoresist layer 164 at this moment, and the thick photoresist layer 162 of while attenuate.In this execution mode, the method for removing thin photoresist layer 164 and the thick photoresist layer 162 of attenuate can be ashing (ashing).
Then please with reference to Fig. 5.As shown in the figure; The patterning photoresist layer that the producer can be left at this moment (that is; Thick photoresist layer 162 behind the attenuate) is the cover curtain; Remove the part dielectric layer 130 of transparent area 113, make the dielectric layer 130 of transparent area 113 have second thickness T 2, and remove the part semiconductor layer 140 and ohmic contact layer 150 of bottom electrode 124 and lower floor's connection gasket 126 tops simultaneously.In this execution mode, the concrete mode of removing semiconductor layer 140, ohmic contact layer 150 and dielectric layer 130 for example can be dry-etching or Wet-type etching.In addition, after this step was accomplished, the producer can stripper (stripper) removes remaining patterning photoresist layer (that is, the thick photoresist layer 162 behind the attenuate).
In this execution mode, the dielectric layer 130 of transparent area 113 tops is to adopt two-stage etching.In the phase I that Fig. 3 illustrated, the dielectric layer 130 of transparent area 113 tops can be by preliminary attenuate.And in the second stage that Fig. 5 illustrated, also can etch into the dielectric layer 130 of transparent area 113 tops during owing to etching semiconductor layer 140 and ohmic contact layer 150, so the dielectric layer 130 of transparent area 113 tops also can be thinned to second thickness T 2 further.
Should be appreciated that; Though this execution mode uses halftoning light shield technology for the usage quantity that reduces light shield in the technology of the 2nd～5 figure; But this does not limit the present invention, has common knowledge the knowledgeable in the technical field under the present invention, also can be according to actual needs; Use one light shield technology to remove the part dielectric layer 130 of transparent area 113, and use another road light shield technology to remove the part semiconductor layer 140 and ohmic contact layer 150 of bottom electrode 124 and lower floor's connection gasket 126 tops.
After the technology of Fig. 5; Grid 122 tops will form the channel layer 142 that is made up of semiconductor layer 140; And the part dielectric layer 130 that is positioned at grid 122 tops has first thickness T 1, and the part dielectric layer 130 that is positioned on the soft substrate plate 110 of transparent area 113 has second thickness T 2.This second thickness T 2 is less than first thickness T 1, and this second thickness T 2, and is preferably between 0.1～0.8 between 0.05～0.95 with respect to the ratio of first thickness T 1, and better be between 0.3～0.6.In addition; Because in Fig. 4; Thick photoresist layer 162 of ashing and thin photoresist layer 164 are with cause contract in the thick photoresist layer 162 (shown in arrow S) unavoidablely; Therefore subsequent etch technology will hurt the dielectric layer 130 of top, transistor area 112 edges, makes the dielectric layer 130 of top, transistor area 112 edges have the 3rd thickness T 3, and this 3rd thickness T 3 less than the thickness of the dielectric layer 130 of transistor area 112 central authorities tops (for example: first thickness T 1).In addition, if having barrier layer on the soft substrate plate 110, this barrier layer also possibly hurt by subsequent etch technology, makes that the thickness of barrier layer is different.
Then please with reference to Fig. 6.As shown in the figure, the producer can form source electrode 172 and drain electrode 174 at this moment in the both sides of channel layer 142 respectively, and can on dielectric layer 130, form data line and the top electrode 176 that connects source electrode 172, and this top electrode 176 is positioned at the top of bottom electrode 124.Above-mentioned source electrode 172 electrically connects channel layer 142 respectively with drain electrode 174.Particularly, the producer can form second conductive layer earlier at this moment above soft substrate plate 110, and this second conductive layer covers structures all on the soft substrate plate 110 comprehensively.Then, this second conductive layer of producer's patternable forms source electrode 172 and drain electrode 174 by this respectively in the both sides of channel layer 142, and on the dielectric layer 130 of bottom electrode 124 tops, forms top electrode 176.In the process of patterning second conductive layer, the producer can select the ohmic contact layer 150 between downward in the lump etching source electrode 172 and the drain electrode 174, makes ohmic contact layer 150 break off and the formation source electrode ohmic contact layer 152 and the ohmic contact layer 154 that drains.The foregoing description is to be that example describes with source electrode 172 with drain electrode 174 cover part channel layers 142; In an alternate embodiment; Channel layer 142 also can cover partly source electrode 172 and drain electrode 174, only needs the adjusting process order, and uses the twice light shield to define its pattern respectively; This knows usually that by this area the knowledgeable is known, and therefore repeats no more.
In this execution mode; Second conductive layer (that is; Source electrode 172, the drain electrode 174 with top electrode 176) material can comprise above-mentioned combination in any or alloys such as titanium, molybdenum, chromium, iridium, aluminium, copper, silver, gold, its formation method can be physical vaporous deposition, like sputtering method; Or chemical vapour deposition technique, the method for patterning second conductive layer then can be little shadow and etching method.
After the technology of Fig. 6; Dielectric layer 130 on grid 122, the grid 122 (that is; Gate dielectric layer), channel layer 142, source electrode ohmic contact layer 152, drain electrode ohmic contact layer 154, source electrode 172 will constitute thin-film transistor with drain electrode 174; And the dielectric layer 130 on the bottom electrode 124, bottom electrode 124 (that is, capacitance dielectric layer) will constitute storage capacitors with top electrode 176.Should be appreciated that; Though the disclosed source electrode 172 of this execution mode all stacks in channel layer 142 tops with drain electrode 174; But has common knowledge the knowledgeable in the technical field under the present invention; The enforcement aspect of also visual actual conditions adjustment thin-film transistor, for example in part execution mode of the present invention, channel layer also can stack in source electrode and constitute thin-film transistor with the drain electrode top.
Then please with reference to Fig. 7.As shown in the figure, the producer can form protective layer 180 at this moment, and this protective layer 180 covers source electrode 172, channel layer 142, drain electrode 174, dielectric layer 130 and top electrode 176.In this execution mode, the material of above-mentioned protective layer 180 can comprise silicon nitride, silica, silicon oxynitride or above-mentioned combination in any.
Then please with reference to Fig. 8.As shown in the figure; The producer can form transistor contacts hole 182, electric capacity contact hole 184 and connection gasket contact hole 186 at this moment in protective layer 180; To expose drain electrode 174, top electrode 176 and lower floor's connection gasket 126 respectively; And remove the protective layer 180 that is positioned at transparent area 113 simultaneously, to expose the dielectric layer 130 that is positioned at transparent area 113.In this execution mode, formation transistor contacts hole 182, electric capacity contact hole 184 can be little shadow and etching method with the method that connection gasket contact hole 186 and removal are positioned at the protective layer 180 of transparent area 113.
Then please with reference to Fig. 9.As shown in the figure, the producer can form pixel electrode 192 at this moment on the dielectric layer that is positioned at transparent area 113 130.This pixel electrode 192 can see through transistor contacts hole 182 respectively and electrically connect drain electrode 174 and top electrode 176 with electric capacity contact hole 184.At the same time, the producer also can form upper strata connection gasket 194 on lower floor's connection gasket 126.Particularly, the producer can form transparency conducting layer earlier at this moment above soft substrate plate 110, and this transparency conducting layer covers structures all on the soft substrate plate 110 comprehensively.Then, this transparency conducting layer of producer's patternable forms pixel electrode 192 and upper strata connection gasket 194 by this.In this execution mode, the material of above-mentioned transparency conducting layer (that is, pixel electrode 192 and upper strata connection gasket 194) can comprise indium tin oxide, indium-zinc oxide, aluminium zinc oxide or above-mentioned combination in any.After the technology of Fig. 9, lower floor's connection gasket 126 will constitute connection gasket with upper strata connection gasket 194, and this connection gasket is positioned in the connection gasket district 116 of soft substrate plate 110, in order to connect external circuit.
In the first embodiment; Because second thickness T 2 of the dielectric layer 130 of transparent area 113 is thinner; Therefore can reduce dielectric layer 130 influence that cumulative stress caused in thermal process, and and then the deflection that reduces soft substrate plate 110 and take advantage of the glass support plate of carrying soft substrate plate 110.In addition; Owing to still have dielectric layer 130 on the transparent area 113, so this execution mode still can provide active component array base board enough protections, in the follow-up semiconductor technology of dielectric layer 130; Because transparent area 113 tops still have part dielectric layer 130 to exist; Therefore can avoid soft substrate plate 110 to receive the destruction of follow-up semiconductor technology, cause surface roughening, reduce display quality.Moreover because this execution mode use halftoning light shield technology reduces the use amount of light shield, so the producer can reduce the influence that dielectric layer 130 cumulative stress are caused under the unlikely situation about significantly rising of manufacturing cost.
Second execution mode
The 10th～20 figure illustrates the manufacturing process profile according to the active component array base board of second embodiment of the invention.Figure 21 illustrates the schematic top plan view according to the active component array base board of first and second execution mode of the present invention.In the 10th～20 figure, the I-I zone illustrates along the section of the line segment I of Figure 21, and the II-II zone illustrates along the section of the line segment II of Figure 21, and the III-III zone illustrates along the section of the line segment III of Figure 21.
Please earlier with reference to Figure 10.As shown in the figure, the producer can provide soft substrate plate 110 earlier at this moment, and this soft substrate plate 110 is preferably has pliability (flexible), makes the follow-up display floater that completes also have pliability.Can define transistor area 112, transparent area 113, the capacitive region 114 and connection gasket district 116 of adjoining mutually on this soft substrate plate 110 in advance.In one or more execution mode of the present invention; Subsequent technique operation for ease; The producer can be arranged at soft substrate plate 110 earlier and carry out technology on the glass support plate, treat that the active component array base board manufacturing is accomplished after, soft substrate plate 110 is peeled off from glass support plate taken off again.In this execution mode, the material of above-mentioned soft substrate plate 110 can comprise plastic cement, for example: polyimides (Polyimide; PI), PET (Polyethylene terephthalate; PET), gather 2,6-naphthalene diacid glycol ester (Polyethylene Naphthalate; Or other copolymer plastic materials PEN) or above-mentioned combination in any.Should be appreciated that, more than the material of the soft substrate plate 110 lifted all be merely illustration, be not in order to restriction the present invention, have common knowledge the knowledgeable in the technical field under the present invention, should look actual needs, elasticity is selected the material of soft substrate plate 110.
Then; The producer can form a patterning first conductive layer on soft substrate plate 110; For example can form first conductive layer earlier; With with little shadow and this first conductive layer of etch process patterning, on soft substrate plate 110, form patterning first conductive layer by this, comprise at least forming grid 122 on the transistor area 112; And patterning first conductive layer more comprises the gate line that connects grid 122, and in the capacitive region of soft substrate plate 110 114 and connection gasket district 116, forms bottom electrode 124 and lower floor's connection gasket 126 respectively.In this execution mode; First conductive layer (that is; Grid 122, bottom electrode 124 and lower floor's connection gasket 126) material can comprise above-mentioned combination in any or alloys such as titanium, molybdenum, chromium, iridium, aluminium, copper, silver, gold, its formation method can be physical vaporous deposition, like sputtering method; Or chemical vapour deposition technique, the method for patterning first conductive layer then can be little shadow and etching method.
Then please with reference to Figure 11.As shown in the figure, the producer can form dielectric layer 130, semiconductor layer 140 and ohmic contact layer 150 at this moment in regular turn.Above-mentioned dielectric layer 130, semiconductor layer 140 and ohmic contact layer 150 cover gate 122, bottom electrode 124, lower floor's connection gasket 126 and soft substrate plate 110.The material of above-mentioned dielectric layer 130 can comprise silicon nitride, silica, silicon oxynitride or above-mentioned combination in any.The material of above-mentioned semiconductor layer 140 can comprise amorphous silicon, polysilicon, oxide semiconductor (oxide semiconductor) or above-mentioned combination in any.The material of above-mentioned ohmic contact layer 150 can comprise N type doped amorphous silicon or P type doped amorphous silicon etc.
Then please with reference to Figure 12.As shown in the figure; The producer is patternable semiconductor layer 140 and ohmic contact layer 150 at this moment; With the semiconductor layer 140 and ohmic contact layer 150 of removing transparent area 113, capacitive region 114 and 116 tops, connection gasket district; And only stay the semiconductor layer 140 and ohmic contact layer 150 of transistor area 112 tops, wherein the semiconductor layer 140 of transistor area 112 tops will be as channel layer 142 usefulness.In this execution mode, patterned semiconductor layer 140 can be little shadow and etching method with the method for ohmic contact layer 150.
Then please with reference to Figure 13.As shown in the figure, the producer can form source electrode 172 and drain electrode 174 at this moment in the both sides of channel layer 142 respectively, and on dielectric layer 130, forms top electrode 176, and this top electrode 176 is positioned at the top of bottom electrode 124.Above-mentioned source electrode 172 electrically connects channel layer 142 respectively with drain electrode 174.Particularly, the producer can form second conductive layer earlier at this moment above soft substrate plate 110, and this second conductive layer covers structures all on the soft substrate plate 110 comprehensively.Then; This second conductive layer of producer's patternable; Form source electrode 172 and drain electrode 174 by this respectively in the both sides of channel layer 142, and can be in forming the data line that connects source electrode 172 on the dielectric layer 130 and on the dielectric layer above the bottom electrode 124 130, forming top electrode 176.In the process of patterning second conductive layer, the producer can select the ohmic contact layer 150 between downward in the lump etching source electrode 172 and the drain electrode 174, makes ohmic contact layer 150 break off and the formation source electrode ohmic contact layer 152 and the ohmic contact layer 154 that drains.The foregoing description is to be that example describes with source electrode 172 with drain electrode 174 cover part channel layers 142; In an alternate embodiment; Channel layer 142 also can cover partly source electrode 172 and drain electrode 174, only needs the adjusting process order, and uses the twice light shield to define its pattern respectively; This knows usually that by this area the knowledgeable is known, and therefore repeats no more.
In this execution mode; Second conductive layer (that is; Source electrode 172, the drain electrode 174 with top electrode 176) material can comprise above-mentioned combination in any or alloys such as titanium, molybdenum, chromium, iridium, aluminium, copper, silver, gold, its formation method can be physical vaporous deposition, like sputtering method; Or chemical vapour deposition technique, the method for patterning second conductive layer then can be little shadow and etching method.
After the technology of Figure 13; Because channel layer 142, source electrode 172 have been formed on the dielectric layer 130 with drain electrode 174; Therefore the dielectric layer 130 on grid 122, the grid 122 (that is; Gate dielectric layer), channel layer 142, source electrode ohmic contact layer 152, drain electrode ohmic contact layer 154, source electrode 172 will constitute thin-film transistor with drain electrode 174, and dielectric layer 130 on the bottom electrode 124, bottom electrode 124 (that is, capacitance dielectric layer) and top electrode 176 will constitute storage capacitors.Should be appreciated that; Though the disclosed source electrode 172 of this execution mode all stacks in channel layer 142 tops with drain electrode 174; But has common knowledge the knowledgeable in the technical field under the present invention; The enforcement aspect of also visual actual conditions adjustment thin-film transistor, for example in part execution mode of the present invention, channel layer also can stack in source electrode and constitute thin-film transistor with the drain electrode top.
Then please with reference to Figure 14.As shown in the figure, the producer can form protective layer 180 at this moment, and this protective layer 180 covers source electrode 172, channel layer 142, drain electrode 174, dielectric layer 130 and top electrode 176.In this execution mode, the material of above-mentioned protective layer 180 can comprise silicon nitride, silica, silicon oxynitride or above-mentioned combination in any.
Then, the producer can form photoresist layer on protective layer 180, this photoresist layer protective mulch 180.Then, the producer can halftoning light shield technology, makes the photoresist layer patterning, to form the patterning photoresist layer.Above-mentioned patterning photoresist layer can comprise thick photoresist layer 162 and thin photoresist layer 164.Thick photoresist layer 162 lays respectively at transistor area 112, the capacitive region 114 and 116 tops, connection gasket district of soft substrate plate 110, and thin photoresist layer 164 is positioned at transparent area 113 tops of soft substrate plate 110.In addition; Be formed with transistor etch-hole 166, electric capacity etch-hole 167 and connection gasket etch-hole 168 in the thick photoresist layer 162, it exposes protective layer 180, the protective layer 180 of top electrode 176 tops and the protective layer 180 of lower floor's connection gasket 126 tops of drain electrode 174 tops respectively.
Then please with reference to Figure 16.As shown in the figure; The producer can be the cover curtain by patterning photoresist layer (comprising thick photoresist layer 162 and thin photoresist layer 164) at this moment; In protective layer 180, form transistor contacts hole 182, electric capacity contact hole 184 and connection gasket contact hole 186, to expose drain electrode 174, top electrode 176 and lower floor's connection gasket 126 respectively.In this execution mode, the concrete mode that forms transistor contacts hole 182, electric capacity contact hole 184 and connection gasket contact hole 186 for example can be dry-etching or Wet-type etching.
Then please with reference to Figure 17, as shown in the figure, the producer can remove thin photoresist layer 164, and the thick photoresist layer 162 of while attenuate, to expose the protective layer 180 of transparent area 113 tops.In this execution mode, the method for removing thin photoresist layer 164 and the thick photoresist layer 162 of attenuate can be ashing (ashing).
Then please with reference to Figure 18.As shown in the figure; The patterning photoresist layer that the producer can be left at this moment (that is; Thick photoresist layer 162 behind the attenuate) for the cover curtain, remove the protective layer 180 that is positioned at transparent area 113, and the dielectric layer 130 of transparent area 113; Make the part dielectric layer 130 that is positioned at grid 122 tops have first thickness T 1, the part dielectric layer 130 that is positioned on the soft substrate plate 110 of transparent area 113 has second thickness T 2.This second thickness T 2 is less than first thickness T 1, and this second thickness T 2, and is preferably between 0.1～0.8 between 0.05～0.95 with respect to the ratio of first thickness T 1, and better be between 0.3～0.6.In this execution mode, the concrete mode of removing protective layer 180 and dielectric layer 130 for example can be dry-etching or Wet-type etching.
Should be appreciated that; Though this execution mode uses halftoning light shield technology for the usage quantity that reduces light shield in the technology of the 15th～18 figure; But this does not limit the present invention; Have common knowledge the knowledgeable in the technical field under the present invention, also can use one light shield technology to form transistor contacts hole 182, electric capacity contact hole 184 and connection gasket contact hole 186 according to actual needs; And use another road light shield technology to remove the protective layer 180 that is positioned at transparent area 113, and the dielectric layer 130 of transparent area 113.
In addition; Because in Figure 17; Thick photoresist layer 162 of ashing and thin photoresist layer 164 are with cause contract in the thick photoresist layer 162 (shown in arrow S) unavoidablely; Therefore subsequent etch technology will hurt the protective layer 180 of top, transistor area 112 edges, makes the protective layer 180 of top, transistor area 112 edges have the 4th thickness T 4, and this 4th thickness T 4 less than the thickness of the protective layer 180 of transistor area 112 central authorities tops (for example: the 3rd thickness T 3).In addition, if having barrier layer on the soft substrate plate 110, this barrier layer also possibly hurt by subsequent etch technology, makes that the thickness of barrier layer is different.
Then please with reference to Figure 19.As shown in the figure, the producer at this moment can stripper (stripper) removes remaining patterning photoresist layer (that is, the thick photoresist layer 162 behind the attenuate).
Then please with reference to Figure 20.As shown in the figure, the producer can form pixel electrode 192 at this moment on the dielectric layer that is positioned at transparent area 113 130.This pixel electrode 192 can see through transistor contacts hole 182 respectively and electrically connect drain electrode 174 and top electrode 176 with electric capacity contact hole 184.At the same time, the producer also can form upper strata connection gasket 194 on lower floor's connection gasket 126.Particularly, the producer can form transparency conducting layer earlier at this moment above soft substrate plate 110, and this transparency conducting layer covers structures all on the soft substrate plate 110 comprehensively.Then, this transparency conducting layer of producer's patternable forms pixel electrode 192 and upper strata connection gasket 194 by this.In this execution mode, the material of above-mentioned transparency conducting layer (that is, pixel electrode 192 and upper strata connection gasket 194) can comprise indium tin oxide, indium-zinc oxide, aluminium zinc oxide or above-mentioned combination in any.After the technology of Figure 20, lower floor's connection gasket 126 will constitute connection gasket with upper strata connection gasket 194, and this connection gasket is positioned in the connection gasket district 116 of soft substrate plate 110, in order to connect external circuit.
Likewise; In second execution mode; Because second thickness T 2 of the dielectric layer 130 of transparent area 113 is thinner, therefore can reduce dielectric layer 130 influence that cumulative stress caused in thermal process, and and then the deflection that reduces soft substrate plate 110 and take advantage of the glass support plate of carrying soft substrate plate 110.In addition; Owing to still have dielectric layer 130 on the transparent area 113, so this execution mode still can provide active component array base board enough protections, in the follow-up semiconductor technology of dielectric layer 130; Because transparent area 113 tops still have part dielectric layer 130 to exist; Therefore can avoid soft substrate plate 110 to receive the destruction of follow-up semiconductor technology, cause surface roughening, reduce display quality.Moreover because this execution mode use halftoning light shield technology reduces the use amount of light shield, so the producer can reduce the influence that dielectric layer 130 cumulative stress are caused under the unlikely situation about significantly rising of manufacturing cost.
Active component array base board of the present invention can provide bendable substrate, follow-uply can be made into various flat-panel screens, for example LCD, OLED, electrophoretic display device (EPD) or the like.Can make above-mentioned flat-panel screens have the characteristic of flexible equally, promote the range of application of flat-panel screens.
Though the present invention with execution mode openly as above; Right its is not in order to limit the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention, and when can doing various changes and retouching, so protection scope of the present invention is as the criterion with claims.
Claims (20)
1. active component array base board comprises:
One soft substrate plate, definition has at least one transistor area and at least one transparent area on this soft substrate plate, and this transistor area is adjoined with this transparent area mutually;
One grid is positioned on this soft substrate plate of this transistor area;
One dielectric layer; Cover this grid and this soft substrate plate; This dielectric layer of part that is positioned at this grid top has one first thickness, and this dielectric layer of part that is positioned on this soft substrate plate of this transparent area has one second thickness, and wherein this second thickness is less than this first thickness;
One channel layer, one source pole and a drain electrode are positioned on this dielectric layer of this transistor area, and this channel layer is positioned at the top of this grid, and this source electrode and this drain electrode are positioned at these channel layer both sides and electrically connect this channel layer respectively; And
One pixel electrode is positioned on this dielectric layer of this transparent area, and this pixel electrode electrically connects should drain electrode.
2. active component array base board as claimed in claim 1 is characterized in that the material of this soft substrate plate comprises plastic cement.
3. active component array base board as claimed in claim 1 is characterized in that the material of this soft substrate plate comprises polyimides (Polyimide; PI), PET (Polyethyleneterephthalate; PET), gather 2,6-naphthalene diacid glycol ester (Polyethylene Naphthalate; PEN) or above-mentioned combination in any.
4. active component array base board as claimed in claim 1 is characterized in that, the material of this dielectric layer comprises silicon nitride, silica, silicon oxynitride or above-mentioned combination in any.
5. active component array base board as claimed in claim 1 is characterized in that, further comprises at least one storage capacitors, and this storage capacitors is positioned on this soft substrate plate, and this storage capacitors comprises a bottom electrode, a capacitance dielectric layer and a top electrode.
6. active component array base board as claimed in claim 5 is characterized in that, this capacitance dielectric layer is the part of this dielectric layer.
7. active component array base board as claimed in claim 1 is characterized in that, further comprises at least one connection gasket, and this connection gasket is positioned on this soft substrate plate, and this connection gasket comprises a lower floor's connection gasket and a upper strata connection gasket.
8. active component array base board as claimed in claim 1 is characterized in that, the material of channel layer comprises amorphous silicon, polysilicon, oxide semiconductor or above-mentioned combination in any.
9. active component array base board as claimed in claim 1 is characterized in that, comprises that further a protective layer covers this channel layer, this source electrode and this drain electrode.
10. active component array base board as claimed in claim 1 is characterized in that, the material of this pixel electrode comprises indium tin oxide, indium-zinc oxide, aluminium zinc oxide or above-mentioned combination in any.
11. the manufacturing approach of an active component array base board comprises the following steps:
One soft substrate plate is provided, and definition has at least one transistor area and at least one transparent area on this soft substrate plate;
On this transistor area of this soft substrate plate, form a grid;
Form a dielectric layer and semi-conductor layer in regular turn, this dielectric layer and this semiconductor layer cover this grid and this soft substrate plate;
Remove this semiconductor layer of part; To form a channel layer in this grid top; And remove the part thickness of this dielectric layer be positioned at this transparent area in the lump; Make this dielectric layer of part that is positioned at this grid top have one first thickness, this dielectric layer of part that is positioned on this soft substrate plate of this transparent area has one second thickness, and wherein this second thickness is less than this first thickness;
Form an one source pole and a drain electrode respectively in the both sides of this channel layer, and electrically connect this channel layer respectively;
Form a protective layer, this protective layer covers this channel layer, this source electrode, this drain electrode and this dielectric layer;
In this protective layer, form a transistor contacts hole, exposing this drain electrode respectively, and removal simultaneously is positioned at this protective layer of this transparent area, to expose this dielectric layer that is positioned at this transparent area; And
Be positioned at formation one pixel electrode on this dielectric layer of this transparent area, this pixel electrode sees through this transistor contacts hole and electrically connects and should drain.
12. the manufacturing approach of active component array base board as claimed in claim 11 is characterized in that, the material of this soft substrate plate comprises plastic cement.
13. the manufacturing approach of active component array base board as claimed in claim 11 is characterized in that, the material of this soft substrate plate comprises polyimides (Polyimide; PI), PET (Polyethylene terephthalate; PET), gather 2,6-naphthalene diacid glycol ester (PolyethyleneNaphthalate; PEN) or above-mentioned combination in any.
14. the manufacturing approach of active component array base board as claimed in claim 11 is characterized in that, the material of this dielectric layer comprises silicon nitride, silica, silicon oxynitride or above-mentioned combination in any.
15. the manufacturing approach of active component array base board as claimed in claim 11 is characterized in that, on this transistor area of this soft substrate plate, forms the step of this grid, more comprises forming a bottom electrode on this soft substrate plate.
16. the manufacturing approach of active component array base board as claimed in claim 15 is characterized in that, removes the step of this semiconductor layer of part and this dielectric layer, comprising:
Form a photoresist layer, cover this semiconductor layer;
With a halftoning light shield technology, make this photoresist layer patterning, form a patterning photoresist layer;
With this patterning photoresist layer is the cover curtain, removes this semiconductor layer that this transparent area exposes, and removes this photoresist layer of part of this bottom electrode top simultaneously; And
With this remaining patterning photoresist layer is the cover curtain, removes this dielectric layer of part of this transparent area, makes this dielectric layer of transparent area have this second thickness, removes this semiconductor layer of part on this bottom electrode simultaneously.
17. the manufacturing approach of active component array base board as claimed in claim 15 is characterized in that, forms the step of this source electrode and this drain electrode respectively in the both sides of this channel layer, more comprises forming a top electrode on this dielectric layer, and is positioned at the top of this bottom electrode.
18. the manufacturing approach of active component array base board as claimed in claim 11 is characterized in that, on this transistor area of this soft substrate plate, forms the step of this grid, more comprises forming lower floor's connection gasket on this soft substrate plate.
19. the manufacturing approach of active component array base board as claimed in claim 18 is characterized in that, is being positioned at the step that forms this pixel electrode on this dielectric layer of this transparent area, more comprises forming a upper strata connection gasket on this lower floor's connection gasket.
20. the manufacturing approach of an active component array base board comprises the following steps:
One soft substrate plate is provided, and definition has at least one transistor area and at least one transparent area on this soft substrate plate;
On this transistor area of this soft substrate plate, form a grid;
Form a dielectric layer, cover this grid and this soft substrate plate;
On this dielectric layer, form a channel layer, one source pole and a drain electrode, this source electrode and this drain electrode are formed at the both sides of this channel layer respectively, and electrically connect this channel layer respectively;
Form a protective layer, this protective layer covers this channel layer, this source electrode, this drain electrode and this dielectric layer;
In this protective layer, form a transistor contacts hole; To expose this drain electrode respectively; And remove this protective layer that is positioned at this transparent area simultaneously, and this dielectric layer of this transparent area, make this dielectric layer of part that is positioned at this grid top have one first thickness; This dielectric layer of part that is positioned on this soft substrate plate of this transparent area has one second thickness, and wherein this second thickness is less than this first thickness; And
Be positioned at formation one pixel electrode on this dielectric layer of this transparent area, this pixel electrode sees through this transistor contacts hole and electrically connects and should drain.
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| WO2019051863A1 (en) * | 2017-09-15 | 2019-03-21 | 惠科股份有限公司 | Method for manufacturing active array switch |
| WO2021147033A1 (en) * | 2020-01-22 | 2021-07-29 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display device |
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| US20080213949A1 (en) * | 2007-01-02 | 2008-09-04 | Au Optronics Corp. | Method for manufacturing array substrate |
| CN102184928A (en) * | 2010-12-29 | 2011-09-14 | 友达光电股份有限公司 | Display element and method for manufacturing the same |
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| TW201119110A (en) * | 2009-11-18 | 2011-06-01 | Metal Ind Res & Dev Ct | Fabrication method of organic thin-film transistors |
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| US20080018850A1 (en) * | 2006-07-20 | 2008-01-24 | Au Optronics Corp. | Array substrate and method for fabricating thereof |
| US20080213949A1 (en) * | 2007-01-02 | 2008-09-04 | Au Optronics Corp. | Method for manufacturing array substrate |
| CN102184928A (en) * | 2010-12-29 | 2011-09-14 | 友达光电股份有限公司 | Display element and method for manufacturing the same |
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| WO2019051863A1 (en) * | 2017-09-15 | 2019-03-21 | 惠科股份有限公司 | Method for manufacturing active array switch |
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| TW201316515A (en) | 2013-04-16 |
| TWI491040B (en) | 2015-07-01 |
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Application publication date: 20120613 |