TWI489569B - Method for forming elements of semiconductor package - Google Patents

Description

Component manufacturing method for semiconductor package structure

The invention relates to a circuit layer manufacturing method, in particular to a component manufacturing method of a semiconductor package structure.

With the rapid development of the electronics industry, with the advancement of semiconductor process technology, more sub-components are integrated into the semiconductor wafer, and the performance of the wafer is better, so the input/output connection (I/O) is set on the wafer. The number of connections) is increasing. For a fine pitch wafer size, there are both thin lines (line width less than 10 μm) and large-sized open areas (diameter width greater than 200 μm).

Please refer to FIGS. 1A to 1D, which are schematic cross-sectional views showing the manufacturing method of the conventional semiconductor package structure 1.

As shown in FIG. 1A, a substrate 10 has a plurality of electrode pads 100 and a passivation layer 101, and the passivation layer 101 is formed with a plurality of openings 101a to correspondingly expose the electrode pads 100.

Next, a metal layer 12 is formed on the electrode pads 100 and the passivation layer 101, and the metal layer 12 defines a plurality of line portions 12a and an open portion 12b.

As shown in FIG. 1B, a resist layer 13 is formed on the line of the metal layer 12. On 12a.

As shown in FIG. 1C, the open portion 12b and other metal layers are not wet-covered by the etching solution, and the line portion 12a under the resist layer 13 is used as the wiring layer 14.

The resist layer 13 is removed as shown in FIG. 1D.

In the method of fabricating the semiconductor package structure 1, when wet etching is performed, the wet etching generates an isotropic etching, so the etching time needs to be controlled to avoid the etching time being too long to cause the wiring layer 14 to be etched. Open circuit.

However, when wet etching, the flow field of the etching liquid is relatively easy to be located at the edge of the open portion 12b, and does not easily flow to the central portion of the open portion 12b, that is, it cannot be uniformly distributed on the open portion 12b, so that the empty space is caused. The amount of etching of the portion 12b is not uniform, and thus the excess void portion 12b', particularly the central portion of the open portion 12b, results in poor product yield and yield.

Further, when the excess vacant portion 12b' is left, the remaining vacant portion 12b' is subsequently removed, and a large amount of etching liquid is required to be surely removed, which not only increases the amount of the etching liquid but also easily damages the surrounding structure.

Moreover, in order to cooperate with the fabrication of the circuit layer 14, after the etching is stopped, the open portion 12b is not completely removed due to the excessive exposed area, so that excessive residual hollow portions 12b', especially the central portion of the open portion 12b, are generated. Therefore, the electrical properties are affected. For example, the area of the residual open space portion 12b' is too large and the connection to the circuit layer 14 causes a short circuit, resulting in poor yield and yield of the product.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned various deficiencies of the prior art, the present invention provides a method for fabricating a semiconductor package structure, comprising: providing a substrate having a plurality of electrode pads and a passivation layer, wherein the passivation layer exposes the electrode pads; forming a metal layer thereon An electrode pad and the passivation layer, wherein the metal layer defines a wire portion and a hollow portion; forming a first resistance layer on the line portion of the metal layer, and forming a second resistance layer on a portion of the space portion of the metal layer; etching Removing the metal layer without covering the open portion of the second resist layer, using the line portion of the metal layer as a circuit layer, and electrically connecting the circuit layer to the electrode pads; and removing the first and second layers Resistance layer.

In the above-described component manufacturing method, the substrate is a wafer, an interposer or a wafer on which internal wiring has been fabricated.

In the above method of fabricating the substrate, the process of the substrate includes: cutting the wafer to obtain a plurality of wafers; and rearranging each of the wafers on a carrier and using at least one wafer as the substrate.

In the above component manufacturing method, the passivation layer is formed with a plurality of openings to correspondingly expose the electrode pads.

In the above component manufacturing method, the second resistive layer is a plurality of blocks, for example, a column, and the column systems are cylindrical or elliptical columns having a maximum diameter of not more than 3 μm.

In the above member manufacturing method, the second resist layer is located in a central region of the open portion.

In the above component manufacturing method, the second resist layer occupies 20 to 45% of the surface area of the open portion.

In the above component manufacturing method, the circuit layer is a line redistribution layer.

In addition, in the foregoing component manufacturing method, after removing the first and second resist layers, the remaining open portions are removed, for example, the remaining open portions are removed by wet etching.

As can be seen from the above, the method for fabricating the semiconductor package structure of the present invention is formed on a portion of the open portion by the second resist layer, so that the etching solution flows to the first and second resist layers during wet etching. Therefore, compared with the prior art, the method of the present invention can etch most of the area of the open portion to greatly reduce the residual amount of the open portion, thereby improving product yield and yield.

Moreover, since there is very little open space, when the remaining space is subsequently removed, only a small amount of etching liquid can be used to quickly and surely remove the remaining air, which not only reduces the amount of etching liquid but also does not damage the surrounding area. The structure.

Moreover, the second resist layer is formed on the open portion to reduce the exposed area of the open portion. Therefore, after the etching of the circuit layer is completed and the etching is stopped, the exposed area of the open portion is substantially removed. Only a few empty pockets remain, thus greatly reducing the possibility of affecting electrical properties, thus effectively improving the yield and yield of the product.

1,2,2'‧‧‧ semiconductor package structure

10,20‧‧‧substrate

100,200‧‧‧electrode pads

101,201‧‧‧ Passivation layer

101a, 201a‧‧‧ Opening

12,22‧‧‧metal layer

12a, 22a‧‧‧Line

12b, 12b’, 22b, 22b’ ‧ ‧ Air Force

13‧‧‧resist

14,24,24’‧‧‧ circuit layer

20’‧‧‧ wafer

20a‧‧‧ Ontology

23a‧‧‧First barrier layer

23b‧‧‧second barrier layer

240‧‧‧ dielectric layer

241‧‧‧Line redistribution

25‧‧‧Insulating protective layer

26‧‧‧Metal under the bump

27‧‧‧Electrical bumps

3‧‧‧ wafer

4‧‧‧ Carrier

R‧‧‧diameter

T‧‧‧ Deviation

1A to 1D are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package structure; and FIGS. 2A to 2D are schematic cross-sectional views showing a method of fabricating a semiconductor package structure of the present invention; wherein, the 2B' diagram is a partial perspective view of Figure 2B; 2E is a schematic cross-sectional view showing another embodiment of the method for fabricating a semiconductor package structure of the present invention; and FIGS. 3A to 3B are top views of the front operation of FIG. 2A.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2D are schematic cross-sectional views showing the method of manufacturing the semiconductor package structure 2 of the present invention.

As shown in FIG. 2A, a substrate 20 is provided. The substrate 20 has a body 20a, a plurality of electrode pads 200 disposed on the body 20a, and a passivation layer 201. The passivation layer 201 is formed with a plurality of openings 201a. Each of the electrode pads 200 is exposed.

Next, a metal layer 22 is formed on the electrode pad 200 and the passivation layer 201, and the metal layer 22 defines a plurality of line portions 22a and a hollow portion 22b.

In this embodiment, the substrate 20 is a wafer, an interposer or a wafer on which an internal circuit (not shown) has been fabricated, and the wafers have an integrated circuit, that is, the inside of the body 20a is electrically connected to the electrode. The circuit layer of the pad 200 (not shown), and the passivation layer 201 is tantalum nitride (SiNx). Specifically, as shown in FIGS. 3A to 3B, the wafer 3 having the completed internal wiring (not shown) is wafer dicing to obtain a plurality of wafers 20', and each of the wafers 20' is used as The substrate 20 is placed on a carrier member 4, and each of the substrates 20 is rearranged according to a subsequent required package size, that is, the substrate 20 has a desired spacing between the substrates.

Further, the structure of Fig. 2A is a partial cross-sectional view of one of the wafers 20' of Fig. 3A.

As shown in FIG. 2B, the first resist layer 23a is formed on the line portion 22a of the metal layer 22, and the second resist layer 23b is formed on a portion of the open portion 22b of the metal layer 22.

In this embodiment, the first resistive layer 23a and the second resistive layer 23b are photoresists, and the second resistive layer 23b is a plurality of blocks, as shown in the figure, six blocks, specifically, the Some of the block systems are cylindrical or elliptical columns, and their maximum diameter r is no more than 3 μm, as shown in Figure 2B'.

Further, the second resist layer 23b is located in a central portion of the open portion 22b as shown in Fig. 2B', and the second resist layer 23b occupies 20 to 45% of the surface area of the open portion 22b.

As shown in FIG. 2C, the metal layer 22 is removed by etching to cover the first layer. The open portion 22b of the second resist layer 23b and other regions not covered with the first resist layer 23a have the line portion 22a of the metal layer 22 as the wiring layer 24, and the circuit layer 24 has the under bump metal portion (Under Bump) Metallurgy, UBM) electrically connects the electrode pad 200.

In the present embodiment, the wet etching is performed, and the wet etching generates an isotropic etching, that is, etching is performed in other directions in addition to the etching in the vertical direction, for example, the horizontal direction.

Further, the wiring layer 24 is formed by using a characteristic of a critical dimension (Ciatical Dimension, CD) of the etching line (Bias) t ≦ 4 to 7 μm, wherein the t shown in FIG. 2C is Bias/2.

Moreover, the wet etching process uses 6 wt% of hydrofluoric acid (HF) as an etchant, wherein for 6 wt% of hydrofluoric acid, different metal layers 22 will have different deviations (Bias), and the same The geometry of the metal layer 22 and the different UBM configurations also affects the bias (Bias), as shown in the following table.

In addition, the etching liquid absorbed by the second resist layer 23b easily etches the metal layer 22 under the second resist layer 23b (ie, the partial open portion 22b), so that part of the second resist layer 23b remains in the passivation. On layer 201 (or the substrate 20).

The member method of the present invention is formed in the central portion of the open portion 22b of the metal layer 22 by the second resist layer 23b, so when wet etching, the etching is performed. The flow field of the liquid is distributed at the edge of the exposed area of the open portion 22b, that is, to the first resist layer 23a and the second resist layer 23b, so that the central portion of the open portion 22b can be etched to substantially reduce the open space. The residual amount in the central portion of the portion 22b can increase the yield and yield of the product.

Furthermore, the second resist layer 23b is formed on the open portion 22b to reduce the exposed area of the open portion 22b. Therefore, after the etching of the circuit layer 24 is completed and the etching is stopped, the exposed portion of the open portion 22b is exposed. Substantially removed, only a few empty portions 22b' (ie, the metal layer 22 under the second resist layer 23b) remain, thereby greatly reducing the possibility of affecting electrical properties, that is, the surface of the residual open portion 22b' is actively small. The circuit layer 24 is not connected, thereby effectively improving the yield and yield of the product.

As shown in Fig. 2D, the first and second resist layers 23a, 23b are removed, and the remaining open portion 22b', that is, the metal layer 22 under the second resist layer 23b, is removed.

In the present embodiment, the remaining open portion 22b' is removed using an etching solution such as 6 wt% hydrofluoric acid (HF).

Furthermore, the process for forming the circuit layer 24 is a redistribution layer (RDL) process.

Since the component manufacturing method of the present invention has a small amount of open space 22b' remaining, when the remaining hollow portion 22b' is subsequently removed, only a small amount of etching liquid is needed to quickly and surely remove the remaining hollow portion 22b', thereby not only reducing the etching liquid. The amount used, without damaging the surrounding structure (such as circuit layer 24).

Further, in another embodiment of the method of fabricating a semiconductor package structure 2', as shown in Fig. 2E, the wiring layer 24' includes a dielectric layer 240. With a line redistribution layer (RDL) 241. However, the number of layers associated with the circuit layer 24' can be formed as desired, and is not limited to one layer.

Furthermore, in a subsequent process, an insulating protective layer 25 such as a solder resist layer may be formed on the wiring layer 24', and the circuit redistribution layer 241 may be exposed to form an under bump metallurgy (UBM). 26, 俾 for bonding conductive bumps 27 such as solder material.

Further, the structure of the metal 26 under the bump is various and is not particularly limited and will not be described.

Alternatively, the circuit layers 24, 24' may have wire mats for the wire bonding process.

The invention can be applied to the manufacturing method of the circuit layer of the wafer level package to improve the yield yield.

In summary, in the method for fabricating a semiconductor package structure of the present invention, a plurality of discontinuous, such as a cylindrical block, is disposed as a second resist layer in the open portion of the metal layer, and then wet etching is used. The characteristics of the etching are used to generate an etching liquid disturbing field, so that when the wiring layer is formed by etching, it is easier to remove most of the metal material of the open portion.

Furthermore, since most of the material of the open space can be removed, the yield and yield of the product can be improved.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

20‧‧‧Substrate

20a‧‧‧ Ontology

200‧‧‧electrode pads

201‧‧‧ Passivation layer

23a‧‧‧First barrier layer

23b‧‧‧second barrier layer

24‧‧‧Line layer

T‧‧‧ Deviation

Claims (13)

A method for fabricating a semiconductor package structure includes: providing a substrate having a plurality of electrode pads and a passivation layer, wherein the passivation layer exposes the electrode pads; forming a metal layer on the electrode pads and the passivation layer, and the metal layer Defining a wire portion and an open portion; forming a first resist layer on the line portion of the metal layer, and forming a second resist layer on a portion of the open portion of the metal layer; etching removing the metal layer without covering the second resistor The hollow portion of the layer is such that the line portion of the metal layer serves as a circuit layer, and the circuit layer is electrically connected to the electrode pads; and the first and second resist layers are removed. The method of fabricating a component of a semiconductor package structure according to claim 1, wherein the substrate is a wafer, an interposer or a wafer on which internal wiring has been fabricated. The method of fabricating a semiconductor package structure according to claim 1, wherein the process of the substrate comprises: cutting a wafer to obtain a plurality of wafers; and rearranging each of the wafers on a carrier, and At least one wafer is used as the substrate. The method of fabricating a semiconductor package structure according to claim 1, wherein the passivation layer is formed with a plurality of openings to correspondingly expose the electrode pads. The component of the semiconductor package structure as described in claim 1 The method, wherein the second resist layer is a plurality of blocks. The method of fabricating a component of a semiconductor package structure according to claim 5, wherein the block systems are pillars. The method of fabricating a component of a semiconductor package structure according to claim 6, wherein the pillar system is a cylinder or an elliptical cylinder. The method of manufacturing a semiconductor package structure according to claim 7, wherein the pillars have a maximum diameter of not more than 3 μm. The method of fabricating a component of a semiconductor package structure according to claim 1, wherein the second resist layer is located in a central region of the open portion. The method of fabricating a semiconductor package structure according to claim 1, wherein the second resist layer occupies 20 to 45% of the surface area of the open portion. The method of fabricating a component of a semiconductor package structure according to claim 1, wherein the circuit layer is a line redistribution layer. The method for fabricating a semiconductor package structure according to claim 1, wherein the removing the remaining first hollow portion is removed after removing the first and second resist layers. The method of fabricating a semiconductor package structure according to claim 12, wherein the remaining open portion is removed by wet etching.