TWI484596B - Dynamic random access memory and method for fabricating the same - Google Patents

Description

Dynamic random access memory and manufacturing method thereof

The present invention relates to a dynamic random access memory and a method of fabricating the same, and more particularly to a buried bit line of a dynamic random access memory cell and a method of fabricating the same.

At present, a stacked random random access memory (DRAM) with a capacitor stacked on a transistor can achieve a high memory density target. However, the buried bit line (BL) of the stacked DRAM will cause the bit line-bit capacitance (BL-BL capacitance) problem between different buried bit lines due to the shrinking process size. Increasingly serious. In addition, in a stacked DRAM, different DRAM cells share a long buried buried bit line and a buried bit line contact (CB). This shared buried bit line contact is due to itself. The larger area creates a problem of buried bit line contact leakage (CB leakage).

Therefore, there is a need for a dynamic random access memory having a novel structure and a method of fabricating the same to solve the above problems.

In view of the above, an embodiment of the present invention provides a dynamic random access memory, including a buried bit line disposed in a first trench extending in a first direction in a substrate, the buried bit The line includes a plurality of bit line contacts disposed on a sidewall of the first trench along the first direction; a first insulator disposed in the substrate and extending in a second direction in a second trench On a bottom surface of the trough, wherein the above a pair of sidewalls of the first insulator respectively adjacent to the different bit line contacts; a pair of buried word lines are respectively disposed on a pair of sidewalls of the second trench, and respectively covering a portion of the first insulator .

Another embodiment of the present invention provides a method for fabricating a dynamic random access memory, including providing a substrate, forming a first trench along a first direction in the substrate, and forming a first trench in the first trench a buried bit line including a one-dimensional contact strip disposed on a sidewall of the first trench along the first direction; and a second trench formed in a second direction in the substrate, wherein Forming, during the forming of the second trench, the bit line contact strips are cut to form a plurality of the bit line contacts, respectively exposed from a pair of sidewalls of the second trench; and the second trench Forming a first insulator on a bottom surface, wherein a pair of sidewalls of the insulator respectively adjoin different bit line contacts; forming a pair of buried word lines on a pair of sidewalls of the second trench; A portion of the first insulator is covered separately.

1 is a perspective view showing a dynamic random access memory cell (hereinafter referred to as DRAM) 500 according to an embodiment of the present invention, for convenience of displaying a buried bit line (BL) and a buried word line (buried). The configuration of the word line, BW) does not show the insulation for isolating the different buried word lines, and the structure between the buried bit line and the buried word line, but the present embodiment is not limited. The cell size of the DRAM 500 as shown in Fig. 1 is 4F ² (where F is the minimum half pitch, or cell size). As shown in FIG. 1, the DRAM 500 is disposed in a substrate 200, and includes at least one buried bit line (BL) 250, at least one first insulator 228, and at least one pair of buried word lines. (buried word line, BW) 244. As shown in FIG. 1, the buried bit line 250 is disposed in a first trench 412 extending in a first direction 410 in the substrate 200. The buried bit line 250 includes a plurality of bit line contacts 208a. The first side 410 is spaced apart from the first side 414a of the first trench 412. The first insulator 228 is disposed on a bottom surface of the second trench 422 extending in a second direction 420 different from the first direction 410 in the substrate 200, wherein the pair of sidewalls 229 of the first insulator 228 are respectively adjacent to each other. Different bit line contacts 208a. As shown in FIG. 1, a pair of buried word lines 244 of DRAM 500 are respectively disposed on a pair of sidewalls 230 of the second trench 422, and cover a portion of the first insulator 228, respectively.

In the embodiment shown in FIG. 1, the bit line contact 208a of the buried bit line 250 of the DRAM 500, the buried word line 244, the substrate portion 314 adjacent to the bit line contact 208a, and the two phases are located. The substrate portion 316 between the adjacent buried word lines 244 and the other substrate portion 318 on the substrate portion 316 may constitute a vertical transistor, wherein the bit line contact 208a acts as a drain contact of the vertical transistor. The buried word line 244 is used as the gate of the vertical transistor, and the vertically stacked substrate portion 314, the substrate portion 316, and the substrate portion 318 serve as the drain region, the channel region, and the source region of the vertical transistor. In addition, the DRAM 500 further includes a capacitor 312 electrically contacting the source region of the vertical transistor (substrate portion 318).

2a, 2b to 8a, 8b are schematic cross-sectional views showing a method of manufacturing a dynamic random access memory according to an embodiment of the present invention, wherein 2a-8a are cross-sectional views taken along line A-A' of Fig. 1, and Figs. 2b-8b are cross-sectional views taken along line B-B' of Fig. 1. As shown in Figures 2a and 2b, first, a substrate 200 is provided. In an embodiment of the invention, the substrate 200 can be a germanium substrate. In other embodiments, silicon germanium (SiGe), bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI), Or other commonly used semiconductor substrates are used as the substrate 200. The substrate 200 can be implanted with a p-type or n-type dopant to change its conductivity type for design needs. Thereafter, a zeroth insulating pad 100 may be overlaid on the substrate 200 by chemical vapor deposition (CVD) as an etched hard mask for the subsequent first trench formed in the substrate 200. In an embodiment of the invention, the zeroth insulating pad 100 may be tantalum nitride.

Next, referring to FIGS. 2a and 2b, the zeroth insulating pad 100 can be patterned by a lithography and etching process, and the formation position of the first trench 412 can be defined. Then, an etching process may be performed to form the first trench 412 in the substrate 200 along the first direction 410 as shown in FIG. 1 by using the patterned zeroth insulating pad 100 as an etch hard mask. Then, a buried bit line 250 is formed in the first trench 412, and includes a bit line contact strip 208 disposed in a first direction 410 on a sidewall 414a of the lower portion of the first trench 412. An insulating pad 202 compliantly covers the sidewalls 414a, 415a and a bottom surface 416 of the lower portion of the first trench 412, and adjacent to the bit line contact strip 208, and a first conductive material 207 filling the lower portion of the first trench 412 And covering the first insulating pad 202 and the bit line contact strip 208. In an embodiment of the invention, the first conductive material 207 includes a first barrier layer 204 and a first metal strip 206, wherein the first barrier layer 204 is formed in the first trench 412. The first insulating strip 202 and the bit line contact strip 208 are covered, and the first metal strip 206 is filled to fill the lower portion of the first trench 412 and covers the first barrier layer 204. In an embodiment of the invention, the first insulating pad 202 may comprise an oxide, a nitride or a combination thereof, and the first barrier layer may comprise a laminated structure, the material of which comprises titanium, titanium nitride or a combination thereof And the bit line contact strip 208 can include a telluride (eg, TiSi _x ). In an embodiment of the invention, the diffusion region 210 adjacent the sidewall of the bit line contact strip 208 can be formed in the substrate 200 by diffusing the dopant of the bit line contact strip 208 to the substrate 200. In an embodiment of the invention, the diffusion region 210 is located in the substrate portion 314 (drain region) as shown in FIG. 1 and can be used as a diffusion junction between the buried bit line and the drain of the vertical transistor. And the first conductive material 207 is electrically connected to the drain of the vertical transistor by the bit line contact strip 208 and the diffusion region 210.

Referring to FIGS. 2a and 2b, after the buried bit line 250 is formed, a second insulating pad 212 may be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) to cover the first The sidewalls 414b, 415b of the upper portion of the trench 412 embed the bit line 250 and the top surface 201 of the zeroth insulating pad 100. Next, a second insulating 214 may be formed in the first trench 412 by a deposition method such as high density plasma chemical vapor deposition (HDP-CVD) and a subsequent etching back step. Part of the second insulating pad 212. In an embodiment of the invention, the second insulator 214 and the second insulating pad 212 are made of different materials. For example, when the second insulator 214 is an oxide, the second insulating pad 212 is a nitride. Then, a dielectric 216 can be formed on the second insulator 214 by using, for example, a spin-on deposition method and a subsequent etch back step, the top surface of which is lower than the top surface 201 of the substrate 200. . In an embodiment of the invention, the height position of the dielectric 216 in the first trench 412 is the same as a pair of buried word lines formed subsequent to the other trench to facilitate subsequent formation of the dielectric 216. The conductive material can be connected to the buried word line. Then, a third insulating layer 218 can be formed by high-density plasma chemical vapor deposition (HDP-CVD), filling the first trench 412 and covering the substrate 200, wherein a top of the third insulating layer 218 The face is essentially a flat surface. In an embodiment of the present invention, the material of the second insulating pad 212, the second insulating layer 214, and the third insulating layer 218 may include an oxide, a nitride, or a combination thereof, wherein the second insulating layer 214 and the third insulating layer The layer 218 can be the same material, and the materials of the second insulator 214 and the third insulating layer 218 are different from the material of the second insulating pad 212. For example, the second insulator 214 and the third insulating layer 218 are both oxides, and the second insulating pad 212 is nitride.

Next, the manner in which the second trench 422 is formed will be described. As shown in FIG. 1, the first trench 412 and the second trench 422 are designed to be disposed to cross each other. Referring to FIGS. 2a and 2b, a carbon hard mask layer 220 and a nitride hard mask layer 222 may be sequentially formed on the third insulating layer 218 by chemical vapor deposition (CVD). Thereafter, a photoresist can be formed by a coating method, and a lithography process is performed using a buried word line mask to form a plurality of photoresist patterns 224 along the second direction 420. In an embodiment of the invention, the carbon hard mask layer 220 and the nitride hard mask layer 222 are used as an etching process for forming the second trench 422 having a high aspect ratio. A mask is used to avoid damage to the surface of the substrate 200 during the etching process.

Next, referring to FIGS. 3a and 3b, an anisotropic etching step such as dry etching is performed to remove the nitride hard mask layer 222 not covered by the photoresist pattern 224 to form a nitride hard mask pattern (Fig. Not shown), the photoresist pattern 224 is removed during the process. Thereafter, a nitride hard mask pattern (not shown) is used as a mask, and an anisotropic etching step such as dry etching is performed to remove the carbon hardened by the nitride hard mask pattern (not shown). The mask layer 220 is formed to form a carbon hard mask pattern 220a, at which time the nitride hard mask pattern is removed during the process. Then, using the carbon hard mask pattern 220a as a mask, an anisotropic etching step such as dry etching is performed to remove the third insulating layer 218 and the substrate 200 not covered by the carbon hard mask pattern 220a (eg, 3b) Figure shows). Since the first trench 412 and the second trench 422 are designed to be disposed to cross each other, during the etching process for forming the second trench 422, the first trench 412 is also removed and is not hardened by carbon. The third insulating layer 218 and the dielectric 216 covered by the pattern 220a are stopped until the second insulator 214 is stopped, and the substrate 200 outside the first trench 412 is simultaneously etched to the bit line contact strip 208 to Forming a second trench 422 in the second direction 420 in the substrate 200, wherein the period of forming the second trench 422 is to cut the bit line contact strip 208 to form a plurality of bit lines as shown in FIG. Contact 208a. As shown in the first, third, and third embodiments, the first trench 412 and the second trench 422 are disposed to intersect each other, and the bottom surface 423 of the second trench 422 is designed to be located above the bottom surface 416 of the first trench 412, but No more than the bottom line contacts the bottom surface of the strip 208 to ensure that the bit line contact strip 208 will form the second trench 422 The process was cut off during the process.

Next, referring to Figures 4a and 4b, the carbon hard mask pattern 220a can be removed by dry etching.

Next, referring to Figures 5a and 5b, a cleaning process can be performed by diluting hydrofluoric acid (DHF) to remove, for example, a native oxide on the sidewall 230 of the second trench 422, and simultaneously shifting Dielectric 216 in first trench 412 is removed to form a void 226 surrounded by second insulating pad 212, second insulator 214, and third insulating layer 218. Diluting hydrofluoric acid in this cleaning process has a high etch rate for dielectric 216. Thereafter, a first insulator 228 may be formed on a bottom surface 423 of the second trench 422 by a deposition method such as chemical vapor deposition (CVD) and a subsequent etching back step. Referring again to FIG. 1, a pair of sidewalls 229 of the first insulator 228 abut the different bit line contacts 208, respectively, and as shown in FIGS. 1 and 5a, the bottom surface 246 of the first insulator 228 is not higher than the bit. The bottom surface 211 of the contact 208a, and the top surface 247 of the first insulator 228 is not lower than the top surface 209 of the bit line contact 208a to ensure that the bit line contact 208a adjacent in the first direction 410 can The first insulator 228 is isolated from each other.

Next, referring to FIGS. 5a and 5b, a pair of thermal oxide layers 232 are respectively formed on the pair of sidewalls 230 of the second trench 422 by, for example, thermal oxidation.

Next, referring to FIGS. 6a and 6b, a second barrier layer 234 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD), from the third insulating layer 218. The top surface extends over the sidewalls 230 of the second trench 422, the first insulator 228, and the holes shown in FIG. 5a. Side wall of 226. Then, a metal material 236 may be formed by chemical vapor deposition (CVD) to cover the second barrier layer 234 and fill the second trench 422 and the holes 226. Thereafter, a planarization process such as chemical mechanical polishing (CMP) may be performed to planarize the surface of the metal material 236.

Next, referring to FIGS. 7a and 7b, an etching back step may be used to remove a portion of the metal material 236 and the second resistor located on the top surface of the third insulating layer 218 and partially located in the second trench 422. The barrier layer 234 is to a specific depth (eg, the top surface of the metal material 236 and the second barrier pad layer 234 in the second trench 422 is lower than the surface of the substrate 200). Then, a first insulating hard mask layer 110 is formed by chemical vapor deposition (CVD) compliance. In an embodiment of the invention, the first insulating hard mask layer 110 may be made of tantalum oxide.

Next, referring to FIGS. 8a and 8b, using the first insulating hard mask layer 110 as an etch hard mask, an anisotropic etching process such as dry etching is performed to cut off the metal located in the second trench 422. A material 236 and a second barrier layer 234 are formed on the pair of sidewalls 230 of the second trench 422 to form a pair of buried word lines 244, each of the buried word lines 244 being formed by a second barrier layer 234a and The two metal strips 236a are formed. After the dry etch process, the first insulator 228 is exposed from the gap between the buried word lines 244. As shown in FIG. 8a, a buried conductor line 244 is formed while a second conductive material 244a is formed in the first trench 412, and embedded in the first direction 410 as shown in FIG. 1 in FIG. 5a. In the cavity 226 shown. As shown in FIGS. 1 and 8a, the two ends of the second conductive material 244a are respectively connected to a pair of buried word lines located on both sides of the channel region (substrate portion) 318. 244, and the second conductive material 244a and the buried bit line 250 below it are isolated from each other by the second insulator 214 and the second insulating pad 212. In an embodiment of the invention, the second conductive material 244a is extended from a pair of sidewalls 230 of the second trench 422 to a portion of the second barrier layer 234b embedded in the cavity 226 as shown in FIG. 5a and A portion of the two metal strips 236b are formed, wherein the second barrier layer 234b of the second conductive material 244a surrounds the second metal strip 236b. Note that the second barrier pads 234a, 234b are different portions of the same second barrier layer, while the second metal strips 236a, 236b are different portions of the same second metal strip. Thereafter, an insulating material 240 is formed integrally, covering the top surface of the third insulating layer 218 and filling the second trench 422. Then, a subsequent process is performed to form the dynamic random access memory 500 according to an embodiment of the present invention as shown in FIG. 1.

In one embodiment of the present invention, a dynamic random access memory 500 is provided. The bit line contacts 208a of two adjacent DRAM cells are separated by the first insulator 228 and separated from each other, so that the bit of the buried bit line can be buried. The area of the line contact is reduced, so that the bit line-bit line parasitic capacitance (BL-BL) generated by the common DRAM cell sharing the long burial bit line of the conventional dynamic random access memory can be greatly reduced. Capacitance) and buried bit line contact leakage (CB leakage) and other issues. In addition, in the method for manufacturing a dynamic random access memory according to the embodiment of the present invention, only the buried word line mask process required for the process can be used to complete the truncation of buried bit lines between different DRAM cells, thereby eliminating the need for additional Photomask process.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100‧‧‧ zeroth insulation mat

110‧‧‧First insulating hard mask layer

200‧‧‧Substrate

201, 211, 247‧‧‧ top

202‧‧‧First insulation mat

204‧‧‧First barrier layer

206‧‧‧First metal strip

207‧‧‧First Conductor

208‧‧‧ bit line contact strip

208a‧‧‧ bit line contact

209, 246, 416, 423‧‧‧ bottom

210‧‧‧Diffusion zone

212‧‧‧Second insulation mat

214‧‧‧second insulation

216‧‧‧ dielectric

218‧‧‧ Third insulation layer

220‧‧‧Carbon hard mask

220a‧‧‧carbon hard mask pattern

222‧‧‧ nitride hard mask layer

224‧‧‧resist pattern

226‧‧‧ hole

228‧‧‧First insulation

229, 223, 230, 414a, 415a, 414b, 415b‧‧‧ side walls

232‧‧‧ Thermal Oxide

234, 234a, 234b‧‧‧ second barrier layer

236‧‧‧Metal materials

236a, 236b‧‧‧ second metal strip

240‧‧‧Insulation

244‧‧‧ buried word line

244a‧‧‧Second conductor

250‧‧‧buried bit line

312‧‧‧ Capacitance

314, 316, 318‧‧‧ substrate part

410‧‧‧First direction

412‧‧‧First trench

420‧‧‧second direction

422‧‧‧Second trench

500‧‧‧ Dynamic Random Access Memory

Fig. 1 is a perspective view showing a dynamic random access memory according to an embodiment of the present invention.

2a-8a are cross-sectional views taken along line A-A' of Fig. 1 and showing a cross-sectional view showing a method of manufacturing a dynamic random access memory according to an embodiment of the present invention.

2b-8b is a cross-sectional view taken along line B-B' of Fig. 1 and showing a cross-sectional view showing a method of manufacturing the dynamic random access memory according to an embodiment of the present invention.

200‧‧‧Substrate

208a‧‧‧ bit line contact

228‧‧‧First insulation

229, 230, 414a‧‧‧ side walls

234a, 234b‧‧‧ second barrier layer

236a, 236b‧‧‧ second metal strip

244‧‧‧ buried word line

244a‧‧‧Second conductor

250‧‧‧buried bit line

312‧‧‧ Capacitance

314, 316, 318‧‧‧ substrate part

410‧‧‧First direction

412‧‧‧First trench

420‧‧‧second direction

422‧‧‧Second trench

500‧‧‧ Dynamic Random Access Memory

Claims (17)

A dynamic random access memory, comprising: a buried bit line disposed in a first trench extending in a first direction in a substrate, the buried bit line comprising a plurality of bit line contacts, along The first direction is disposed on a sidewall of the first trench; a first insulator is disposed on a bottom surface of the second trench extending in a second direction in the substrate, wherein the first insulation The pair of sidewalls of the object respectively adjoin the different bit line contacts; and a pair of buried word lines are respectively disposed on the pair of sidewalls of the second trench and respectively cover a portion of the first insulator. The DRAM of claim 1, wherein the buried bit line comprises: a first insulating pad layer covering the sidewall and a bottom surface of the lower portion of the first trench, and adjoining the a bit line contact; and a first conductive material filling the lower portion of the first trench and covering the first insulating pad layer and the bit line contacts. The dynamic random access memory according to claim 2, further comprising: a second insulating pad covering the sidewall of the first trench and the buried bit line; a second insulator, Filling the upper portion of the first trench and covering the second insulating pad layer; and a second conductive material embedded in the second insulator along the first direction, wherein the two ends of the second conductive material are respectively connected The pair of buried word lines. Dynamic random access memory as described in claim 2 The first conductive material further includes: a first barrier pad layer formed in the first trench and covering the first insulating pad layer and the bit line contacts; and a first metal a strip filling the first trench and covering the first barrier layer. The dynamic random access memory according to claim 3, wherein the pair of buried word lines are composed of a thermal oxide layer, a second barrier layer and a second metal strip, wherein the heat An oxide layer covers the pair of sidewalls of the second trench, and the second barrier layer is interposed between the thermal oxide layer and the second metal strip. The dynamic random access memory according to claim 5, wherein the second conductive material is extended from the pair of sidewalls of the second trench and embedded in the second insulator. The barrier layer and a portion of the second metal strip are formed, wherein the second barrier layer of the second conductive material surrounds the second metal strip. The dynamic random access memory according to claim 1, further comprising a plurality of diffusion regions located in the substrate and adjacent to sidewalls of the bit line contacts. The dynamic random access memory according to claim 1, wherein the first trench and the second trench are disposed to cross each other, and the bottom surface of the second trench is located in the first trench Above the bottom surface. The dynamic random access memory according to claim 1, wherein a bottom surface of the first insulator is not higher than a bottom surface of the bit line contacts, wherein a top surface of the first insulator is not Below the top surface of the bit line contacts. A method for fabricating a dynamic random access memory, comprising the steps of: providing a substrate; forming a first trench in a first direction in the substrate; forming a buried bit line in the first trench, Included in the first direction, a first trench is disposed on a sidewall of the first trench; a second trench is formed in the substrate along a second direction, wherein the second trench is formed Intersecting the bit line contact strips to form a plurality of the bit line contacts, respectively exposing from a pair of sidewalls of the second trench; forming a surface on a bottom surface of the second trench a first insulator, wherein a pair of sidewalls of the insulator respectively adjoin the different bit line contacts; and a pair of buried word lines are formed on a pair of sidewalls of the second trench, respectively covering a portion of the first An insulator. The method for manufacturing a dynamic random access memory according to claim 10, wherein the first trench and the second trench are disposed to cross each other, and the bottom surface of the second trench is located in the first trench Above a bottom surface of the slot. The method of manufacturing a dynamic random access memory according to claim 11, wherein the buried bit line includes: a first insulating pad covering the sidewall and a bottom surface of the lower portion of the first trench, and Adjacent to the bit line contacts; and a first conductive material filling the lower portion of the first trench and covering the first An insulating pad and the bit line contacts. The manufacturing method of the dynamic random access memory according to claim 12, after the forming the buried bit line further comprises: conforming to form a second insulating pad layer covering the sidewall of the upper portion of the first trench a buried bit line and a top surface of the substrate; forming a second insulator covering a portion of the second insulating pad; forming a dielectric on the second insulator; and forming a third comprehensively An insulating layer filling the first trench and covering the substrate, wherein a top surface of the third insulating layer is substantially a flat surface. The method for manufacturing a dynamic random access memory according to claim 13, wherein the forming the second trench further comprises sequentially forming a carbon hard mask layer and a nitride on the third insulating layer. a hard mask layer; forming a plurality of photoresist patterns along the second direction by using a buried word line mask; performing an anisotropic etching step to remove the nitride not covered by the photoresist patterns a hard mask layer, the carbon hard mask layer, the third insulating layer, the substrate, the second insulator, the dielectric until the bit line contact not covered by the photoresist patterns is completely removed And the photoresist pattern, the nitride hard mask layer and the carbon hard mask layer are removed. The method for manufacturing a dynamic random access memory according to claim 14, wherein the forming the first insulator further comprises: A cleaning process is performed to remove the dielectric to form a cavity surrounded by the second insulating pad layer, the second insulating layer, and the third insulating layer. The method for manufacturing a dynamic random access memory according to claim 15, wherein the forming the pair of buried word lines further comprises: forming a pair of thermal oxide layers on the pair of sidewalls of the second trench; Compliance forming a second barrier layer extending from a top surface of the third insulating layer covering the pair of sidewalls of the second trench, the sidewalls of the first insulator and the hole; forming a metal comprehensively a material covering the second barrier layer and filling the second trench and the hole; and removing the metal material on the top surface of the third insulating layer and partially located in the second trench and a second barrier layer; compliance forms a hard mask layer; an anisotropic etching process is performed to intercept the metal material and the second barrier layer in the second trench. The method for manufacturing a dynamic random access memory according to claim 10, wherein a bottom surface of the first insulator is not higher than a bottom surface of the bit line contacts, wherein the first insulator The top surface is not lower than the top surface of the bit line contacts.