201119000 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種埋藏位元線及其製造方法，特別 是有關於一種動態隨機存取記憶體晶胞的埋藏位元線及其 製造方法。 【先前技術】 動隨機存取5己憶體（Dynamic Random Access Memory，DRAM)屬於一種揮發性記憶體（v〇latile memory)’主要的作用原理是利用電容内儲存電荷的多寡來 代表-個二進位位元_是i還是〇，以儲存資料。為達到 高密度的要求’目前最有效的方法是透過縮小製造製程和 採用單元設計技術來減小晶片的尺寸。減小晶片尺寸的另 一種方法是實現更為有效的陣列举μ , 』木稱’在連續幾代發展 後’儲存技術通常會變成某種單元你 干兀邯局的限制，單元尺寸 的每一次改善都需要進行大量的工作也、Λ、， 平 減少蝕刻的最小尺 寸。 隨機存取記憶體 因此’亟需一種具有新穎結構的動態 及其製造方法。 ~ 【發明内容】 有鑑於此，本發明之一實 線，設置於一基板的一溝槽中， 接上述溝槽的部分上述基板中； 槽的部分側壁上；一導電插塞， ，提供—種埋藏位元 包括一擴散區，形成於鄰 /遮蔽層’形成於上述溝 形成於上述溝槽中，且覆 9095-A34446TWF 4 201119000 蓋上述擴散區和上述遮蔽層的側壁。 本發明之另一實施例係提供一種埋藏位元線的製造 方法，包括提供一基板；於上述基板中形成一溝槽；於上 述溝槽的部分側壁上形成一遮蔽層；於上述溝槽中形成一 第一硬遮罩層，覆蓋部分上述遮蔽層；移除未被上述第一 硬遮罩層覆蓋的上述遮蔽層，以暴露出上述溝槽的部分側 壁；移除上述第一硬遮罩層；於鄰接上述溝槽暴露的側壁 的上述基板中形成一擴散區；於上述溝槽中形成一導電插 塞，且覆蓋上述擴散區的側壁。 【實施方式】 以下以各實施例詳細說明並伴隨著圖式說明之範 例，做為本發明之參考依據。在圖式或說明書描述中，相 似或相同之部分皆使用相同之圖號。且在圖式中，實施例 之形狀或是厚度可擴大，並以簡化或是方便標示。再者， 圖式中各元件之部分將以分別描述說明之，值得注意的 是，圖中未繪示或描述之元件，為所屬技術領域中具有通 常知識者所知的形式，另外，特定之實施例僅為揭示本發 明使用之特定方式，其並非用以限定本發明。 第la圖係顯示本發明一實施例之動態隨機存取記憶 體晶胞（以下簡稱DRAM)600a的透視圖。在本發明一實施 例中，DRAM 600a的晶胞尺寸為4F2(其中F為最小微影製 程尺寸，或稱單元尺寸）。如第la圖所示，上述DRAM 600 的一垂直電晶體300、一埋藏位元線（buried bit line, BL)500a 和一字元線(word line，WL)308 皆設於一基板 200201119000 6. Technical Description: The present invention relates to a buried bit line and a method of fabricating the same, and more particularly to a buried bit line of a dynamic random access memory cell and a method of fabricating the same . [Prior Art] Dynamic Random Access Memory (DRAM) belongs to a type of volatile memory (v〇latile memory). The main principle of operation is to use the amount of charge stored in the capacitor to represent - two The carry bit _ is i or 〇 to store the data. To achieve high density requirements, the most effective method at present is to reduce the size of the wafer by reducing the manufacturing process and using cell design techniques. Another way to reduce the size of the wafer is to achieve a more efficient array of μ, "woody 'after several generations of development' storage technology will usually become a unit of your constraints, every improvement in unit size A lot of work is required, too, and the minimum size of the etching is reduced. Random Access Memory Therefore, there is a need for a dynamic structure with a novel structure and a method of manufacturing the same. In view of the above, a solid line of the present invention is disposed in a trench of a substrate, in a portion of the substrate connected to the trench; a portion of the sidewall of the trench; a conductive plug, providing - The buried bit includes a diffusion region formed in the trench formed in the trench and covered by the 9095-A34446TWF 4 201119000 to cover the diffusion region and the sidewall of the shielding layer. Another embodiment of the present invention provides a method for fabricating a buried bit line, comprising: providing a substrate; forming a trench in the substrate; forming a shielding layer on a portion of the sidewall of the trench; Forming a first hard mask layer covering a portion of the shielding layer; removing the shielding layer not covered by the first hard mask layer to expose a portion of the sidewall of the trench; removing the first hard mask a layer; a diffusion region is formed in the substrate adjacent to the exposed sidewall of the trench; a conductive plug is formed in the trench and covers a sidewall of the diffusion region. BEST MODE FOR CARRYING OUT THE INVENTION The following is a detailed description of the embodiments and the accompanying drawings are intended to be a reference for the present invention. In the drawings or the description of the specification, the same drawing numbers are used for the similar or identical parts. Also, in the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention. Figure la is a perspective view showing a dynamic random access memory cell (hereinafter referred to as DRAM) 600a according to an embodiment of the present invention. In one embodiment of the invention, DRAM 600a has a cell size of 4F2 (where F is the minimum lithography process size, or cell size). As shown in FIG. 1a, a vertical transistor 300, a buried bit line (BL) 500a, and a word line (WL) 308 of the DRAM 600 are disposed on a substrate 200.
9095-A34446TWF 201119000 中。如第la圖所示，DRAM 600包括一基板200。一垂直 電晶體300，形成於基板200中。垂直電晶體300係具有 垂直堆疊的一下層汲極區314、一中間層通道區316和一 上層之源極區318。另外，垂直電晶體300係具有至少一 垂直側壁302。一字元線308，沿一第一方向322形成於基 板200中，其中字元線308係設於垂直電晶體300的垂直 侧壁302上，並做為垂直電晶體300的閘極。字元線308 與垂直電晶體300之間係設有一絕緣層306，以做為垂直 電晶體300的閘極絕緣層。如第ia圖所示，DRAM 600更 包括一埋藏位元線500a，沿不同於第一方向322的一第二 方向320形成於基板200中的一溝槽210中，且位於垂直 電晶體300的下方，並電性接觸該對垂直電晶體300的汲 極區314。另外，DRAM 600更包括一電容312，電性接觸 垂直電晶體300的源極區318。第lb圖為沿第la圖的A-A， 切線的剖面圖，其顯示本發明一實施例之DRAM的一例如 位元線500a之埋藏位元線500a的剖面圖。如第lb圖所示， 其中埋藏位元線500a包括一遮蔽層208和鄰接之一擴散源 層228 ’形成於溝槽210的部分侧壁上；以及一導電插塞 240 ’形成於溝槽210中，且覆蓋擴散源層228和遮蔽層 208的側壁。 第2〜10圖係顯示本發明一實施例之DRAM 600a的埋 藏位元線500a的製造方法的剖面示意圖。如第2圖所示， 首先’提供一基板200。在本發明一實施例中，基板200 可為矽基板。在其他實施例中，可利用鍺化矽（SiGe)、塊 狀半導體（bulk semiconductor)、應變半導體（strained 9095-A34446TWF 6 201119000 semiconductor)、化合物半導體（c〇mp0und semiconductor)、 絶緣層上覆石夕(silicon on insulator, SOI)，或其他常用之半 導體基板做為基板200。基板200可植入p型或n型摻質， 以針對設計需要改變其導電類型。在本發明一實施例中， 基板200可植入ρ型摻質。接著，可利用微影及蝕刻製程’ 於基板200中形成一子溝槽202。之後，可利用化學氣相 沉積法(CVD)或物理氣相沉積法(PvD)，順應性於該子溝槽 202的側壁206和底面204上形成遮蔽層208。在本發明一 • 實施例中，子溝槽202係用以定義後續形成之遮蔽層以及 擴散源層底面的位置。在本發明一實施例中，遮蔽層 可包括一氧化層、一氮化物層或其組合。舉例來說，遮蔽 層208可為覆盍子溝槽202的侧壁206之一氧化層和覆蓋 上述氧化層之一氮化層所形成的疊層結構。 之後，请參考第3圖，可再利用钱刻製程，從子溝槽 202的底面204移除部分遮蔽層208以及其下的部分基板 200，以形成一溝槽21〇，並暴露出其底面212和部分側壁 _ 214。然後，可利用例如熱氧化法沖隨^ 〇xidati〇n)，順應 性於溝槽210的底面212和未被遮蔽層208覆蓋的側壁214 上形成底部絕緣墊層216。在本發明一實施例中，底部絕 緣墊層216可包括氧化層、氮化物層或其組合。在本實施 例中’底部絕緣墊層216可為氧化層。 接著，請參考第4圖，可利用塗佈（coating)方式，全 面性形成一光阻，並填入溝槽21〇中。之後，可利用回蝕 刻（etching back)方式，移除位於基板2〇〇上及部分位於溝 槽210中的一部分光阻，以分別於溝槽21〇中形成光阻9095-A34446TWF 201119000. As shown in FIG. 1a, the DRAM 600 includes a substrate 200. A vertical transistor 300 is formed in the substrate 200. The vertical transistor 300 has a lower stacked drain region 314, an intermediate layer channel region 316, and an upper source region 318. Additionally, vertical transistor 300 has at least one vertical sidewall 302. A word line 308 is formed in the substrate 200 along a first direction 322, wherein the word line 308 is disposed on the vertical sidewall 302 of the vertical transistor 300 and serves as the gate of the vertical transistor 300. An insulating layer 306 is disposed between the word line 308 and the vertical transistor 300 to serve as a gate insulating layer of the vertical transistor 300. As shown in FIG. ia, the DRAM 600 further includes a buried bit line 500a formed in a trench 210 in the substrate 200 along a second direction 320 different from the first direction 322, and located in the vertical transistor 300. Below, and electrically contacting the drain region 314 of the pair of vertical transistors 300. In addition, the DRAM 600 further includes a capacitor 312 electrically contacting the source region 318 of the vertical transistor 300. Figure lb is a cross-sectional view taken along line A-A of the first drawing, showing a buried bit line 500a of a DRAM such as a bit line 500a of an embodiment of the present invention. As shown in FIG. 1b, the buried bit line 500a includes a shielding layer 208 and a neighboring diffusion source layer 228' formed on a portion of the sidewall of the trench 210; and a conductive plug 240' is formed in the trench 210. And covering the sidewalls of the diffusion source layer 228 and the shielding layer 208. 2 to 10 are schematic cross-sectional views showing a method of manufacturing the buried bit line 500a of the DRAM 600a according to an embodiment of the present invention. As shown in Fig. 2, a substrate 200 is first provided. In an embodiment of the invention, the substrate 200 can be a germanium substrate. In other embodiments, a germanium telluride (SiGe), a bulk semiconductor, a strained semiconductor (strained 9095-A34446TWF 6 201119000 semiconductor), a compound semiconductor (c〇mp0und semiconductor), and an insulating layer may be used. (silicon on insulator, SOI), or other commonly used semiconductor substrates are used as the substrate 200. The substrate 200 can be implanted with a p-type or n-type dopant to change its conductivity type for design needs. In an embodiment of the invention, the substrate 200 can be implanted with a p-type dopant. Next, a sub-trench 202 can be formed in the substrate 200 by using a lithography and etching process. Thereafter, a masking layer 208 can be formed on the sidewalls 206 and the bottom surface 204 of the sub-trench 202 by chemical vapor deposition (CVD) or physical vapor deposition (PvD). In an embodiment of the invention, sub-trench 202 is used to define the location of the subsequently formed masking layer and the bottom surface of the diffused source layer. In an embodiment of the invention, the masking layer may comprise an oxide layer, a nitride layer or a combination thereof. For example, the masking layer 208 can be an oxide layer of the sidewall 206 of the germanium trench trench 202 and a laminate structure formed by a nitride layer covering one of the oxide layers. Thereafter, referring to FIG. 3, a portion of the shielding layer 208 and a portion of the substrate 200 thereunder may be removed from the bottom surface 204 of the sub-trench 202 to form a trench 21 and expose the bottom surface thereof. 212 and a portion of the side wall _ 214. Then, a bottom insulating pad layer 216 can be formed on the bottom surface 212 of the trench 210 and the sidewall 214 not covered by the masking layer 208 by, for example, thermal oxidation. In an embodiment of the invention, the bottom insulating pad layer 216 may comprise an oxide layer, a nitride layer, or a combination thereof. In the present embodiment, the bottom insulating pad layer 216 may be an oxide layer. Next, referring to Fig. 4, a photoresist can be formed in a full surface by a coating method, and filled in the trench 21〇. Thereafter, an etch back can be used to remove a portion of the photoresist on the substrate 2 and partially in the trench 210 to form a photoresist in the trench 21, respectively.
I S 9095-A34446TWF ^ 201119000 218 ’其分別覆蓋底部絕緣墊層216和料遮蔽層2〇8。如 第4圖所示’光阻218的頂面22()係低於溝槽21()的頂面， 且高於底部絕緣墊層216。在本發明一實施例中，光阻218 的頂面22G係用以定義後續形成之遮蔽詹以及擴散源層頂 面的位置。 然後二請參考第5圖，可利用蝕刻方式，移除未被光 阻218覆盖的遮敝層208，以暴露出第二溝槽的上部 側壁221 ’並定義出遮蔽層208之頂面209。 之後’請參考第6圖’移除光阻218。接著，再利用 例如熱氧化法(thermal oxidation)，於溝槽210的暴露的上 部侧壁221上形成之頂部絕緣墊層222。在本發明實施例 中，頂部絕緣墊層222可包括氧化層、氮化物層或其組合。 在本實施例中’頂部絕緣墊層222可為氧化層。如第6圖 所示’位於溝槽210中的底部絕緣墊層216與頂部絕緣墊 層222藉由遮蔽層208彼此隔開。 第7〜9圖係顯示利用自對準（self-aligned)方式於溝槽 210中形成蝕刻選擇比彼此不同的複數層硬遮罩層，以藉 由後續的蝕刻製程定義出本發明一實施例之擴散源層2 2 8 或擴散區230的位置。請參考第7圖，可利用沉積和回蝕 刻（etching back)製程，於溝槽210中形成一絕緣層224，並 覆蓋底部絕緣墊層216、遮蔽層208和部分頂部絕緣墊層 222。如第7圖所示，絕緣層224的頂面係低於基板200的 表面，且高於遮蔽層208的頂面。在本發明一實施例中， 絕緣層224可為氧化物，例如為多孔氧化物（porous oxide)。接著，可再利用沉積和回姓刻（etching back)製程’ 9095-A34446TWF 8 201119000I S 9095-A34446TWF ^ 201119000 218 ' covers the bottom insulating layer 216 and the material shielding layer 2〇8, respectively. As shown in Fig. 4, the top surface 22() of the photoresist 218 is lower than the top surface of the trench 21() and higher than the bottom insulating spacer 216. In one embodiment of the invention, top surface 22G of photoresist 218 is used to define the location of the subsequently formed mask and the top surface of the diffusion source layer. Then, referring to FIG. 5, the concealing layer 208 not covered by the photoresist 218 may be removed by etching to expose the upper sidewall 221' of the second trench and define the top surface 209 of the shielding layer 208. After that, please refer to Figure 6 to remove the photoresist 218. Next, a top insulating pad layer 222 is formed over the exposed upper sidewall 221 of the trench 210 using, for example, thermal oxidation. In an embodiment of the invention, the top insulating pad layer 222 may comprise an oxide layer, a nitride layer, or a combination thereof. In the present embodiment, the top insulating pad layer 222 may be an oxide layer. As shown in Fig. 6, the bottom insulating pad layer 216 and the top insulating pad layer 222 in the trench 210 are separated from each other by the shielding layer 208. 7 to 9 show that a plurality of hard mask layers having etching selectivity different from each other are formed in the trench 210 by self-aligned manner to define an embodiment of the present invention by a subsequent etching process. The position of the diffusion source layer 2 2 8 or the diffusion region 230. Referring to FIG. 7, an insulating layer 224 is formed in the trench 210 by a deposition and etching back process, and covers the bottom insulating pad layer 216, the shielding layer 208, and a portion of the top insulating pad layer 222. As shown in Fig. 7, the top surface of the insulating layer 224 is lower than the surface of the substrate 200 and higher than the top surface of the shielding layer 208. In an embodiment of the invention, the insulating layer 224 may be an oxide, such as a porous oxide. Then, the deposition and returning process can be reused '9095-A34446TWF 8 201119000
於溝槽210中形成一多晶矽層260 ’並覆蓋絕緣層224。如 第7圖所示，多晶石夕層260的頂面略低於基板2〇0的表面， 舉例來說’多晶矽層260的頂面低於基板2〇〇的表面的值 可介於ΙΟΟΑ〜2000Α之間。然後，對多晶石夕層“ο進行— 離子植入步驟262。如苐7圖所示’由於離子植入步驟262 的方向（即為元件付说262前頭的方向）與基板200表面且 有一夾角a ’其值例如可介於30°至80。之間，因此離子植 入步驟262可於多晶矽層260形成一摻雜區26如和一非摻 雜區260b。如第7圖所示，由於多晶矽層26〇的頂面略低 於基板200的表面，因而基板2〇〇會在離子植入步驟262 期間產生遮蔽效應，所以形成的摻雜區26〇a與非摻雜區 260b的邊界(boundary)自左至右逐漸向下延伸。在本發明 一實施例中，多晶矽層260可為未摻雜多晶矽（und〇ped polysilicon)。在本發明一實施例中，離子植入步驟262的 摻質可為二氟化硼（BF2)。 接著，請參考第8圖，可對多晶矽層260進行一濕蝕 刻^程’移除部分的摻雜區26〇a和非摻雜區260b，直到 暴路出。p刀絕緣層224為止。在濕蝕刻製程期間，如第7 圖所：的具有摻質的摻雜區260a的蝕刻速率會小於不具 =貝的非搀雜區260b 者彼此間具有姓刻選擇比，因 二=摻雜區260a厚度愈厚的多晶矽層26〇的移除量會少 摻雜區260a厚度愈薄的多晶石夕層·。所以，如第 漸;：：經過T製程之後，會形成厚度自右至左逐 柯支，寻的弟二硬遮罩層260C。 然後，請參考第9圖，可利用第二硬遮罩層26〇c做氣A polysilicon layer 260' is formed in the trench 210 and covers the insulating layer 224. As shown in FIG. 7, the top surface of the polycrystalline layer 260 is slightly lower than the surface of the substrate 2〇0. For example, the value of the top surface of the polycrystalline germanium layer 260 is lower than the surface of the substrate 2〇〇. ~2000Α between. Then, the polycrystalline layer is "etched - ion implantation step 262. As shown in Fig. 7, the direction of the ion implantation step 262 (i.e., the direction in front of the component 262) and the surface of the substrate 200 are present. The angle a ' may be, for example, between 30° and 80°, so the ion implantation step 262 may form a doped region 26 such as a non-doped region 260b in the polysilicon layer 260. As shown in FIG. Since the top surface of the polysilicon layer 26 is slightly lower than the surface of the substrate 200, the substrate 2 turns a shadowing effect during the ion implantation step 262, so the boundary between the formed doped region 26a and the undoped region 260b is formed. The boundary layer 260 is gradually extended downward from left to right. In an embodiment of the invention, the polysilicon layer 260 may be an undoped polysilicon. In an embodiment of the invention, the ion implantation step 262 The dopant may be boron difluoride (BF2). Next, referring to FIG. 8, the polysilicon layer 260 may be subjected to a wet etching process to remove portions of the doped regions 26a and 260b until Storm path. p knife insulation layer 224. During the wet etching process, as shown in Figure 7. The etch rate of the doped region 260a having a dopant is smaller than that of the non-doped region 260b having no scallops, and the ratio of the polysilicon layer 26 愈 is thicker due to the thickness of the second doped region 260a. In addition, the thinner doped layer 260a has a thinner polycrystalline stone layer. Therefore, as the gradual;:: After the T process, a thickness is formed from right to left, and the second hard cover is found. Layer 260C. Then, please refer to Figure 9, which can be made with the second hard mask layer 26〇c
9095-A34446TWF 201119000 蝕刻硬遮罩層，進行例如乾蝕刻之一非等向蝕刻製程，移 除未被第二硬遮罩層260c覆蓋的絕緣層224，直到暴露出 部分遮蔽層208和部分底部絕緣墊層216為止。在本發明 一實施例中，因為由多晶矽層260形成的第二硬遮罩層 260c與絕緣層224為不同的材質，例如，絕緣層224為氧 化物，而第二硬遮罩層260c為多晶矽，因此，可以選用適 當的蝕刻劑，以使絕緣層224具有較第二硬遮罩層260c高 的蝕刻率（具有良好的蝕刻選擇比）。經過非等向蝕刻製程 之後，係形成第一硬遮罩層224a，其具有凹陷262，並暴 露出部分頂部絕緣墊層222、部分遮蔽層208和部分底部 絕緣墊層216。 之後，再利用第一硬遮罩層224a、第二硬遮罩層260c 和暴露的頂部絕緣墊層222和底部絕緣墊層216做為蝕刻 硬遮罩層，進行例如濕餘刻之一等向餘刻製程，移除未被 第一硬遮罩層224a覆蓋的遮蔽層208，以暴露出溝槽210 的部分側壁226。在本發明一實施例中，由於第一硬遮罩 層224a、第二硬遮罩層260c與遮蔽層208分別為不同的材 質，例如，第一硬遮罩層224a、頂部絕緣墊層222和底部 絕緣墊層216為氧化物，第二硬遮罩層260c為多晶矽，而 遮蔽層208為氮化物，因此，可以選用適當的蝕刻劑，以 使遮蔽層208具有較第一硬遮罩層224a、頂部絕緣墊層 222、底部絕緣墊層216和第二硬遮罩層260c高的蝕刻率 (具有良好的蝕刻選擇比）。經過等向蝕刻製程之後，係移 除未被第一硬遮罩層224a覆蓋的遮蔽層208，以暴露出溝 槽210的部分侧壁226。 9095-A34446TWF 10 201119000 然後’請參考S ίο圖，可利用濕姓刻方式，移 一硬遮罩層224a和第二硬遮罩層26〇c 〇 十、 之後’凊參考弟11圖，可進杆_ 退仃預清潔步驟 (pre-clean)’以移除位於溝槽210的側壁226上的例如原 氧化物（native oxide)。接著，可利用例如化學氣相沉二= (CVD)之薄膜沉積方式以及後續的回餘刻步驟以於溝样 210暴露的側壁226上形成擴散源層228。如第u圖所'八曰 其擴散源層228係鄰接遮蔽層208，且與遮蔽層位_於 相同高度。在本發明-實施例中，擴散源層⑽可為$ 多晶矽層之導電層’例如為摻雜砷的多晶矽層(“do: poly)。然後，可利用例如退火製程，將擴散源層^ .質擴散進入鄰接的基板2GG中’以於鄰接擴散源層如^ 部分基板200中形成一擴散區230。在本發明一實施例中， 擴散區.230可做為位元線與垂直電晶體之汲極^擴=接面 (diffusion junction)，而後續形成的導電插塞係藉由擴散源 層228和擴散區230電性連接至垂直電晶體的汲極。= 板200的導電類型為p型之一實施例中，擴散區23〇的^ 電類型可為η型。擴散區230的導電類型係依據擴散源層 228的摻質的導電類型而定，但非限定本實施例。'之後: 可進行石夕化製程，於溝槽210分別形成石夕化物層232，且 覆盍擴散源層228的側壁。在本發明一實施例中，矽化物 層232可包括鈦石夕化物或钻石夕化物，其用以降低擴散源層 2 2 8與後續形成的導電插塞之間的電阻。 接著’請參考第12圖’可利用物理氣相沉積法(Pvd)、 化學氣相沉積法(CVD)、原子層沉積法(ALD)或其組合，伞'9095-A34446TWF 201119000 Etching the hard mask layer, performing an anisotropic etching process such as dry etching, removing the insulating layer 224 not covered by the second hard mask layer 260c until a portion of the masking layer 208 and a portion of the bottom insulating layer are exposed The mat layer 216 is up. In an embodiment of the present invention, since the second hard mask layer 260c and the insulating layer 224 formed of the polysilicon layer 260 are made of different materials, for example, the insulating layer 224 is an oxide, and the second hard mask layer 260c is a polysilicon layer. Thus, a suitable etchant can be selected such that the insulating layer 224 has a higher etch rate (with a good etch selectivity ratio) than the second hard mask layer 260c. After the non-isotropic etching process, a first hard mask layer 224a is formed which has recesses 262 and exposes a portion of the top insulating pad layer 222, a portion of the masking layer 208, and a portion of the bottom insulating pad layer 216. Thereafter, the first hard mask layer 224a, the second hard mask layer 260c, and the exposed top insulating pad layer 222 and the bottom insulating pad layer 216 are used as an etched hard mask layer, for example, one of the wet residuals is used. The masking process 208 removes the masking layer 208 that is not covered by the first hard mask layer 224a to expose portions of the sidewalls 226 of the trenches 210. In an embodiment of the invention, the first hard mask layer 224a, the second hard mask layer 260c and the shielding layer 208 are respectively made of different materials, for example, the first hard mask layer 224a, the top insulating layer 222, and The bottom insulating layer 216 is an oxide, the second hard mask layer 260c is a polysilicon, and the shielding layer 208 is a nitride. Therefore, a suitable etchant may be selected so that the shielding layer 208 has a first hard mask layer 224a. The top insulating pad layer 222, the bottom insulating pad layer 216, and the second hard mask layer 260c have a high etching rate (having a good etching selectivity ratio). After the isotropic etch process, the masking layer 208 that is not covered by the first hard mask layer 224a is removed to expose portions of the sidewalls 226 of the trench 210. 9095-A34446TWF 10 201119000 Then 'Please refer to the S ίο diagram, you can use the wet surname to move a hard mask layer 224a and the second hard mask layer 26〇c 〇10, after the '凊 reference brother 11 map, can enter The rod _ pre-cleaning 'pre-clean' to remove, for example, native oxide on the sidewall 226 of the trench 210. Next, a diffusion source layer 228 can be formed on the exposed sidewalls 226 of the trench 210 using, for example, a thin film deposition method of chemical vapor deposition (CVD) and a subsequent back-receiving step. As shown in Fig. u, the diffusion source layer 228 is adjacent to the shielding layer 208 and has the same height as the shielding layer. In the present invention-embodiment, the diffusion source layer (10) may be a conductive layer of a polycrystalline germanium layer, such as an arsenic doped polysilicon layer ("do: poly"). Then, for example, an annealing process may be utilized to diffuse the source layer. The diffusion is introduced into the adjacent substrate 2GG to form a diffusion region 230 adjacent to the diffusion source layer, such as the portion of the substrate 200. In an embodiment of the invention, the diffusion region 230 can be used as a bit line and a vertical transistor. The drain plug is a diffusion junction, and the subsequently formed conductive plug is electrically connected to the drain of the vertical transistor by the diffusion source layer 228 and the diffusion region 230. = The conductivity type of the board 200 is p-type In one embodiment, the type of the diffusion region 23A may be an n-type. The conductivity type of the diffusion region 230 depends on the conductivity type of the dopant of the diffusion source layer 228, but is not limited to the embodiment. The lithography process can be performed to form a lithographic layer 232 in the trenches 210 and to cover the sidewalls of the diffusion source layer 228. In an embodiment of the invention, the bismuth compound layer 232 can include titanium lithium or diamond eve a compound for reducing the diffusion source layer 2 28 and subsequent formation A resistor interposed between the plug Next 'Please refer to FIG. 12' may use a physical vapor deposition (Pvd), chemical vapor deposition (CVD), atomic layer deposition (ALD), or combinations thereof, umbrella '
9095-A34440 丁 WF 11 201119000 溝槽210中形成導電插塞240，且覆蓋擴散源層228的側 壁。如第12圖所示，導電插塞240覆蓋底部絕緣墊層216 和部分頂部絕緣塾層222 ’導電插塞240a和220b的頂面 237低於基板200。在本發明一實施例中，導電插塞240可 分別包括外層之阻障層234和内層之導電層236，其中阻 障層23 4分別覆盖底部絕緣塾層216和部分頂部絕緣塾層 222 ’而導電層236覆蓋阻障層234。在本發明一實施例中， 阻障層234可包括鈦、氮化鈦或其組合，而導電層236可 包括例如鎢之金屬。在本實施例中，阻障層234可為鈦和 氮化鈦組成的疊層。之後’可利用例如化學氣相沉積法 (CVD)及後續之例如化學機械研磨（CMP)之平坦化製程，於 溝槽210中形成覆蓋層258，且覆蓋導電插塞240。在本發 明一實施例中，覆蓋層258的頂面與基板200共平面。經 過上述製程之後，係形成本發明一實施例之埋藏位元線 500a。 本發明一實施例係提供例如DRAM的一埋藏位元線 5〇〇a及其製造方法’其令埋藏位元線500a係經由設於溝槽 210中一侧（single side)的擴散源層228和鄰接的擴散區230 電性連接至其上的垂直電晶體。另外，擴散源層228鄰接 遮蔽層208 ’且與遮蔽層208位於相同高度。另外，擴散 源層228的位置係利用自對準（seif_aiigned)方式於溝槽210 中形成蝕刻選擇比彼此不同的複數層硬遮罩層，再藉由後 續的蝕刻製程定義出來。 第13a圖係顯示本發明另一實施例之DRAM 600b的 透視圖。第13b圖為沿第13a圖的A-A，切線的剖面圖，其 9095-A34446TWF 12 201119000 顯不本發明另一貫施例之DRAM的埋藏位元線500b的剖 面圖。第14〜i 5圖係顯示本發明另一實施例之D RA M的埋 藏位元線的製造方法的剖面示意圖。上述圖式中的各元件 如有與第la〜12圖所示相同或相似的部分，則可參考前面 的相關敍述，在此不做重複說明。 第13a圖係顯不本發明另—實施例之dram _b的 透視圖。第13b圖為沿第Ha圖的A_A，切線的剖面圖，其 顯不本發明另-貫施例之dram的之埋藏位元線500b的 •剖面圖。上述DRAM 6〇〇b的埋藏位元線5〇Ob與如第la 和lb圖所示之DRAM 600a的埋藏位元線5〇〇a的不同處為 埋藏位元線50〇b不具有擴散源層228。上述DRAM 6〇〇b 的埋藏位元線500b的製造方法將利用第14〜15圖說明。 第14〜15圖係顯不本發明另—實施例2Dram的埋藏 位元線5GGb的製造方法的剖面示㈣，其特別顯示僅具有 擴散區230之DRAM的埋藏位元線5〇〇b的製造方法。請 參考第14圖，於溝槽210中形成遮蔽層2〇8、頂部絕緣墊 • ^ 222 *底部絕緣墊層216，並移除部分遮蔽層通，以暴 路溝槽210的部分側壁226之後，可進行一預清潔步驟 (Pi*e-Clean)’以移除位於溝槽21〇的側壁226上的例如原生 氧化物（native oxide)。接著，可利用氣相摻雜（gas/vap〇r d〇Ping)方式’將含有摻質的氣體從溝槽210暴露的側壁226 庄入其鄰接的部分基板200中，以形成擴散區230。在本 發月只把例中’氣相摻雜（gas/vapor doping)方式可包括 向溫快速氣相摻雜（RVD)、室溫氣相摻雜、氣體沉浸雷射 推雜（GILD)等。在本發明一實施例中，擴散區23〇可做拜 --Zr9095-A34440 D WF 11 201119000 A conductive plug 240 is formed in the trench 210 and covers the side walls of the diffusion source layer 228. As shown in Fig. 12, the conductive plug 240 covers the bottom insulating pad layer 216 and a portion of the top insulating germanium layer 222'. The top surface 237 of the conductive plugs 240a and 220b is lower than the substrate 200. In an embodiment of the invention, the conductive plugs 240 may respectively include an outer barrier layer 234 and an inner conductive layer 236, wherein the barrier layer 23 4 covers the bottom insulating layer 216 and a portion of the top insulating layer 222', respectively. Conductive layer 236 covers barrier layer 234. In an embodiment of the invention, barrier layer 234 may comprise titanium, titanium nitride, or a combination thereof, and conductive layer 236 may comprise a metal such as tungsten. In the present embodiment, the barrier layer 234 may be a laminate of titanium and titanium nitride. Thereafter, a capping layer 258 is formed in the trench 210 by a planarization process such as chemical vapor deposition (CVD) and subsequent chemical mechanical polishing (CMP), and the conductive plug 240 is covered. In an embodiment of the invention, the top surface of the cover layer 258 is coplanar with the substrate 200. After the above process, the buried bit line 500a of one embodiment of the present invention is formed. An embodiment of the present invention provides a buried bit line 5a of a DRAM and a method of fabricating the same, which causes the buried bit line 500a to pass through a diffusion source layer 228 disposed on a side of the trench 210. And a vertical transistor that is electrically connected to the adjacent diffusion region 230. Additionally, diffusion source layer 228 abuts shielding layer 208' and is at the same height as shielding layer 208. In addition, the position of the diffusion source layer 228 is formed by a self-aligned (seif_aiigned) manner in the trench 210 to form a plurality of hard mask layers having different etching selectivity than each other, and then defined by a subsequent etching process. Fig. 13a is a perspective view showing a DRAM 600b according to another embodiment of the present invention. Fig. 13b is a cross-sectional view taken along line A-A of Fig. 13a, tangential, and 9095-A34446TWF 12 201119000 showing a cross-sectional view of the buried bit line 500b of the DRAM of another embodiment of the present invention. Figs. 14 to 5 are schematic cross-sectional views showing a method of manufacturing a buried bit line of D RA M according to another embodiment of the present invention. For the components in the above drawings, if they have the same or similar parts as those shown in Figs. 1 to 12, reference may be made to the related description, and the description thereof will not be repeated. Fig. 13a is a perspective view showing a dram_b of another embodiment of the present invention. Fig. 13b is a cross-sectional view taken along line A_A of the Ha diagram, which shows a cross-sectional view of the buried bit line 500b of the dram of another embodiment of the present invention. The difference between the buried bit line 5〇Ob of the above DRAM 6〇〇b and the buried bit line 5〇〇a of the DRAM 600a as shown in FIGS. 1a and 1b is that the buried bit line 50〇b has no diffusion source. Layer 228. The method of manufacturing the buried bit line 500b of the above DRAM 6〇〇b will be described using Figs. 14 to 15. Figs. 14 to 15 show a cross-sectional view (4) of a method of manufacturing the buried bit line 5GGb of the second embodiment of the present invention, which particularly shows the fabrication of the buried bit line 5〇〇b of the DRAM having only the diffusion region 230. method. Referring to FIG. 14, a shielding layer 2〇8, a top insulating pad•^222* bottom insulating pad layer 216 are formed in the trench 210, and a portion of the shielding layer pass is removed to cover a portion of the sidewall 226 of the trench 210. A pre-cleaning step (Pi*e-Clean) can be performed to remove, for example, a native oxide on the sidewall 226 of the trench 21〇. Next, the gas-doped (gas/vap〇r d〇Ping) method can be used to mold the gas containing the dopant from the sidewalls 226 of the trench 210 into its adjacent portion of the substrate 200 to form the diffusion region 230. In this month, only the gas/vapor doping method can include temperature fast gas phase doping (RVD), room temperature gas phase doping, gas immersion laser doping (GILD), etc. . In an embodiment of the invention, the diffusion region 23 can be made to worship -Zr
9〇95-A34446TWF 13 201119000 位元線與垂直電晶體之汲極的擴散接面（diffusi〇n junction)。在基板200的導電類型為p型之一實施例中， 擴散區230的導電類型可為n型。擴散區23〇的導電類型 係依據氣體摻質的導電類型而定，但非限定本實施例。如 第14圖所示，擴散區23〇與遮蔽層2〇8實質上位於相同的 南度。 或者，在本發明其他實施例中，也可藉由一摻雜介電 層形成擴散區230。請參考第16圖，於溝槽21〇中形成遮 蔽層208、頂部絕緣墊層222和底部絕緣墊層216，並移除 部分遮敝層208 ’以暴露溝槽210的部分側壁226之後， 可進行一預清潔步驟(pre_clean)，以移除位於溝槽21〇的侧 壁226上的例如原生氧化物(native 〇xide)。接著，可利用 化學氣相沉積法(CVD)之薄膜沉積方式，順應性於溝槽21〇 内側形成一摻雜介電層262,並覆蓋側壁226。本實施例 中，摻雜介電層262可為砷玻璃(Asglass〇xide)。然後，可 利用例如退火製程，將摻雜介電層262的摻質從側壁 擴散進入鄰接的基板200中，以形成一擴散區23〇。之後， 再利用濕蝕刻方式，移除摻雜介電層262。9〇95-A34446TWF 13 201119000 Bit line and the diffusion junction of the vertical transistor (diffusi〇n junction). In an embodiment in which the conductivity type of the substrate 200 is a p-type, the conductivity type of the diffusion region 230 may be an n-type. The conductivity type of the diffusion region 23 is determined depending on the conductivity type of the gas dopant, but is not limited to the embodiment. As shown in Fig. 14, the diffusion region 23A and the shielding layer 2〇8 are substantially at the same southness. Alternatively, in other embodiments of the invention, diffusion region 230 may also be formed by a doped dielectric layer. Referring to FIG. 16, a masking layer 208, a top insulating pad layer 222 and a bottom insulating pad layer 216 are formed in the trench 21, and a portion of the concealing layer 208' is removed to expose a portion of the sidewall 226 of the trench 210. A pre-cleaning step (pre_clean) is performed to remove, for example, native 〇xide on the sidewall 226 of the trench 21〇. Next, a doped dielectric layer 262 may be formed on the inner side of the trench 21A by a thin film deposition method using chemical vapor deposition (CVD), and cover the sidewall 226. In this embodiment, the doped dielectric layer 262 can be arsenic glass (Asglass®). The dopant of the doped dielectric layer 262 can then be diffused from the sidewalls into the adjacent substrate 200 using, for example, an anneal process to form a diffusion region 23A. Thereafter, the doped dielectric layer 262 is removed by wet etching.
經過如第14和16圖所示之不同方式形成擴散區23〇 之後，請參考第15圖，可利用物理氣相沉積法(PVD)於 溝槽210中分別形成導電插塞24〇，且覆蓋遮蔽層2〇8和 擴散區230的侧壁。如第15圖所示，導電插塞24〇覆蓋底 部絕緣墊層216和部分頂部絕緣塾層222，導電插塞· 的頂面237低於基板200。在本發明一實施例中，導電插 塞240可分別包括外層之阻障層说和内層之導電層挪， 9095-A34446TWF 14 201119000 其中阻障層234覆蓋底部絕緣塾層216和部分頂部絕緣塾 層222，而導電層236覆蓋阻障層234。在本發明一實施例 中’阻障層234可包括欽、氮化欽或其組合，而導電層a% 可包括例如鎢之金屬。在本實施例中，阻障層234可為鈦 和氮化鈦組成的疊層結構。之後，可利用例如化學氣相沉 積法（CVD)及後讀之例如化學機械研磨（CMP)之平坦化製 程，於溝槽210中形成例如氧化層之覆蓋層258，且覆蓋 導電插塞240。在本發明一實施例中，覆蓋層258的頂面 _ 與基板200共平面。經過上述製程之後，係形成本發明另 一實施例之例如DRAM的位元線之一埋藏位元線5〇〇b。 本發明另一實施例係提供例如DRAM的埋藏位元線 500b及其製造方法，其中埋藏位元線5〇〇b係經由設於溝 槽210中一側的擴散區230電性連接至其上的垂直電晶 體。另外，擴散區230與遮蔽層208實質上位於相同的高 度。再者，擴散區230的位置係利用自對準（self_aligned) 方式於溝槽21 〇中形成钱刻選擇比彼此不同的複數層硬遮 • 罩層’再藉由後續的蝕刻製程定義出來。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明’任何熟習此技藝者，在不脫離本發明之精神和範 圍内’當可作些許之更動與潤斜’因此本發明之保護範圍 當視後附之申請專利範圍所界定為準。 【圖式簡單說明】 第1a圖係顯示本發明一實施例之動態隨機存取記憶 體晶胞的透視圖。 9095-A34446TWF 15 201119000 第lb圖為沿第la圖的A-A’切線的剖面圖，其顯示本 發明一實施例之動態隨機存取記憶體晶胞的埋藏位元線。 第2〜12圖係顯示本發明一實施例之動態隨機存取記 憶體晶胞的埋藏位元線的製造方法的剖面示意圖。 第13a圖係顯示本發明另一實施例之動態隨機存取記 憶體晶胞的透視圖。 第13b圖為沿第13a圖的A-A’切線的剖面圖，其顯示 本發明另一實施例之動態隨機存取記憶體晶胞的埋藏位元 線。 第14〜16圖係顯示本發明另一實施例之動態隨機存取 記憶體晶胞的埋藏位元線的製造方法的剖面示意圖。 【主要元件符號說明】 200〜基板； 202〜子溝槽； 210〜溝槽； 204、212〜底面； 206、214、22 卜 225、226〜側壁； 208〜遮蔽層； 209、217、220、237、255〜頂面； 216〜底部絕緣墊層； 218〜光阻； 222〜頂部絕緣墊層； 224〜絕緣層； 224a〜第一硬遮罩層； 9095-A34446TWF 16 201119000 228〜擴散源層； 230〜擴散區； 232〜矽化物層； 234〜阻障層； 236〜導電層， 240〜導電插塞； 252〜保護層； 256〜絕緣層； 258〜覆蓋層； 260〜多晶矽層； 26〇3•〜推雜區， 260b〜非摻雜區； 260c〜第二硬遮罩層； 262〜摻雜介電層262 ; 300〜垂直電晶體； 302〜垂直側壁； 306〜絕緣層； 308〜字元線； 312〜電容； 314〜〉及極區， 316〜通道區； 318〜源極區， 320〜第一方向； 322〜第二方向； a〜角度； 9095-A34446TWF 17 201119000 500a、500b〜埋藏位元線； 600a、600b〜動態隨機存取記憶體晶胞。After the diffusion regions 23 are formed in different manners as shown in FIGS. 14 and 16, referring to FIG. 15, the conductive plugs 24 can be formed in the trenches 210 by physical vapor deposition (PVD), respectively, and covered. The shielding layer 2〇8 and the sidewalls of the diffusion region 230. As shown in Fig. 15, the conductive plug 24A covers the bottom insulating pad layer 216 and a portion of the top insulating germanium layer 222, and the top surface 237 of the conductive plug is lower than the substrate 200. In an embodiment of the invention, the conductive plugs 240 may respectively include a barrier layer of the outer layer and a conductive layer of the inner layer, 9095-A34446TWF 14 201119000, wherein the barrier layer 234 covers the bottom insulating layer 216 and a portion of the top insulating layer 222, and conductive layer 236 covers barrier layer 234. In an embodiment of the invention, the barrier layer 234 may comprise chin, nitrite or a combination thereof, and the conductive layer a% may comprise a metal such as tungsten. In the present embodiment, the barrier layer 234 may be a laminated structure composed of titanium and titanium nitride. Thereafter, a capping layer 258 such as an oxide layer may be formed in the trench 210 by a planarization process such as chemical vapor deposition (CVD) and post-reading such as chemical mechanical polishing (CMP), and the conductive plug 240 may be covered. In an embodiment of the invention, the top surface _ of the cover layer 258 is coplanar with the substrate 200. After the above process, a bit line 5 〇〇b of one of the bit lines of the DRAM of another embodiment of the present invention is formed. Another embodiment of the present invention provides a buried bit line 500b such as a DRAM, and a method of fabricating the same, wherein the buried bit line 5〇〇b is electrically connected thereto via a diffusion region 230 provided on one side of the trench 210. Vertical transistor. Additionally, diffusion region 230 is substantially at the same height as masking layer 208. Moreover, the position of the diffusion region 230 is defined by a self-aligned manner in the trench 21 形成 to form a plurality of hard mask layers different from each other and then defined by a subsequent etching process. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention to those skilled in the art, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1a is a perspective view showing a dynamic random access memory cell of an embodiment of the present invention. 9095-A34446TWF 15 201119000 Figure lb is a cross-sectional view taken along line A-A' of Fig. 1a showing the buried bit line of the DRAM cell of an embodiment of the present invention. Figs. 2 to 12 are schematic cross-sectional views showing a method of manufacturing a buried bit line of a dynamic random access memory cell according to an embodiment of the present invention. Figure 13a is a perspective view showing a dynamic random access memory cell of another embodiment of the present invention. Fig. 13b is a cross-sectional view taken along line A-A' of Fig. 13a showing the buried bit line of the DRAM cell of another embodiment of the present invention. Figs. 14 to 16 are schematic cross-sectional views showing a method of manufacturing a buried bit line of a dynamic random access memory cell according to another embodiment of the present invention. [Description of main component symbols] 200 to substrate; 202 to sub-trench; 210 to trench; 204, 212 to bottom; 206, 214, 22, 225, 226 to sidewall; 208 to shielding layer; 209, 217, 220, 237, 255~ top surface; 216~ bottom insulating pad; 218~ photoresist; 222~ top insulating pad; 224~ insulating layer; 224a~ first hard mask layer; 9095-A34446TWF 16 201119000 228~ diffusion source layer 230~diffusion zone; 232~ telluride layer; 234~ barrier layer; 236~ conductive layer, 240~ conductive plug; 252~ protective layer; 256~ insulating layer; 258~ cover layer; 260~ polycrystalline layer; 〇3•~ erbium region, 260b~undoped region; 260c~second hard mask layer; 262~doped dielectric layer 262; 300~vertical transistor; 302~vertical sidewall; 306~insulating layer; ~ word line; 312~capacitor; 314~> and polar region, 316~channel region; 318~source region, 320~ first direction; 322~second direction; a~angle; 9095-A34446TWF 17 201119000 500a, 500b~buried bit line; 600a, 600b~ dynamic random access memory cell.
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