TWI483547B - Capacitance sensing circuit with anti-electromagnetic capability - Google Patents

Description

Capacitive sensing circuit with anti-electromagnetic interference capability

The invention relates to a capacitance sensing circuit, in particular to a capacitance sensing circuit with electromagnetic interference resistance.

According to the development of computer technology, the application of capacitive sensing is widely used, such as fingerprint identification, MEMS accelerometers and capacitive touch panels. Capacitance vs. frequency is commonly used in traditional capacitive sensing technology. For the circuit to be converted, please refer to the first figure, which is a block diagram of a conventional capacitive sensing device. As shown in the figure, the prior art is configured to form an oscillating circuit through a first comparator 100', a second comparator 102', a control circuit 104', and a resistor 106'. The oscillating circuit is coupled to a test unit. Capacitor 108', and using the difference in capacitance value of the capacitor 108' to be tested, different oscillation frequencies are generated, and the capacitance value of the capacitor 108' to be tested is known according to different oscillation frequencies to achieve capacitance detection. purpose.

Furthermore, please refer to the second figure together as a block diagram of another capacitive sensing device of the prior art. As shown, the prior art generates a fixed slope by forming a fixed current source 200', a first control switch 201', a second control switch 202', an integrating capacitor 203', and a comparator 204'. The circuit, the fixed slope generating circuit is coupled to a capacitor 205' to be tested, and uses different capacitance values of the capacitor 205' to be tested, and the starting voltage is different, so that the enabling time of the comparator 204' is different to achieve capacitance detection. the goal of.

In addition, please refer to the third figure together, which is another capacitive sensing device of the prior art. Block diagram. As shown, the prior art technique forms a generation time-to-digital converter through a complex buffer 300', a frequency phase detector 301', a control unit 302', and a controllable buffer 303'. The generation time-to-digital converter is coupled to a capacitor 304 to be tested, and generates a time-to-digital converter that utilizes a difference in the magnitude of the capacitance of the capacitor 304 to be tested to cause a time difference of the control signal output by the control unit 302'. To achieve the purpose of capacitance detection.

However, the techniques in the above first to third figures are not immune to electromagnetic interference. In particular, the application of capacitive sensors generally needs to be combined with peripheral circuits such as microprocessors. When electromagnetic noise is capacitively coupled to In the comparator, the oscillation frequency will be distorted, or the initial voltage will be misaligned, so that the detection of the capacitance is wrong. The above circuit and the detection of the capacitance are more complicated than the clock cycle.

Therefore, how to solve the above problems and propose a novel capacitive sensing circuit with anti-electromagnetic interference capability, which can avoid the influence of electromagnetic noise on the performance of the capacitive sensing circuit, so that the above problems can be solved.

One of the objects of the present invention is to provide a capacitive sensing circuit with electromagnetic interference resistance, which eliminates common mode noise by a differential circuit to achieve electromagnetic interference resistance.

One of the objects of the present invention is to provide a capacitance sensing circuit with electromagnetic interference resistance, which adjusts the output of a filter by dynamic range, so that the capacitance sensing circuit has the characteristics of low time-consuming pulse period.

One of the objectives of the present invention is to provide a capacitive sensing circuit with electromagnetic interference resistance, which eliminates the influence of the parasitic capacitance of the capacitor to be tested by a fifth switch and a sixth switch, thereby increasing the capacitance sensing circuit. The dynamic measurement range of the capacitor to be tested.

The capacitive sensing circuit with electromagnetic interference resistance of the present invention comprises a filter and a differential circuit. The filter is coupled to a capacitor to be tested, and receives a plurality of reference signals to generate a first filtered signal and a second filtered signal, and the differential circuit receives the first filtered signal and the second filtered signal, and eliminates the first filtered signal. The common mode noise of the filtered signal generates a differential signal, and the magnitude of the differential signal is related to the size of the capacitor to be tested, and achieves the purpose of detecting the capacitance to be tested. The common mode noise is eliminated by the differential circuit to achieve the capability of resisting electromagnetic interference, and the differential circuit can adjust the output of the filter in a dynamic range, so that the capacitance sensing circuit has the characteristics of low time-consuming pulse period.

Conventional technology:

100’‧‧‧First comparator

102’‧‧‧Second comparator

104'‧‧‧Control circuit

106’‧‧‧Resistance

108’‧‧‧Measured capacitance

200'‧‧‧ constant current source

201’‧‧‧First control switch

202’‧‧‧Second control switch

203'‧‧‧Integral Capacitance

204'‧‧‧ comparator

205’‧‧‧Measured capacitance

300’‧‧‧Multiple buffers

301’‧‧‧ Frequency Phase Detector

302’‧‧‧Control unit

303'‧‧‧Controllable buffer

304'‧‧‧Measured capacitance

this invention:

10‧‧‧ filter

11‧‧‧Switch Module

120‧‧‧First switch

122‧‧‧Second switch

124‧‧‧third switch

126‧‧‧fourth switch

14‧‧‧First output capacitor

16‧‧‧First output switch

18‧‧‧second output capacitor

19‧‧‧Second output switch

20‧‧‧Differential circuit

30‧‧‧Measured capacitance

32‧‧‧Parasitic capacitance

40‧‧‧Amplifier

50‧‧‧Amplifier

60‧‧‧ fifth switch

62‧‧‧ sixth switch

The first figure is a block diagram of a conventional capacitive sensing device; the second figure is a block diagram of another capacitive sensing device of the prior art; and the third figure is another capacitive sensing of the prior art. 4 is a block diagram of a capacitive sensing circuit according to a preferred embodiment of the present invention; and FIG. 5 is a circuit diagram of a filter of a preferred embodiment of the fourth embodiment; The output waveform diagram of the capacitance sensing circuit of a preferred embodiment of the present invention; the seventh diagram is a timing diagram of the switch control according to a preferred embodiment of the present invention; and the seventh diagram is the present invention. A timing diagram of a switch control of another preferred embodiment; an eighth diagram is a circuit diagram of a filter according to another preferred embodiment of the present invention; and a ninth diagram is a filter of another preferred embodiment of the present invention. 10A is a timing diagram of a ninth diagram of a preferred embodiment of the present invention; and a tenth diagram is a timing diagram of a ninth diagram of another preferred embodiment of the present invention; Figure C is a timing diagram of a ninth diagram of another preferred embodiment of the present invention; The timing diagram of a ninth preferred embodiment according to FIG.; And Figure 11 is a circuit diagram of a filter of another preferred embodiment of the present invention.

In order to provide a better understanding and understanding of the structural features and the efficacies of the present invention, please refer to the preferred embodiment and the detailed description, as explained below: please refer to the fourth figure. A block diagram of a capacitive sensing circuit in accordance with a preferred embodiment of the invention. As shown in the figure, the capacitive sensing circuit with electromagnetic interference resistance of the present invention can be applied to fingerprint recognition, acceleration sensors and touch panels. The capacitance sensing circuit includes a filter 10 and a differential circuit 20. The filter 10 is coupled to a capacitor 30 to be tested, and the filter 10 receives a plurality of reference signals to generate a first filtered signal and a second filtered signal. The filter 10 receives a first reference signal V _REF1 and a second reference. A first filtered signal and a second filtered signal are generated by the signal V _REF2 , a third reference signal V _REF3 and a fourth reference signal V _REF4 , wherein a preferred embodiment of the filter 10 of the present invention is a finite pulse Response Filter (Finite Impulse Response, FIR).

The differential circuit 20 receives the first filtered signal and the second filtered signal, and the differential circuit 20 cancels the common mode noise of the first filtered signal and the second filtered signal to generate a differential signal, wherein the magnitude of the differential signal is related to the measured signal. The size of the capacitor 30, that is, the difference circuit 20 can calculate the difference between the first filtered signal and the second filtered signal to generate a differential signal, since the differential signal is related to the capacitor 30 to be tested, that is, the capacitance value of the capacitor 30 to be tested. The size of the first filtered signal and the second filtered signal will be affected, and the magnitude of the differential signal generated by the differential circuit 20 varies according to the capacitance value of the capacitor 30 to be tested. Therefore, the subsequent circuit (not shown) can The capacitance value of the capacitor 30 to be tested is known according to the differential signal. Since the present invention utilizes the differential circuit 20 to subtract the first filter The differential signal is obtained by the signal and the second filtered signal. Therefore, when an electromagnetic interference noise is generated by the first filtered signal and the second filtered signal, the differential circuit 20 can subtract the first filtered signal and the second filtered signal. At the same time, the elimination of electromagnetic interference noise, that is, the elimination of common mode noise, in order to achieve the ability to resist electromagnetic interference. Among them, a preferred embodiment of the differential circuit 20 of the present invention is a differential amplifier.

In addition, the capacitive sensing circuit of the present invention having an anti-electromagnetic interference performance further includes an amplifier 40. The amplifier 40 is coupled to the differential circuit 20, and the amplifier 40 receives and amplifies the differential signal. The present invention forms a dynamic range adjustment circuit by the differential circuit 20 and the amplifier 40. The dynamic range adjustment circuit can effectively reduce the detection. The detection of the clock cycle of the capacitor 30, thereby reducing power consumption, to achieve power saving purposes. The amplifier 40 is a Variable Gain Amplifier (VGA).

Referring to FIG. 5 together, it is a circuit diagram of a filter which is a preferred embodiment of the fourth figure. As shown in the figure, the filter 10 of the capacitive sensing circuit with electromagnetic interference resistance of the present invention comprises a switch module 12, a first output capacitor 14, a first output switch 16, and a second output capacitor 18. A second output switch 19. The switch module 12 is coupled to the receiving capacitor 30 and receives the reference signals. The switch module 12 receives the first reference signal V _REF1 and the second reference signal V _REF2 , and the first output capacitor 14 is coupled to the switch module 12 . a first output terminal, the first output switch 16 is coupled between the first output capacitor 14 and the reference signal to generate a first filtered signal, that is, the first output switch 16 is the first output capacitor 14 and the third reference signal V _REF3 The first output signal is outputted, and the second output capacitor 18 is coupled to the second output end of the switch module 12, and the second output switch 19 is coupled between the second output capacitor 18 and the reference signal to generate a second filter. The second output switch 19 is coupled between the second output capacitor 18 and the fourth reference signal V _REF4 to output a second filtered signal.

In addition, the switch module 12 includes a first switch 120, a second switch 122, a third switch 124, and a fourth switch 126. One end of the first switch 120 is coupled to the first reference signal V _REF1 , and the other end of the first switch 120 is coupled to the receiving capacitance 30 , and one end of the second switch 122 is coupled to the receiving capacitor 30 and the first switch 120 , and the second switch 122 The other end is coupled to the first output capacitor 14, the third end of the third switch 124 is coupled to the second reference signal V _REF2 , the other end of the third switch 124 is coupled to the receiving capacitor 30 , and the other end of the fourth switch 126 is coupled to the receiving capacitor 30 and The third switch 124 and the other end of the fourth switch 126 are coupled to the second output capacitor 18 . Thus, in the present invention, the first filtered signal and the second filtered signal are generated by controlling the turn-on/turn-off sequence of the open module 12 and the second output switch 19 of the first output switch 16.

Please refer to FIG. 6 and FIG. 7A together, which are timing diagrams of output waveform diagram and switch control of the capacitance sensing circuit according to a preferred embodiment of the present invention. As shown in the figure, the capacitance sensing circuit of the present invention turns on and off the first switch 120, the second switch 122, and the third switch 124 sequentially after turning on and off the first output switch 16 and the second output switch 19. The fourth switch 126 changes the slope of the voltage of the first filtered signal V ₁ at the first output capacitor 14 , and the first output capacitor 14 is coupled to the third reference signal V _REF3 , so that the first filtered signal V ₁ is The third reference signal V _REF3 is a starting voltage and the slope of the voltage signal changes. Similarly, the second output capacitor 18 generates a voltage slope change of the second filtered signal V ₂ , that is, the second output capacitor 18 is coupled to the fourth reference signal. V _REF4 , so that the second filter signal V _{2 has} a fourth reference signal V _REF4 as a starting voltage and the slope of the voltage signal changes due to the voltage slope of the first filtered signal V _{1 and} the voltage slope of the second filtered signal V ₂ . In contrast, the difference circuit 20 can generate a differential signal by the difference value between the first filtered signal V ₁ and the second filtered signal V ₂ . The first output capacitor 14 and the second output capacitor 18 are an integral capacitor.

Please refer to Figure 5 and Figure 7A for an electromagnetic interference signal from the capacitor to be tested. 30 enters, the switching frequency is higher than the electromagnetic interference signal frequency, after the first switch 120 is turned on, the electromagnetic interference signal is stored in the capacitor 30 to be tested, after the second switch 122 is turned on, the end of the first output capacitor 14 Obtaining the difference value of the electromagnetic interference signals of the first switch 120 and the second switch 122. Since the switching switch frequency is higher than the electromagnetic interference signal frequency, the difference value is almost equal to the slope of the electromagnetic interference signal; and further, the third switch 124 is turned on. After that, the electromagnetic interference signal is stored in the capacitor 30 to be tested. After the fourth switch 126 is turned on, the end of the second output capacitor 18 obtains the electromagnetic interference signal difference between the third switch 124 and the fourth switch 126, because the switch The frequency is higher than the frequency of the electromagnetic interference signal, and the difference value is almost equal to the slope of the electromagnetic interference signal, and the slope of the common mode electromagnetic interference signal of the two signals can be eliminated through the differential circuit 20.

In addition, please refer to FIG. 7B as a timing diagram of the switch control of another preferred embodiment of the present invention. As shown in the figure, the difference between the embodiment and the embodiment of FIG. 7A is that the sequence of the switch control in this embodiment is that the first output switch 14, the second output switch 19 and the first switch 120 are simultaneously turned on/off. Then, the second switch 122, the third switch 124, and the fourth switch 126 are sequentially turned on/off. Thus, the filter of the embodiment can also generate a waveform as shown in FIG.

Please refer to the eighth figure, which is a circuit diagram of a filter according to another preferred embodiment of the present invention. As shown in the figure, the difference between this embodiment and the embodiment of the fifth embodiment is that an amplifier 50 is added to the embodiment. The amplifier 50 has a first input end, a second input end, a first output end and a second output end. The first input end and the second input end are coupled to the switch module 12, the first output end and the first output end The second output terminal is coupled between the first input end and the first output end of the amplifier 50, and the second output capacitor 18 is coupled to the first output end of the amplifier 50. Between the two input terminals and the second output terminal, one end of the first output switch 16 is coupled to the switch module 12 and the amplifier 50, and the other end of the first output switch 16 is coupled to the third reference signal V _REF3 , and the second output switch 19 The other end of the second output switch 19 is coupled to the fourth reference signal V _REF4 . Thus, since the present invention increases the amplifier 50 to increase the voltage gain to increase the amplification of the first filtered signal and the second filtered signal, the first output capacitor 14 and the second output capacitor 18 of a smaller capacitance value can be used, thereby achieving cost savings. the goal of. A preferred embodiment of the amplifier 50 of the present invention is an Operational Amplifier (OPA).

Further, please refer to the ninth drawing, which is a circuit diagram of a filter according to another preferred embodiment of the present invention. As shown in the figure, since the capacitor 30 to be tested of the present invention generates a parasitic capacitor 32, the parasitic capacitor 32 is coupled to one end of the receiving capacitor 30 and coupled to the switch module 12. Because of the relationship of the parasitic capacitance 32, the dynamic sensing range of the capacitance sensing circuit of the present invention is too small. Therefore, the present invention further includes the filter 10 of the capacitance sensing circuit of the present embodiment. A fifth switch 60 and a sixth switch 62. One end of the fifth switch 60 is coupled to the reference signal (ie, the third reference signal V _REF3 ), and the other end of the fifth switch 60 is coupled to the parasitic capacitor 32 . One end of the sixth switch 62 is coupled to the fifth switch 60 and the parasitic capacitor 32, and the other end of the sixth switch 62 is coupled to the reference signal (ie, the fourth reference signal V _REF4 ). Thus, in this embodiment, the conduction sequence of the first switch 120 to the fourth switch 126 of the switch module 12 is matched to increase the dynamic measurement range of the capacitor 30 to be tested. Hereinafter, the operation of the fifth switch 60 and the sixth switch 62 in cooperation with the first switch 120 to the fourth switch 126 of the switch module 12 will be described.

Please refer to FIG. 10A together, which is a timing diagram of the ninth diagram of a preferred embodiment of the present invention. As shown, when the first output switch 16 and the second output switch 19 are turned on, the fifth switch 60 is also turned on, and the first switch 120 is turned on after the first output switch 16 and the second output switch 19 are turned on, and fifth. The switch 60 is also turned off while the first switch 120 is turned off. At this time, the second switch 122 and the sixth switch 62 are turned on, and then the third switch 124 is turned on. When the third switch 124 is turned off, the sixth switch 62 is also turned off. The fourth switch 126 and the fifth switch 60 are turned on, and thus repeating the on/off sequence of the plurality of switches, the influence of the capacitance value of the parasitic capacitor 32 relative to the capacitance value of the capacitor 30 to be tested is reduced, and the capacitance to be tested is increased. Dynamic measurement range. Wherein, according to the sequence of the switches mentioned above, the voltage of the first output capacitor 14 is: If n approaches infinity,

That is, as described above, when the capacitance value of the capacitor 30 to be tested is much larger than the capacitance value of the parasitic capacitor 32, the parasitic capacitance 32 can be neglected, and the dynamic measurement range of the capacitor 30 to be tested is increased, that is, the embodiment can avoid V. The voltage of _{C14 overlaps} with the voltage of V _C18 too early, which affects the dynamic measurement range of the capacitor 30 to be tested. Further, the second output capacitor 18 can also be known from the above. Meanwhile, please refer to FIG. 10C, the on/off sequence between the first switch 120 and the sixth switch 62 is substantially the same as that of the tenth A picture, except that the first output switch 16 and the second output are only the first output switch 16 and the second output. While the switch 19 is turned on, the first switch 120 and the fifth switch 60 are also turned on. The rest are the same as in Figure 10A, so they are not mentioned here.

Please refer to FIG. 10B, which is a timing diagram of a ninth diagram of another preferred embodiment of the present invention. As shown in the figure, the embodiment is different from the embodiment of FIG. A in that, when the first output switch 16 and the second output switch 19 are turned on, the sixth switch 62 is also turned on, and the first switch 120 is at the first output. After the switch 16 and the second output switch 19 are turned on, the sixth switch 62 is also turned off while the first switch 120 is turned off. At this time, the second switch 122 and the fifth switch 60 are turned on, and then the third switch 124 is turned on. When the third switch 124 is turned off, the fifth switch 60 is also turned off, and then the fourth switch 126 and the sixth switch 62 are turned on, so that the above-mentioned plurality of switch on/off sequences are repeated, so that the capacitance value of the parasitic capacitor 32 is relative to the capacitance to be tested. The influence of the capacitance value of 30 is increased, and the capacitance value of the parasitic capacitor 32 is used to know the capacitance value of the capacitor 30 to be tested, so that the dynamic measurement range of the capacitor 30 to be tested can be increased. Wherein, according to the sequence of the switches mentioned above, the voltage of the first output capacitor 14 is: If n approaches infinity,

It can be seen from the above that the capacitance value of the parasitic capacitance 32 is much larger than the capacitance value of the capacitance 30 to be tested, and the capacitance value of the parasitic capacitance 32 is passed to know the capacitance value of the capacitance 30 to be tested, so that the capacitance to be tested can be increased by 30. The dynamic measurement range, that is, the embodiment can prevent the voltage of V _C14 from intersecting the voltage of V _C18 too late, and affect the dynamic measurement range of the capacitor 30 to be tested. In addition, the second output capacitor 18 can also be obtained by the above method. know. Meanwhile, please refer to the tenth D picture, the on/off sequence between the first switch 120 and the sixth switch 62 is substantially the same as that of the tenth B picture, except that the first output switch 16 and the second output are only the first output switch 16 and the second output. While the switch 19 is turned on, the first switch 120 and the sixth switch 62 are also turned on. The rest are the same as the tenth B picture, so they are not mentioned here.

Please refer to FIG. 11 , which is a circuit diagram of a filter according to another preferred embodiment of the present invention. As shown in the figure, this embodiment differs from the embodiment of the ninth embodiment in that an amplifier 50 is added to the present embodiment. The amplifier 50 has a first input end, a second input end, a first output end and a second output end. The first input end and the second input end are coupled to the switch module 12, the first output end and the first output end The second output terminal is coupled between the first input end and the first output end of the amplifier 50, and the second output capacitor 18 is coupled to the first output end of the amplifier 50. Between the two input terminals and the second output terminal, one end of the first output switch 16 is coupled to the switch module 12 and the amplifier 50, and the other end of the first output switch 16 is coupled to the third reference signal V _REF3 , and the second output switch 19 . The other end of the second output switch 19 is coupled to the fourth reference signal V _REF4 . Thus, since the present invention increases the amplifier 50 to increase the voltage gain to increase the amplification of the first filtered signal and the second filtered signal, the first output capacitor 14 and the second output capacitor 18 of a smaller capacitance value can be used, thereby achieving cost savings. the goal of. The rest of the structure is the same as the ninth figure, so it will not be mentioned here.

In summary, the capacitive sensing circuit with impedance electromagnetic interference capability of the present invention is coupled to a capacitor to be tested by a filter, and receives a plurality of reference signals to generate a first filtered signal and a second filtered signal. And receiving, by a differential circuit, the first filtered signal and the second filtered signal, and canceling the common mode noise of the second filtered signal of the first filtered signal to generate a differential signal, wherein the magnitude of the differential signal is related to the size of the capacitor to be tested, and The purpose of detecting the capacitance to be tested is achieved. The common mode noise is eliminated by the differential circuit to achieve the capability of resisting electromagnetic interference, and the differential circuit can adjust the output of the filter in a dynamic range, so that the capacitance sensing circuit has the characteristics of low time-consuming pulse period.

The invention is a novelty, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China, and the invention patent application is filed according to law, and the prayer bureau will grant the patent as soon as possible. prayer.

However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the shapes, structures, features, and spirits described in the claims are equivalently changed. Modifications are intended to be included in the scope of the patent application of the present invention.

10‧‧‧ filter

20‧‧‧Differential circuit

30‧‧‧Measured capacitance

40‧‧‧Amplifier

Claims (17)

A capacitive sensing circuit with electromagnetic interference resistance, comprising: a filter coupled to a capacitor to be tested, and receiving a plurality of reference signals to generate a first filtered signal and a second filtered signal, the filter comprising: a switch module coupled to the capacitor to be tested and receiving the reference signals; a first output capacitor coupled to the first output of the switch module; a first output switch coupled to the first output Between the capacitor and the reference signal, the first filter signal is generated; a second output capacitor is coupled to the second output end of the switch module; and a second output switch coupled to the second output capacitor Between the reference signals, the second filtered signal is generated; and a differential circuit receives the first filtered signal and the second filtered signal, and cancels the common mode noise of the first filtered signal and the second filtered signal And generating a differential signal, the magnitude of the differential signal being related to the size of the capacitor to be tested; wherein the capacitor to be tested further comprises a parasitic capacitor coupled to one end of the capacitor to be tested and the switch module. The capacitive sensing circuit with electromagnetic interference resistance according to claim 1, further comprising: an amplifier that receives and amplifies the differential signal. The capacitive sensing circuit with anti-electromagnetic interference capability as described in claim 2, wherein the amplifier is a Variable Gain Amplifier (VGA). The capacitive sensing circuit of the electromagnetic interference-resistant capability of claim 1, wherein the switch module comprises: a first switch, one end of which is coupled to the reference signal, and the other end of the first switch is coupled a second switch, one end of which is coupled to the capacitor to be tested and the first switch, the other end of the second switch is coupled to the first output capacitor; and a third switch is coupled to the reference at one end a signal, the other end of the third switch is coupled to the capacitor to be tested; and a fourth switch, one end of which is coupled to the capacitor to be tested and the third switch, and the other end of the fourth switch is coupled to the second output capacitor . The capacitive sensing circuit with electromagnetic interference resistance according to claim 1, wherein the first output capacitor and the second output capacitor are an integrating capacitor. The capacitive sensing circuit with electromagnetic interference resistance according to claim 1, wherein the differential circuit is a differential amplifier. The capacitive sensing circuit with anti-electromagnetic interference capability as described in claim 1 is applied to fingerprint recognition, acceleration sensors and touch panels. The capacitor sensing circuit of claim 1, wherein the filter further comprises: a fifth switch, one end of which is coupled to the reference signal, and the other end of the fifth switch is coupled The parasitic capacitance is coupled to the fifth switch and the parasitic capacitor, and the other end of the sixth switch is coupled to the reference signal. A capacitive sensing circuit with electromagnetic interference resistance, comprising: a filter coupled to a capacitor to be tested, and receiving a plurality of reference signals to generate a first filtered signal and a second filtered signal, the filter comprising: a switch module coupled to the capacitor to be tested and receiving the reference signals; an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first The first output end and the second output end are configured to output the first filtered signal and the second filtered signal; a first output capacitor coupled Connected between the first input end of the amplifier and the first output end; a second output capacitor coupled between the second input end of the amplifier and the second output end; a first output switch One end of the switch module is coupled to the amplifier, the other end of the first output switch is coupled to the reference signal, and a second output switch is coupled to the switch module and the amplifier at one end, and the second output switch The other end is coupled to the reference signal; and a differential circuit receives the first filtered signal and the second filtered signal, and cancels the common mode noise of the first filtered signal and the second filtered signal to generate a differential signal. The size of the differential signal is related to The magnitude of the capacitance to be measured; wherein the measured capacitor further comprises a parasitic capacitance, the parasitic capacitance coupled to the capacitance measured with an end of the switch module. The capacitive sensing circuit of the anti-electromagnetic interference capability of claim 9, wherein the switch module comprises: a first switch, one end of which is coupled to the reference signal, and the other end of the first switch is coupled a second switch having one end coupled to the capacitor to be tested and the first switch, the other end of the second switch coupled to the first output capacitor and the amplifier; and a third switch coupled at one end Connected to the reference signal, the other end of the third switch is coupled And a fourth switch, one end of which is coupled to the capacitor to be tested and the third switch, and the other end of the fourth switch is coupled to the second output capacitor and the amplifier. The capacitive sensing circuit with electromagnetic interference resistance according to claim 9 is an operational amplifier (OPA). The capacitive sensing circuit with anti-electromagnetic interference capability according to claim 9 , wherein the first output capacitor and the second output capacitor are an integral capacitor. The capacitive sensing circuit with electromagnetic interference resistance according to claim 9 further includes: an amplifier that receives and amplifies the differential signal. The capacitive sensing circuit with electromagnetic interference resistance according to claim 13 is the variable gain amplifier (VGA). The capacitive sensing circuit with electromagnetic interference resistance according to claim 9 is wherein the differential circuit is a differential amplifier. The capacitive sensing circuit with anti-electromagnetic interference capability as described in claim 9 of the patent application is applied to a fingerprint identification, an acceleration sensor and a touch panel. The capacitor sensing circuit of the anti-electromagnetic interference capability of claim 9, wherein the filter further comprises: a fifth switch, one end of which is coupled to the reference signal, and the other end of the fifth switch is coupled The parasitic capacitance is coupled to the fifth switch and the parasitic capacitor, and the other end of the sixth switch is coupled to the reference signal.