201114179 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係有關於一種電容感應電路，其係尤指一種 具抗電磁干擾能力之電容感測電路。 【先前技術·】 [0002] 按，由於現今電腦科技的發展對於電容感應偵測的 應用日驅廣泛，例如指紋辨識、微機電加速感測器以及 電容式觸控面板，而在傳統電容感應偵測技術上普遍使 用電容對頻率轉換的電路，請一併參閱第一圖，係為習 * 知技術之電容感測裝置之方塊圖。如圖所示，此習知技 ' 術係透過一第一比較器100’ 、一第二比較器102’ 、一 控制電路104’以及一電阻106’形成一振盪電路，該振 盪電路耦接一待測電容108’ ，並利用該待測電容108’ 的電容值大小差異而產生不同的振盪頻率，且依據不同 之振盪頻率而得知該待測電容108’的電容值大小，以達 到電容偵測的目的。 再者，請一併參閱第二圖，係為習知技術之另一電 ❹ 容感測裝置之方塊圖。如圖所示，此習知技術係透過一 定電流源200’ 、一第一控制開關201’ 、一第二控制開 關202’ 、一積分電容203’以及一比較器204’ 以形成 一固定斜率產生電路，該固定斜率產生電路耦接一待測 電容205’ ，並利用待測電容205’的電容值的不同而起 始電壓不同，使比較器204’的致能時間不同，以達到電 容偵測的目的。 另，請一併參閱第三圖，係為習知技術之另一電容 感測裝置之方塊圖。如圖所示，此習知技術係透過複數 099134517 表單編號 A0101 第 3 頁/共 28 頁 0992060262-0 201114179 、态、一頻率相位偵測器301，、一控制單元 302’、與_可控制緩衝器咖，形成—生成時間對數位 轉換器。該生成時間對數位轉換器輕接—待測電容綱， ’並生成時間對數位轉換器係利用待測電容3〇4，之電容 值大小的不同而導致控制單元3G2,冑出之控制訊號的時 間差異’以達到電容偵測之目的。 惟查，上述第一圖至第三圖之技術並無對電磁干擾 有免疫能力，尤其是電容感測器之應用普遍需結合微處 理器等周邊電路進行運用，當電磁雜訊從電容耦合至比 較器’振盪頻率將电赛失真，抑或是導致起始電壓失準 . ........ .... ’以致對電容之偵測產生錯誤，上述電路並對電容的偵 測較耗費時脈週期等缺點。# 因此，如何針對上述問題而提出一種新穎具抗電磁 干擾能力之電容感應電路，其可避免因電磁雜訊而影響 電容感應電路的效能’使可解決上述之問題。 【發明内容】 [0003] 099134517 ： . _ . . .·：. 本發明之目的之一，在於提供一種具抗電磁干擾能 力之電容感測電路，其藉由一差分電路消除共模雜訊， 以達到抗電磁干擾的能力。 本發明之目的之一，在於提供一種具抗電磁干擾能 力之電容感測電路，其藉由動態範圍調整一濾波器的輸 出，使電容感測電路具低耗費時脈週期數的特性。 本發明之目的之一，在於提供一種具抗電磁干擾能力之 電容感測電路，其藉由一第五開關與一第六開關而消除 待測電容之寄生電容的影響，進而增加電容感測電路之 待測電容的動態量測範圍。 表單編號Α0101 第4頁/共28頁 〇995 201114179 ，發日狀具抗電針擾能力之電容感測電路包含— w °°與一差分電路。濾波器耦接一待測電容，並接收 複^參考訊鼓產n纽訊號與—第二渡波訊號 消Li差分電路接收第—紐訊號與第二濾波訊號，並 ^ *第〜濾波訊號第二濾波訊號之共模雜訊而產生—差 刀訊鱿，差分訊號之大小相關於待測電容 到待、八’』、，而達 ，以^電容偵測的目的。並藉由差分電路消除共模雜訊 整:達到抗電磁干擾的能力，且差分電路可動態範圍調 Ο [0004] Ο 099134517 厂波器的輸出，使電容感測電路具低耗費時脈週期數 的特性。 【實施方式】 ：f| » Ί f !§$ 1¾ 靡 兹為使貴審查委員對皋發明各結構特徵及所達成之 功效有更進—步之瞭解與認識，謹佐以較佳之實施例及 配合詳細之說明，說明如後： 請參閱第四圖，係為本發明之一較佳實施例之電容感 測電路的方塊圖。如圖所示，本發明之具抗電磁干擾能 力之電容感測電路係可應用於指紋辨識、加速感測器與 觸控面板等。該電容感測電路包含一濾波器10與一差分 電路20。濾波器1〇耦接一待測電容30，並濾波器10接收 複數參考訊號而產生一第一濾波訊號與一第二濾波訊號 ，即濾波器1〇接收一第一參考訊號vREF1、一第二參考訊 號VREF2、一第三參考訊號\^3與一第四參考訊號VREF4 ，而產生第一濾波訊號與第二濾波訊號，其中，本發明 之滤波器10的一較佳實施例為一有限脈衝響應滤波器 (Finite Impulse Response ， FIR)。 並 0992060262-0 差分電路20係接收第一濾波訊號與第二濾波訊號 表單編號A0101 第5頁/共28頁 201114179 差分電路20可消除第一濾波訊號第二濾波訊號之共模雜 訊而產生一差分訊號，其中，差分訊號之大小相關於待 測電容30之大小，即差分電路20可運算出第一濾波訊號 與第二濾波訊號的差值，而產生差分訊號，由於差分訊 號相關於待測電容30，也就是待測電容30之電容值大小 將會影響第一濾波訊號與第二濾波訊號的大小，而使差 分電路20所產生之差分訊號的大小依據待測電容30之電 容值大小而不同，所以，後續電路（圖中未示）可依據差 分訊號而得知待測電容30之電容值。由於本發明係利用 差分電路20相減第一濾波訊號與第二濾波訊號而得知差 分訊號，所以，當有一電磁干擾雜訊產生於第一濾波訊 號與第二濾波訊號時，差分電路20即可在相減第一濾波 訊號與第二濾波訊號的同時，消除‘電磁干擾雜訊，也就 是消除共模雜訊，以達到抗電磁干擾的能力。其中，本 發明之差分電路20之一較佳實施例為一差分放大器。 此外，本發明之具抗電磁干擾能例之電容感測電路更 包含一放大器40。放大器40係耦接於差分電路20，並放 大器40係接收並放大差分訊號，本發明係藉由差分電路 20與放大器40而形成一動態範圍調整電路，此動態範圍 調整電路可有效降低偵測待測電容30的偵測時脈週期， 進而減少功率的消耗，以達到省電的目的。其中，放大 器40為一可調式增益放大器（Variable Gain Amplifier ， VGA) 。 請一併參閱第五圖，係為係為第四圖之一較佳實施例 之渡波器的電路圖。如圖所示，本發明之具抗電磁干擾 能力之電容感測電路的濾波器10包含一開關模組12、一 099134517 表單編號A0101 第6頁/共28頁 0992060262-0 201114179201114179 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a capacitive sensing circuit, and more particularly to a capacitive sensing circuit having electromagnetic interference resistance. [Previous Technology·] [0002] Press, due to the development of computer technology today, there are a wide range of applications for capacitive sensing, such as fingerprint identification, MEMS accelerometers and capacitive touch panels, while traditional capacitive sensing Capacitance-to-frequency conversion circuits are commonly used in measurement technology. Please refer to the first figure for a block diagram of a capacitive sensing device. As shown in the figure, the oscillating circuit is coupled to a first comparator 100', a second comparator 102', a control circuit 104', and a resistor 106'. Capacitor 108' to be tested, and different oscillation frequency is generated by using the difference in capacitance value of the capacitor 108' to be tested, and the capacitance value of the capacitor 108 to be tested is known according to different oscillation frequencies to achieve capacitance detection. The purpose of the test. Furthermore, please refer to the second figure, which is a block diagram of another electrical sensing device of the prior art. As shown, the prior art generates a fixed slope by a certain current source 200', a first control switch 201', a second control switch 202', an integrating capacitor 203', and a comparator 204'. The circuit, the fixed slope generating circuit is coupled to a capacitor 205' to be tested, and uses different capacitance values of the capacitor 205' to be tested, and the starting voltage is different, so that the enabling time of the comparator 204' is different to achieve capacitance detection. the goal of. In addition, please refer to the third figure, which is a block diagram of another capacitive sensing device of the prior art. As shown, the prior art is through a plurality of 099134517 Form No. A0101, Page 3 of 28 0992060262-0 201114179, State, a Frequency Phase Detector 301, a Control Unit 302', and _ Controllable Buffer The coffee maker, formed - generates a time-to-digital converter. The generation time is lightly connected to the digital converter - the capacitance to be tested, and the time-to-digital converter is generated by using the capacitance to be tested 3〇4, and the magnitude of the capacitance value causes the control unit 3G2 to output the control signal. Time difference 'to achieve the purpose of capacitance detection. However, the techniques in the above first to third figures are not immune to electromagnetic interference. In particular, the application of capacitive sensors generally needs to be combined with peripheral circuits such as microprocessors. When electromagnetic noise is capacitively coupled to Comparator 'oscillation frequency will distort the game, or cause the starting voltage to be out of alignment. . . . . . . . . . so that the detection of the capacitor produces an error, the above circuit and the detection of the capacitance Consequences such as the clock cycle. # Therefore, how to solve the above problems and propose a novel capacitive sensing circuit with anti-electromagnetic interference capability, which can avoid the influence of electromagnetic noise on the performance of the capacitive sensing circuit, so that the above problems can be solved. SUMMARY OF THE INVENTION [0003] 099134517: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . To achieve the ability to resist electromagnetic interference. SUMMARY OF THE INVENTION One object of the present invention is to provide a capacitive sensing circuit having immunity to electromagnetic interference, which adjusts the output of a filter by dynamic range, so that the capacitive sensing circuit has the characteristics of low time-consuming pulse period. One of the objectives of the present invention is to provide a capacitive sensing circuit with electromagnetic interference resistance, which eliminates the influence of the parasitic capacitance of the capacitor to be tested by a fifth switch and a sixth switch, thereby increasing the capacitance sensing circuit. The dynamic measurement range of the capacitor to be tested. Form No. Α0101 Page 4 of 28 〇995 201114179, the capacitive sensing circuit with anti-electro-acoustic capability includes - w ° ° and a differential circuit. The filter is coupled to a capacitor to be tested, and receives the second reference signal and the second wave signal eliminating Li circuit to receive the first signal and the second filter signal, and the second filter signal The common mode noise of the filtered signal is generated by the difference knife. The size of the differential signal is related to the capacitance to be measured, to the eight', and to the purpose of the capacitance detection. And the common mode noise is eliminated by the differential circuit: the ability to resist electromagnetic interference is achieved, and the differential circuit can be adjusted in dynamic range [0004] Ο 099134517 The output of the factory wave device makes the capacitance sensing circuit have a low time-consuming pulse period Characteristics. [Embodiment] :f| » Ί f !§$13⁄4 靡 为 为 为 为 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 With reference to the detailed description, the description will be as follows: Please refer to the fourth figure, which is a block diagram of a capacitance sensing circuit according to a preferred embodiment of the present invention. As shown in the figure, the capacitive sensing circuit with electromagnetic interference resistance of the present invention can be applied to fingerprint recognition, acceleration sensors and touch panels. The capacitive sensing circuit includes a filter 10 and a differential circuit 20. The filter 1 is coupled to a capacitor 30 to be tested, and the filter 10 receives the complex reference signal to generate a first filtered signal and a second filtered signal, that is, the filter 1 receives a first reference signal vREF1, a second The first filter signal and the second filter signal are generated by the reference signal VREF2, a third reference signal \^3 and a fourth reference signal VREF4, wherein a preferred embodiment of the filter 10 of the present invention is a finite pulse. Response Filter (Finite Impulse Response, FIR). And 0992060262-0 differential circuit 20 receives the first filtered signal and the second filtered signal form number A0101 page 5 / 28 pages 201114179 differential circuit 20 can eliminate the common mode noise of the first filtered signal second filtered signal to generate a The difference signal, wherein the magnitude of the differential signal is related to the size of the capacitor 30 to be tested, that is, the difference circuit 20 can calculate the difference between the first filtered signal and the second filtered signal to generate a differential signal, since the differential signal is related to the test The capacitance 30, that is, the capacitance value of the capacitor 30 to be tested, affects the size of the first filtered signal and the second filtered signal, and the magnitude of the differential signal generated by the differential circuit 20 depends on the capacitance of the capacitor 30 to be tested. Different, so the subsequent circuit (not shown) can know the capacitance value of the capacitor 30 to be tested according to the differential signal. Since the differential circuit 20 subtracts the first filtered signal and the second filtered signal to obtain the differential signal, when the electromagnetic interference noise is generated by the first filtered signal and the second filtered signal, the differential circuit 20 is The EMI interference noise, that is, the elimination of common mode noise, can be eliminated while the first filtered signal and the second filtered signal are subtracted, so as to achieve the capability of resisting electromagnetic interference. Among them, a preferred embodiment of the differential circuit 20 of the present invention is a differential amplifier. Further, the capacitance sensing circuit of the present invention having an anti-electromagnetic interference performance further includes an amplifier 40. The amplifier 40 is coupled to the differential circuit 20, and the amplifier 40 receives and amplifies the differential signal. The present invention forms a dynamic range adjustment circuit by the differential circuit 20 and the amplifier 40. The dynamic range adjustment circuit can effectively reduce the detection. The detection of the clock cycle of the capacitor 30, thereby reducing power consumption, to achieve power saving purposes. The amplifier 40 is a Variable Gain Amplifier (VGA). Please refer to the fifth figure together, which is a circuit diagram of the ferrophone which is a preferred embodiment of the fourth figure. As shown in the figure, the filter 10 of the capacitive sensing circuit with electromagnetic interference resistance of the present invention comprises a switch module 12, a 099134517, form number A0101, page 6 of 28, 0992060262-0 201114179
099134517 第—輸出電容14、一第一輸出開關16、一第二輸出電容 18與一第二輸出開關1 9。開關模組1 2係耦接待測電容3〇 ，並接收該些參考訊號，即開關模組12接收第一參考訊 號VREFi與第二參考訊號、胛2，第一輸出電容14耦接開關 模組12之一第一輸出端，第一輸出開關16耦接第一輸出 電谷14與參考訊號之間，而產生第一濾波訊號，即第_ 輪出間關16係第一輸出電容14與第三參考訊號v 之間 而輸出第一濾波訊號，第二輸出電容18耦接開關模組12 之第二輸出端，第二輸出開關19係耦接第二輸出電容18 與參考訊號之間’而產生第二濾波訊號，即第二輸出開 關19係耦接第二輸出電容18與第四參考訊號〜評彳之間而 輸出第二濾波訊號。 此外，開關模組12包含一第一開關120、一第二開關 U2、一第三開關124與一第四開關126。第一開關12〇之 —端耦接第一參考訊號VREF1，第一開關120之另一端耦 接待測電容30，第二開關122之一端耦接待測電容3〇與第 開關120，第一開關122之另〜端搞接第一輸出電容μ ，第二開關124之一端搞接第二參考訊號，第三開 關124之另一端耦接待測電容3〇，第四開關126之一端耦 接待測電容30與第三開關124，第四開關126之另一端耦 接第二輸出電容18。如此，本發明係藉由控制開開模組 U、第一輸出開關16第二輸出開關19的導通/截止的順序 ’而產生第一濾波訊號與第二濾波訊號。 請一併參閱第六圖與第七A圖，係為本發明之一較佳 實施例之電容感測電路之輸出波形圖與開關控制的時序 圖。如圖所示，本發明之電容感測電路係先導通與戴止 表單編號A0101 第7頁/共28頁 0992060262-0 201114179 第，輸出㈣16與第：輸出開關19之後’依序導通與載 止第開關120、第二開關122、第三開關1 24與第四開 關126 @使在第一輸出電容14產生第一遽波訊號' 的電 壓斜率變化’並且第—輸出電容14_第三參考訊丄 VREF3 ’所以，使第一濾波訊號v】以第三參考訊號v為 , REF 3 。電壓而電壓訊號之斜率變化；同理，在第二輸出 電容18產生第二濾波訊號、的電壓斜率變化，即第二輸 出電容18輕接第四參考訊號¥刪，所以，使第二滤波訊 號％以第四參考訊號vREF4a-起始電壓而電壓訊號之斜 率變化，由於第一濾波訊號、的電壓斜率輿第二濾波訊 號丫2的電壓斜率為相反，因此，差分電路2〇可藉由第一 ；ii-? 、 濾波訊號v丨與第二濾波訊號.¥ 2的差異值而產生差分訊號 。其中’第一輸出電容14與第二輸出電容1.8為一積分電 容。 請復參閱第五圖與第七A圖，若有一電磁干擾訊號由 待測電容30進入，將切換開關頻率比電磁干擾訊號頻率 尚’由第一開關120導通後’將電磁干擾訊號儲存於待測 電容30，於第二開關122導通之後，第一輸出電容丨4之端 點會得到第一開關120及第二開關122之電磁干擾訊號差 異值，因切換開關頻率比電磁干擾訊號頻率高，所以該 差異值幾乎等於該電磁干擾訊號之斜率；再者，由第三 開關124導通後，將電磁干擾訊號儲存於待測電容30，於 第四開關126導通之後，第二輸出電容18之端點會得到第 三開關124及第四開關126之電磁干擾訊號差異值，因為 切換開關頻率比電磁干擾訊號頻率高’所該差異值幾乎 等於該電磁干擾訊號之斜率’透過差分電路20可將兩訊 099134517 表單編號A0101 0992060262-0 第8頁/共28頁 201114179 號之共模電磁干擾訊號之斜率消除。 此外，請一併參閱第七Β圖，係為係為本發明之另一 較佳實施例之開關控制的時序圖。如圖所示，本實施例 與第七Α圖之實施例不同之處，在於本實施例之開關控制 的順序係第一輸出開關14、第二輸出開關19與第一開關 120同時導通/截止之後，再依序導通/截止第二開關122 、第三開關124與第四開關126，如此，本實施例之濾波 器亦可產生如第六圖之波形。 Ο099134517 The first output capacitor 14, a first output switch 16, a second output capacitor 18 and a second output switch 19. The switch module 12 is coupled to the receiving capacitor 3〇 and receives the reference signals, that is, the switch module 12 receives the first reference signal VREFi and the second reference signal, 胛2, and the first output capacitor 14 is coupled to the switch module. a first output end of the first output switch 16 is coupled between the first output voltage valley 14 and the reference signal to generate a first filtered signal, that is, the first _ round out and the off 16 series first output capacitor 14 and the first The first output signal is output between the three reference signals v, the second output capacitor 18 is coupled to the second output end of the switch module 12, and the second output switch 19 is coupled between the second output capacitor 18 and the reference signal. The second filter signal is generated, that is, the second output switch 19 is coupled between the second output capacitor 18 and the fourth reference signal to the evaluation signal to output the second filtered signal. In addition, the switch module 12 includes a first switch 120, a second switch U2, a third switch 124, and a fourth switch 126. The first switch 12 is coupled to the first reference signal VREF1, and the other end of the first switch 120 is coupled to the receiving capacitor 30. One end of the second switch 122 is coupled to the receiving capacitor 3〇 and the switch 120. The first switch 122 The other end of the second switch 124 is connected to the second reference signal, the other end of the third switch 124 is coupled to the receiving capacitor 3〇, and the other end of the fourth switch 126 is coupled to the receiving capacitor 30. The second output capacitor 18 is coupled to the third switch 124 and the other end of the fourth switch 126. Thus, the present invention generates the first filtered signal and the second filtered signal by controlling the opening/closing sequence of the open module U and the second output switch 19 of the first output switch 16. Please refer to FIG. 6 and FIG. 7A together, which are timing diagrams of the output waveform diagram and the switch control of the capacitance sensing circuit according to a preferred embodiment of the present invention. As shown in the figure, the capacitive sensing circuit of the present invention is first turned on and the stop form number A0101 page 7 / 28 pages 0992060262-0 201114179 first, output (four) 16 and the: output switch 19 'sequential conduction and load The first switch 120, the second switch 122, the third switch 1 24 and the fourth switch 126 @ cause the voltage slope change of the first chopping signal 'at the first output capacitor 14' and the first output capacitor 14_third reference signal丄VREF3 ' So, the first filtered signal v is made with the third reference signal v, REF 3 . The slope of the voltage and the voltage signal changes. Similarly, the second output capacitor 18 generates a second filtered signal, and the voltage slope changes, that is, the second output capacitor 18 is connected to the fourth reference signal, and thus the second filtered signal is used. % is the fourth reference signal vREF4a-the starting voltage and the slope of the voltage signal changes. Since the slope of the voltage of the first filtered signal, the slope of the voltage 舆, and the second filtered signal 丫2 are opposite, the differential circuit 2 can be A differential signal is generated by the difference value of the ii-?, the filtered signal v丨 and the second filtered signal. Wherein the first output capacitor 14 and the second output capacitor 1.8 are an integral capacitor. Please refer to the fifth picture and the seventh picture A. If an electromagnetic interference signal enters the capacitor 30 to be tested, the switching frequency will be switched to the electromagnetic interference signal frequency, and the electromagnetic interference signal will be stored after the first switch 120 is turned on. After the second switch 122 is turned on, the end of the first output capacitor 丨4 will obtain the difference of the electromagnetic interference signals of the first switch 120 and the second switch 122, because the switching frequency is higher than the electromagnetic interference signal frequency. Therefore, the difference value is almost equal to the slope of the electromagnetic interference signal; further, after the third switch 124 is turned on, the electromagnetic interference signal is stored in the capacitor 30 to be tested, and after the fourth switch 126 is turned on, the end of the second output capacitor 18 The point will obtain the electromagnetic interference signal difference value of the third switch 124 and the fourth switch 126, because the switching switch frequency is higher than the electromagnetic interference signal frequency, and the difference value is almost equal to the slope of the electromagnetic interference signal. 099134517 Form No. A0101 0992060262-0 Page 8 of 28 The total slope of the common mode electromagnetic interference signal of 201114179 is eliminated. Further, please refer to the seventh diagram, which is a timing chart of the switch control of another preferred embodiment of the present invention. As shown in the figure, the difference between the embodiment and the embodiment of the seventh embodiment is that the sequence of the switch control in the embodiment is that the first output switch 14, the second output switch 19 and the first switch 120 are simultaneously turned on/off. Then, the second switch 122, the third switch 124 and the fourth switch 126 are sequentially turned on/off. Thus, the filter of the embodiment can also generate a waveform as shown in FIG. Ο
請參閱第八圖，係為本發明之.另一較佳實施例之慮波 器的電路圖。如圖所示，本實施例與第五圖之實施例不 同之處，在於本實施例增加一放大器5〇。放大器50具有 —第一輸入端、一第二輸入端、一第一輸出端與一第二 輸出端，第一輸入端與第一輪入端係搞接開.關模組12， 第一輸出端與第二輸出端係用以輪出第一濾波訊號與第 二濾波訊號，第一輸出電容14耦接放大器5〇之第一輸入 %與第一輸出端之間’第一輪出電容1 8輪接放大器50之 第二輸入端與第二輸出端之間，‘第一輸出開關16之一端 耗接開關模組12與放大器5 0'，第一輸出開關丨6之另一端 耗接第三參考訊號VREF3，第二輸出開關19之-端耦接開 關模組12與放大器50，第二輪出開關19之另一端耦接第 四參考訊號VREF4如此，由於本發明增加放大器以增 加電壓增H ’以增加放大第—濾波訊號與第二攄波訊號 而可使用較小電容值的第—輪出電容14與第二輸以 容18 ’進而達到省成本的目的 50—較佳實施例為—運算放大 f ier，OPA) ° 。其中’本發明之放大器 器（Operational Ampli 099134517 表單編號A0101 第9頁/共28頁 0992060262-0 201114179 此外，請參閱第九圖，係為本發明之另一較佳實施例 之攄波器的電路圖。如圖所示，由於本發明之待測電容 30會產生一寄生電容32，寄生電容32係耦接待測電容3〇 之一端，並耦接開關模組12。因為寄生電容32的關係， 會使本發明之電容感測電路在量測待測電容3〇的動態範 圍會過小，所以，本發明在本實施例之電容感測電路的 濾波器1 0中更包含了一第五開關6 〇與一第六開關6 2。第 五開關60之一端係耦接參考訊號（即第三參考訊號v ) REF 3 ，第五開關60之另一端則耦接f生電容32。第六開關62 之一端係耗接第五開關6 〇與聲羞電容3 2，第六開關6 2之 另一端耦接參考訊號（即第四參考訊號v )。如此，本 REF4 實施例係配合開關模組丨2之第一開關^ 2 〇至第四開關丨2 6 的導通次序，以達到增加待測電容3 〇之琴態量測範圍。 以下係會針對第五開關6〇與第六開關μ如何配合開關模 組12之第一開關120至第四開關的導通次序進行運作 而進行說明。 請一併參閱第十A圖，係爲^#萌^一較佳實施例之 第九圖的時序圖。如圖所示，當第一輸出開關丨6與第二 輸出開關19導通時，第五開關60亦導通，第一開關12〇在 第一輸出開關16與第二輸出開關19導通之後接著導通， 第五開關6 0在第一開關12 〇截止的同時亦截止，此時，第 二開關122與第六開關62則導通，之後第三開關124導通 ，第三開關124截止時，第六開關62亦截止，之後第四開 關126與第五開關60導通，如此重複上述複數開關導通/ 載止次序，即可使寄生電容32之電容值相對於待測電容 3 0之電容值之影響降低，而達到增加待測電容3 〇之動態 099134517 表單編號A0101 第10頁/共28頁 0992060262-0 201114179 里測範圍。其中，由上述之該些開關的次序可知，第— 輪出電容14的電壓為： r(、》]*聊…(1) 若η趨近於無限大時， 1=表*咖...（2) 即由上述可知，當待測電容30之電容值遠大於寄生電 容32之電容值，而使寄生電容32可以忽略，而達到增加 待測電容30之動態量測範圍，即本實施例可避免ν的 OC14 電壓與Vci8的電壓太早交集，而影響待測電容30之動態 量測範圍，此外，第二輸出電容18亦可由上述的方式得 知。同時，請一併參閱第十c圖，其第U：開涵120至第六 開關62間的導通/截止次序與第十A圖大舞上相同，不同 之處僅在於第一輸出開關16與第二輸出開關19導通的同 時，第一開關120與第五開關60亦導通《其餘皆與第十a 圖相同，故在此不再加以贊.述。.： 請一併參閱第十B圖’係為丰發—明弋另一較佳實施例 〇 之第九圖的時序圊。如圖所示，本實施例與第十A圖之實 施例不同之處’在於第一輸出開關16與第二輸出開關19 導通時’第六開關6 2亦導通，第一開關12 〇在第一輸出開 關16與第二輸出開關19導通之後接著導通，第六開關62 在第一開關12 0截止的同時亦截止，此時，第二開關12 2 與第五開關60則導通’之後第三開關124導通，第三開關 124截止時，第五開關60亦截止，之後第四開關126與第 六開關62導通’如此重複上述複數開關導通/截止次序， 即可使寄生電容32之電容值相對於待測電容3〇之電容值 099134517 表單編號A0101 第Π頁/共28頁 0992060262-0 201114179 之衫響增加，而透過寄生電容3 2的的電容值，以得知待 測電容30的電容值，如此亦可達到增加待測電容⑽之動 態量測範圍。其中，由上述之該些開關的次序可知，第 一輸出電容14的電壓為： V(u ~ +M)+ +···+…(3) 若η趨近於無限大時， 聊…⑷ 由上述可知，寄生電容32之電容值遠大於待測電容3〇 之電容值，而透過寄生電容32的的電容值，以得知待測 電容30的電容值，如此亦可達到増加待螂電容3〇之動態 量測範圍，即本實施例可避免、14的，壓與的電壓太 晚交集，而影響待測電容30之動態量測範圍，此外，第 一輸出電容18亦可由上述的方式得知。同.時，請一併參 閱第十D圖，其第一開關120至第六開關62間的導通/截止 次序與第十B圖大致上相同⑴不學之赛嗓幸於第一輸出開 關16與第二輸出開關19導通的同時”第;一開關12〇與第六 開關62亦導通。其餘皆與第f f圖相同，故在此不再加以 贊述。 请參閱第十一圖，係為本發明之另一較佳實施例之渡 波器的電路圖。如圖所示，本實施例與第九圖之實施例 不同之處，在於本實施例增加一個放大器5〇。放大器5〇 具有一第一輸入端、一第二輸入端、一第一輸出端與一 第二輸出端，第一輸入端與第二輸入端係耦接開關模組 12，第一輸出端與第二輸出端係用以輸出第一濾波訊號 與第二濾波訊號，第一輸出電容14耦接放大器50之第一 099134517 表單編號A0101 第12頁/共28頁 0992060262-0 201114179 輸入端與第一輸出端之間，第二輸出電容18耦接放大器 50之第二輸入端與第二輸出端之間，第一輸出開關16之 一端耦接開關模組12與放大器50，第一輸出開關16之另 一端耦接第三參考訊號VREF3，第二輸出開關19之一端耦 接開關模組12與放大器50，第二輸出開關19之另一端耦 接第四參考訊號。如此，由於本發明增加放大器50 K L r 4 以增加電壓增益，以增加放大第一濾波訊號與第二濾波 訊號，而可使用較小電容值的第一輸出電容14與第二輸 出電容18,進而達到省成本的目的。其餘結構皆與第九 圖相同，故於此不再加以贊述。 综上所述，本發明之具祖抗電磁干擾能力之電容感測 電路，其由一濾波器耦接一待測電容，並接收複數參考 訊號而產生一第一濾波訊號與一第二濾波訊號，並由一 差分電路接收第一濾波訊號與第二濾波訊號，並消除第 一濾波訊號第二濾波訊號之共模雜訊而產生一差分訊號 ，差分訊號之大小相關於待測電容之大小，而達到待測 電容偵測的目的。並藉由差分電路消除共模雜訊，以達 到抗愈磁干擾的能力，且差分電路可動態範圍調整濾波 器的輸出，使電容感測電路具低耗費時脈週期數的特性 〇 本發明係實為一具有新穎性、進步性及可供產業利用 者，應符合我國專利法所規定之專利申請要件無疑，爰 依法提出發明專利申請，祈鈞局早曰賜准專利，至感 為禱。 惟以上所述者，僅為本發明之一較佳實施例而已，並 非用來限定本發明實施之範圍，舉凡依本發明申請專利 099134517 表單編號A0101 第13頁/共28頁 0992060262-0 201114179 範圍所述之形狀、構造、特徵及精神所為之均等變化與 修飾，均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 [0005] 第一圖係為習知技術之電容感測裝置之方塊圖； 第二圖係為習知技術之另一電容感測裝置之方塊圖； 第三圖係為習知技術之另一電容感測裝置之方塊圖； 第四圖係為本發明之一較佳實施例之電容感測電路的方 塊圖， 第五圖係為第四圖之一較佳實施例之濾波器的電路圖； 第六圖係為本發明之一較佳實施例之電容感測電路之輸 出波形圖； 第七A圖係為本發明之一較佳實施例之開關控制的時序圖 > 第七B圖係為本發明之另一較佳實施例之開關控制的時序 圖， 第八圖係為本發明之另一較佳實施例之濾波器的電路圖 第九圖係為本發明之另一較佳實施例之濾波器的電路圖 f 第十A圖係為本發明之一較佳實施例之第九圖的時序圖； 第十B圖係為本發明之另一較佳實施例之第九圖的時序圖 > 第十C圖係為本發明之另一較佳實施例之第九圖的時序圖 , 第十D圖係為本發明之另一較佳實施例之第九圖的時序圖 ;以及 表單編號A0101 099134517 第14頁/共28頁 0992060262-0 201114179 第十一圖係為本發明之另一較佳實施例之濾波器的電路 圖。 【主要元件符號說明】Please refer to the eighth embodiment, which is a circuit diagram of a wave filter according to another preferred embodiment of the present invention. As shown in the figure, this embodiment differs from the embodiment of the fifth figure in that an amplifier 5 is added to the present embodiment. The amplifier 50 has a first input end, a second input end, a first output end and a second output end, and the first input end is coupled to the first wheel end end. The module 12 is closed. The first output terminal 14 is configured to rotate the first filtered signal and the second filtered signal, and the first output capacitor 14 is coupled between the first input % of the amplifier 5 and the first output end. Between the second input end and the second output end of the 8-wheeled amplifier 50, one end of the first output switch 16 consumes the switch module 12 and the amplifier 50', and the other end of the first output switch 丨6 consumes the first The third reference signal VREF3, the second output switch 19 is coupled to the switch module 12 and the amplifier 50, and the other end of the second output switch 19 is coupled to the fourth reference signal VREF4. Since the present invention increases the amplifier to increase the voltage increase H' can increase the amplification of the -filter signal and the second chopping signal, and can use the smaller capacitance value of the first-out capacitor 14 and the second input capacitor 18' to achieve cost-saving purposes. 50 - The preferred embodiment is - Operational amplification f ier, OPA) ° . The 'amplifier of the present invention (Operational Ampli 099134517 Form No. A0101, page 9 / 28 pages 0992060262-0 201114179 In addition, please refer to the ninth figure, which is a circuit diagram of a chopper according to another preferred embodiment of the present invention. As shown in the figure, since the capacitor 30 to be tested of the present invention generates a parasitic capacitance 32, the parasitic capacitor 32 is coupled to one end of the receiving capacitor 3〇 and coupled to the switch module 12. Because of the parasitic capacitance 32, The dynamic range of the capacitance sensing circuit of the present invention for measuring the capacitance to be measured 3 过 is too small. Therefore, the present invention further includes a fifth switch 6 in the filter 10 of the capacitance sensing circuit of the present embodiment. The sixth switch 60 is coupled to the reference signal (ie, the third reference signal v) REF 3 , and the other end of the fifth switch 60 is coupled to the f-capacitor 32. The sixth switch 62 The other end of the sixth switch 6 2 is coupled to the reference signal (ie, the fourth reference signal v ). Thus, the REF4 embodiment is coupled with the switch module 丨 2 The first switch ^ 2 〇 to the fourth switch 丨 2 6 The turn-on sequence is used to increase the range of the measured state of the capacitance of the capacitor to be tested. The following is how the fifth switch 6〇 and the sixth switch μ cooperate with the first switch 120 to the fourth switch of the switch module 12. The sequence is operated to explain. Please refer to the tenth A diagram, which is a timing diagram of the ninth diagram of a preferred embodiment. As shown, when the first output switch 丨6 and the second When the output switch 19 is turned on, the fifth switch 60 is also turned on, and the first switch 12 is turned on after the first output switch 16 and the second output switch 19 are turned on, and the fifth switch 60 is also turned off at the first switch 12 At this time, the second switch 122 and the sixth switch 62 are turned on, then the third switch 124 is turned on, and when the third switch 124 is turned off, the sixth switch 62 is also turned off, and then the fourth switch 126 and the fifth switch 60 are turned on. By repeating the above-mentioned plurality of switch on/off sequence, the influence of the capacitance value of the parasitic capacitor 32 with respect to the capacitance value of the capacitor to be tested is reduced, and the dynamic of the capacitor to be tested is increased. 099134517 Form No. A0101 No. 10 Page / Total 28 Pages 099206 0262-0 201114179 The range of the measurement. Among them, the order of the above-mentioned switches is that the voltage of the first-out capacitor 14 is: r(, "]* talk... (1) If η approaches infinity, 1=表*咖...(2) It can be seen from the above that when the capacitance value of the capacitor 30 to be tested is much larger than the capacitance value of the parasitic capacitor 32, the parasitic capacitance 32 can be neglected, and the dynamic of the capacitor 30 to be tested is increased. The measurement range, that is, the embodiment can prevent the OC14 voltage of ν from intersecting the voltage of Vci8 too early, and affect the dynamic measurement range of the capacitor 30 to be tested. Further, the second output capacitor 18 can also be known by the above manner. Meanwhile, please refer to the tenth c-figure, the U: opening/closing sequence between the opening culvert 120 and the sixth switch 62 is the same as that of the tenth A-picture, except that the first output switch 16 is While the second output switch 19 is turned on, the first switch 120 and the fifth switch 60 are also turned on. "The rest are the same as the tenth a picture, and therefore will not be praised here. Please refer to Figure 10B for the timing diagram of the ninth diagram of another preferred embodiment of Fengfa-Ming. As shown in the figure, the difference between the embodiment and the embodiment of FIG. A is 'When the first output switch 16 and the second output switch 19 are turned on, the sixth switch 6 2 is also turned on, and the first switch 12 is in the first place. After the output switch 16 and the second output switch 19 are turned on, the sixth switch 62 is also turned off while the first switch 120 is turned off. At this time, the second switch 12 2 and the fifth switch 60 are turned on. When the switch 124 is turned on, when the third switch 124 is turned off, the fifth switch 60 is also turned off, and then the fourth switch 126 and the sixth switch 62 are turned on. [This repetition of the above-mentioned plurality of switch on/off sequences can make the capacitance value of the parasitic capacitor 32 relatively The capacitance value of the capacitor to be tested is 099134517. Form No. A0101, page 28/total 28 page 0992060262-0 201114179 The number of the ring is increased, and the capacitance value of the parasitic capacitor 32 is used to know the capacitance of the capacitor 30 to be tested. This can also increase the dynamic measurement range of the capacitor (10) to be tested. It can be seen from the sequence of the switches mentioned above that the voltage of the first output capacitor 14 is: V(u ~ +M)+ +···+...(3) If η approaches infinity, chat...(4) It can be seen from the above that the capacitance value of the parasitic capacitance 32 is much larger than the capacitance value of the capacitor 3 to be measured, and the capacitance value of the parasitic capacitance 32 is passed to know the capacitance value of the capacitor 30 to be tested, so that the capacitance to be clamped can also be increased. The dynamic measurement range of 3〇, that is, the voltage of the voltage and the voltage of the capacitor 30 to be tested may be avoided, and the first output capacitor 18 may also be in the above manner. Learned. In the same time, please refer to the tenth D diagram, and the on/off sequence between the first switch 120 and the sixth switch 62 is substantially the same as that of the tenth B diagram. (1) The game is not fortunate. While the second output switch 19 is turned on, "the first switch 12" and the sixth switch 62 are also turned on. The rest are the same as the ffth diagram, and therefore will not be further described here. Please refer to the eleventh figure. A circuit diagram of a ferrophone according to another preferred embodiment of the present invention. As shown in the figure, the difference between the embodiment and the embodiment of the ninth embodiment is that an amplifier 5 is added to the embodiment. The amplifier 5 has a first An input terminal, a second input terminal, a first output terminal and a second output terminal, the first input terminal and the second input terminal are coupled to the switch module 12, and the first output terminal and the second output terminal are used To output the first filtered signal and the second filtered signal, the first output capacitor 14 is coupled to the first 099134517 of the amplifier 50. Form No. A0101 Page 12 / Total 28 Page 0992060262-0 201114179 Between the input end and the first output end, The second output capacitor 18 is coupled to the second input end of the amplifier 50 and Between the output terminals, one end of the first output switch 16 is coupled to the switch module 12 and the amplifier 50, the other end of the first output switch 16 is coupled to the third reference signal VREF3, and one end of the second output switch 19 is coupled to the switch module. The fourth reference signal is coupled to the other end of the second output switch 19. The amplifier 50 KL r 4 is added to increase the voltage gain to increase the amplification of the first filtered signal and the second filtered signal. The first output capacitor 14 and the second output capacitor 18 with smaller capacitance values can be used, thereby achieving the purpose of cost saving. The rest of the structure is the same as the ninth figure, so it will not be praised here. The invention discloses a capacitive sensing circuit with anti-electromagnetic interference capability, which is coupled to a capacitor to be tested by a filter, and receives a plurality of reference signals to generate a first filtered signal and a second filtered signal, and is configured by a differential circuit. Receiving the first filtered signal and the second filtered signal, and canceling the common mode noise of the first filtered signal and the second filtered signal to generate a differential signal, the magnitude of the differential signal being related to the large capacitance to be tested The purpose of detecting the capacitance to be tested is achieved, and the common mode noise is eliminated by the differential circuit to achieve the capability of resisting the magnetic interference, and the differential circuit can dynamically adjust the output of the filter to make the capacitance sensing circuit low. Characteristics of the number of time-consuming cycles: The present invention is a novelty, progressive and available for industrial use, and should meet the requirements of patent applications stipulated in the Patent Law of China. It is only a matter of exemplification of the present invention, which is only a preferred embodiment of the present invention, and is not intended to limit the scope of the practice of the present invention. Patent No. 099134517 Form No. A0101 13 Pages / Total 28 pages 0992060262-0 201114179 The equivalent variations and modifications of the shapes, configurations, features and spirits of the scope are intended to be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [0005] The first figure is a block diagram of a conventional capacitive sensing device; the second figure is a block diagram of another capacitive sensing device of the prior art; The block diagram of another capacitive sensing device of the prior art; the fourth figure is a block diagram of a capacitive sensing circuit according to a preferred embodiment of the present invention, and the fifth figure is a preferred embodiment of the fourth figure. The circuit diagram of the filter; the sixth diagram is the output waveform diagram of the capacitance sensing circuit according to a preferred embodiment of the present invention; and the seventh diagram is the timing diagram of the switch control according to a preferred embodiment of the present invention. FIG. 7B is a timing chart of switch control according to another preferred embodiment of the present invention, and FIG. 8 is a circuit diagram of a filter according to another preferred embodiment of the present invention. FIG. Circuit diagram of a preferred embodiment of the filter FIG. 10A is a timing diagram of a ninth diagram of a preferred embodiment of the present invention; FIG. 10B is another preferred embodiment of the present invention. Timing Chart of the Ninth Diagram> The tenth C diagram is the ninth of another preferred embodiment of the present invention. The timing diagram of the figure, the tenth D diagram is the timing diagram of the ninth diagram of another preferred embodiment of the present invention; and the form number A0101 099134517 page 14 / 28 pages 0992060262-0 201114179 The eleventh figure is A circuit diagram of a filter of another preferred embodiment of the present invention. [Main component symbol description]
[0006] 習知技術 100’ 102’ 104’ 106’ 108’ 200’ 201’ 202’ 203’ 204’ 205’ 300’ 301’ 302’ 303’ 304’ 本發明： 10 11 120 122 第一比較器 第二比較器 控制電路 電阻 待測電容 定電流源 第一控制開關 第二控制開關 積分電容 比較器 待測電容 複數緩衝器 頻率相位偵測器 控制單元 可控制緩衝器 待測電容 遽波器 開關模組 第一開關 第二開關 099134517 124 第三開關 表單編號A0101 第15頁/共28頁 0992060262-0 201114179 126 第四開關 14 第一輸出電容 16 第一輸出開關 18 第二輸出電容 19 第二輸出開關 20 差分電路 30 待測電容 32 寄生電容 40 放大器 50 放大器 60 第五開關 62 第六開關 099134517 表單編號A0101 第16頁/共28頁 0992060262-0[0006] The prior art 100' 102' 104' 106' 108' 200' 201 ' 202 ' 203 ' 204 ' 205 ' 300 ' 301 ' 302 ' 303 ' 304 ' the present invention: 10 11 120 122 first comparator Two comparator control circuit resistance to be measured capacitance constant current source first control switch second control switch integral capacitance comparator to be tested capacitance complex buffer frequency phase detector control unit control buffer to be tested capacitor chopper switch module First switch second switch 099134517 124 third switch form number A0101 page 15 / total 28 page 0992060262-0 201114179 126 fourth switch 14 first output capacitor 16 first output switch 18 second output capacitor 19 second output switch 20 Differential Circuit 30 Capacitance to Be Tested 32 Parasitic Capacitance 40 Amplifier 50 Amplifier 60 Fifth Switch 62 Sixth Switch 099134517 Form No. A0101 Page 16 of 28 0992060262-0