TWI482466B - Amplitude shift keying demodulator - Google Patents
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Description
本發明係有關於一種幅移鍵控解調變電路，特別係有關於一種可提供高可靠度解調訊號之幅移鍵控解調變電路。
The invention relates to an amplitude shift keying demodulation circuit, in particular to an amplitude shift keying demodulation circuit capable of providing a high reliability demodulation signal.
習知幅移鍵控解調器200如第3圖所示，係包含一整流器210、一電性連接該整流器210之封包偵測器220、一電性連接該封包偵測器220之電壓放大器230、一電性連接該電壓放大器230微分器240及一電性連接該微分器240之比較器250，其中該整流器210係包含一第一電阻211及一二極体212，該封包偵測器220係具有一第二電阻221及一第一電容222，該電壓放大器230係具有一第二電容231及一放大器232，當一幅移鍵控(Amplitude Shift Keying)訊號輸送至該幅移鍵控解調器200之輸入端時，訊號先經由該整流器210進行訊號整流動作，接著，經過整流之幅移鍵控訊號係藉由該波封偵測器220以移除該幅移鍵控訊號中的載波並形成一波封訊號，該電壓放大器230係放大該波封訊號，該微分器240係能將放大後之波封訊號中的上升波形轉換為正脈衝，下降波形轉換為負脈衝，最後，正脈衝及負脈衝係輸送至該比較器250進行比較，以決定輸出端為邏輯訊號0或邏輯訊號1，由於習知幅移鍵控解調器200之第一電阻211、第二電阻221、第一電容222及第二電容231皆以大電阻及大電容所構成，因此電路之體積及功率消耗極大，本設計難以實現於積體化上，故其應用將大幅受限。
As shown in FIG. 3, the conventional amplitude shift keying demodulator 200 includes a rectifier 210, a packet detector 220 electrically connected to the rectifier 210, and a voltage amplifier electrically connected to the packet detector 220. The voltage amplifier 230 is electrically connected to the voltage divider 230 and the comparator 250 electrically connected to the differentiator 240. The rectifier 210 includes a first resistor 211 and a diode 212. The packet detector The 220 series has a second resistor 221 and a first capacitor 222. The voltage amplifier 230 has a second capacitor 231 and an amplifier 232. When an Amplitude Shift Keying signal is sent to the amplitude shift keying At the input end of the demodulator 200, the signal first performs signal rectification through the rectifier 210, and then the rectified amplitude shift key signal is used by the wave seal detector 220 to remove the amplitude shift key signal. The carrier wave forms a wave seal signal. The voltage amplifier 230 amplifies the wave seal signal. The differentiator 240 converts the rising waveform in the amplified wave seal signal into a positive pulse, and the falling waveform is converted into a negative pulse. Positive pulse and negative pulse system The comparator 250 is sent to the comparator 250 for comparison to determine whether the output is a logic signal 0 or a logic signal 1. The first resistor 211, the second resistor 221, the first capacitor 222, and the first of the conventional amplitude shift keying demodulator 200 Since the two capacitors 231 are composed of a large resistor and a large capacitor, the volume and power consumption of the circuit are extremely large, and the design is difficult to implement in the integrated system, so the application thereof is greatly limited.
本發明之主要目的係在於提供一種幅移鍵控解調變電路，其包含一半波整流器、一封包回復電路及一緩衝器，該半波整流器係具有一訊號輸入端，該封包回復電路係電性連接該半波整流器且具有一電流鏡、一差動放大器、一第一壓差產生電路及一第二壓差產生電路，該差動放大器係具有一第一NMOS電晶體及一電性連接該第一NMOS電晶體之第二NMOS電晶體，該差動放大器係電性連接該電流鏡，該第一壓差產生電路係電性連接該差動放大器之該第一NMOS電晶體之第一閘極端，該第二壓差產生電路係電性連接該差動放大器之該第二NMOS電晶體之第二閘極端，該緩衝器係具有一訊號輸出端且電性連接該封包回復電路之該電流鏡及該差動放大器，本發明係藉由該第一壓差產生電路及該第二壓差產生電路，可使得該第一NMOS電晶體之該第一閘極端及該第二NMOS電晶體之該第二閘極端之間產生明顯的電位差異，當該半波整流器輸出之訊號為高電位，則該第一閘極端之電位高於該第二閘極端之電位，此時該緩衝器之輸出電位為高電位，反之，當該半波整流器輸出之訊號為低電位，則該第一閘極端之輸出電位低於該第二閘極端之電位，此時該緩衝器之輸出電位為低電位，藉由上述的電路設計，能有效獲得一具有高可靠度解調訊號之解調變電路。
The main object of the present invention is to provide an amplitude shift keying demodulation circuit comprising a half wave rectifier, a packet recovery circuit and a buffer, the half wave rectifier having a signal input end, the packet recovery circuit system Electrically connecting the half-wave rectifier and having a current mirror, a differential amplifier, a first differential pressure generating circuit and a second differential pressure generating circuit, the differential amplifier having a first NMOS transistor and an electrical a second NMOS transistor connected to the first NMOS transistor, the differential amplifier is electrically connected to the current mirror, and the first differential pressure generating circuit is electrically connected to the first NMOS transistor of the differential amplifier a second voltage difference generating circuit is electrically connected to the second gate terminal of the second NMOS transistor of the differential amplifier, the buffer has a signal output end and is electrically connected to the packet recovery circuit In the current mirror and the differential amplifier, the first differential voltage generating circuit and the second differential pressure generating circuit of the present invention can make the first gate terminal and the second NMOS electrode of the first NMOS transistor The crystal A significant potential difference is generated between the second gate terminals. When the signal output by the half-wave rectifier is high, the potential of the first gate terminal is higher than the potential of the second gate terminal, and the output potential of the buffer is at this time. Is high, and vice versa, when the signal output by the half-wave rectifier is low, the output potential of the first gate terminal is lower than the potential of the second gate terminal, and the output potential of the buffer is low. According to the above circuit design, a demodulation circuit having a high reliability demodulation signal can be effectively obtained.
請參閱第1圖，其係本發明之一較佳實施例，一種幅移鍵控解調變電路100，係包含一半波整流器110、一封包回復電路120及一緩衝器130，該半波整流器110係具有一訊號輸入端111，其係可接收一幅移鍵控(Amplitude shift keying)訊號，該封包回復電路120係電性連接該半波整流器110且具有一電流鏡121、一電性連接該電流鏡121之差動放大器122、一第一壓差產生電路123及一第二壓差產生電路124，其中該差動放大器122係具有一第一NMOS電晶體1221及一電性連接該第一NMOS電晶體1221之第二NMOS電晶體1222，該第一NMOS電晶體1221係具有一第一閘極端1221a、一第一汲極端1221b及一第一源極端1221c，該第二NMOS電晶體1222係具有一第二閘極端1222a、一第二汲極端1222b及一第二源極端1222c，此外，該電流鏡121係具有一第一PMOS電晶體1211及一第二PMOS電晶體1212，該第一PMOS電晶體1211係具有一第三閘極端1211a、一第三汲極端1211b及一第三源極端1211c，該第二PMOS電晶體1212係具有一第四閘極端1212a、一第四汲極端1212b及一第四源極端1212c，該第一PMOS電晶體1211之該第三汲極端1211b係電性連接該第三閘極端1211a、該第四閘極端1212a及該第一汲極端1221b，該第二PMOS電晶體1212之該第四汲極端1212b係電性連接該第二NMOS電晶體1222之該第二汲極端1222b，該第一壓差產生電路123係電性連接該差動放大器122之該第一NMOS電晶體1221之該第一閘極端1221a，該第二壓差產生電路124係電性連接該差動放大器122之該第二NMOS電晶體1222之第二閘極端1222a，該緩衝器130係具有一訊號輸出端131及一輸入端132，該緩衝器130係電性連接該封包回復電路120之該電流鏡121及該差動放大器122，在本實施例中，該緩衝器130之該輸入端132係電性連接該第二NMOS電晶體1222之該第二汲極端1222b及該第二PMOS電晶體1212之該第四汲極端1212b。
請再參閱第1圖，在本實施例中，該封包回復電路120之該第一壓差電路123係具有一第三NMOS電晶體1231及一第四NMOS電晶體1232，該第三NMOS電晶體1231係具有一第五閘極端1231a、一第五汲極端1231b及一第五源極端1231c，該第四NMOS電晶體1232係具有一第六閘極端1232a、一第六汲極端1232b及一第六源極端1232c，該第五閘極端1231a係電性連接該第六閘極端1232a，該第五源極端1231c係電性連接該第六汲極端1232b及該第一NMOS電晶體1221之該第一閘極端1221a，此外，該第二壓差電路124係具有一第五NMOS電晶體1241及一第三PMOS電晶體1242，該第五NMOS電晶體1241係具有一第七閘極端1241a、一第七汲極端1241b及一第七源極端1241c，該第三PMOS電晶體1242係具有一第八閘極端1242a、一第八汲極端1242b及一第八源極端1242c，其中該第七閘極端1241a係電性連接該第八閘極端1242a，該第七汲極端1241b係電性連接該第八汲極端1242b及該第二NMOS電晶體1222之該第二閘極端1222a。
請再參閱第1圖，該半波整流器110係另具有一第六NMOS電晶體112及一第七NMOS電晶體113，該第六NMOS電晶體112係具有一第九閘極端112a、一第九汲極端112b及一第九源極端112c，該第七NMOS電晶體113係具有一第十閘極端113a、第十汲極端113b及一第十源極端113c，該第九閘極端112a係電性連接該訊號輸入端111及該第九汲極端112b，該第十汲極端113b係電性連接該第十源極端113c，該第九源極端112c係電性連接該第十閘極端113a、該電流鏡121之該第一PMOS電晶體1211、該第二PMOS電晶體1212、該第一壓差產生電路123之該第三NMOS電晶體1231之該第五閘極端1231a、該第四NMOS電晶體1232之該第六閘極端1232a、該第二壓差產生電路124之該第五NMOS電晶體1241之該第七閘極端1241a及該第三PMOS電晶體1242之該第八閘極端1242a，此外，在本實施例中，該幅移鍵控解調變電路100之該封包回復電路120係另具有一第四PMOS電晶體125，該第四PMOS電晶體125係具有一第十一閘極端125a、一第十一汲極端125b及一第十一源極端125c，該第十一源極端125c係電性連接該半波整流器110，該第十一閘極端125a係電性連接該第十一汲極端125b，該第四PMOS電晶體125係能等效為一二極體，以降低電路之直流電流，又，該封包回復電路120係另具有一第八NMOS電晶體126及一第九NMOS電晶體127，該第八NMOS電晶體126係具有一第十二閘極端126a、一第十二汲極端126b及一第十二源極端126c，該第九NMOS電晶體127係具有一第十三閘極端127a、一第十三汲極端127b及一第十三源極端127c，該第十二閘極端126a係電性連接該第十二汲極端126b、該第十一閘極端125a、該第十一汲極端125b及該第十三閘極端127a，該第十三汲極端127b係電性連接該差動放大器122之該第一NMOS電晶體1221之該第一源極端1221c及該第二NMOS電晶體1222之該第二源極端1222c，其中該第八NMOS電晶體126及該第九NMOS電晶體127係作為一電流鏡以供應該差動放大器122使用。
請參閱第1及2圖，本發明之電路作動係敘述如下，將所接收之幅移鍵控訊號輸入至該半波整流器110，在本實施例中，由於該半波整流器110之該第六NMOS電晶體112及該第七NMOS電晶體113係可分別等效為一整流二極體及一穩壓電容，因此本發明無須使用一般被動元件如電阻及電容等，故可有效降低電路之功率消耗，增加該差動放大器122之判斷可靠度，接著，將經由整流後之幅移鍵控訊號輸送至該封包回復電路120，該封包回復電路120係用以將幅移鍵控訊號轉換為數位訊號，當此時之幅移鍵控訊號為高電位時，由於該第二壓差產生電路123中有一顆電晶體為PMOS電晶體，因此該第一壓差產生電路123係能使該第一NMOS電晶體1221之該第一閘極端1221a之端電壓VP
大於該第二NMOS電晶體1222之該第二閘極端1222a之端電壓VN
，故，通過該第一NMOS電晶體1221之電流係大於通過該第二NMOS電晶體1222之電流，此時流至該緩衝器130之電流因而大幅增加，使得該緩衝器130所輸出之數位訊號為1，相對地，當此時之幅移鍵控訊號為低電位時，該第一閘極端1221a之端電壓VP
低於該第二閘極端1222a之端電壓VN
，此時該緩衝器130之該訊號輸出端131所輸出之數位訊號為0。
本發明係藉由該第一壓差產生電路123及該第二壓差產生電路124，可使得該第一NMOS電晶體1221之該第一閘極端1221a及該第二NMOS電晶體1222之該第二閘極端1222a之間產生明顯的電位差異，當該半波整流器110輸出之訊號為高電位，則該第一閘極端1221a之端電壓VP
高於該第二閘極端1222a之端電壓VN
，此時該緩衝器130之該訊號輸出端131所輸出之數位訊號為1，反之，當該半波整流器110輸出之訊號為低電位，則該第一閘極端1221a之端電壓VP
低於該第二閘極端1222a之端電壓VN
，此時該緩衝器130之該訊號輸出端131所輸出之數位訊號為0，藉由上述的電路設計，能有效獲得一具有高可靠度解調訊號之解調變電路，又，由於本發明無須使用一般被動元件如電阻及電容，因此能有效降低晶片面積，故，本發明能有效應用於體內脊椎電刺激模組(Spinal cord stimulation module)中。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
Referring to FIG. 1 , which is a preferred embodiment of the present invention, an amplitude shift keying demodulation circuit 100 includes a half wave rectifier 110, a packet recovery circuit 120 and a buffer 130. The rectifier 110 has a signal input terminal 111 for receiving an Amplitude Shift Keying signal. The Packet Recovery Circuit 120 is electrically connected to the Half Wave Rectifier 110 and has a current mirror 121 and an electrical The differential amplifier 122, the first differential pressure generating circuit 123 and the second differential pressure generating circuit 124 are connected to the current mirror 121. The differential amplifier 122 has a first NMOS transistor 1221 and an electrical connection. a second NMOS transistor 1222 of the first NMOS transistor 1221, the first NMOS transistor 1221 having a first gate terminal 1221a, a first threshold electrode 1221b and a first source terminal 1221c, the second NMOS transistor The 1222 has a second gate terminal 1222a, a second gate terminal 1222b, and a second source terminal 1222c. The current mirror 121 has a first PMOS transistor 1211 and a second PMOS transistor 1212. A PMOS transistor 1211 has a third gate The second PMOS transistor 1212 has a fourth gate terminal 1212a, a fourth 汲 terminal 1212b and a fourth source terminal 1212c, the first terminal 1211a, the third NMOS terminal 1211b, and the third source terminal 1212c. The third 汲 terminal 1211b of the PMOS transistor 1211 is electrically connected to the third gate terminal 1211a, the fourth gate terminal 1212a and the first 汲 terminal 1221b, and the fourth 汲 terminal 1212b of the second PMOS transistor 1212 Electrically connecting the second NMOS terminal 1222b of the second NMOS transistor 1222, the first differential pressure generating circuit 123 is electrically connected to the first thyristor of the first NMOS transistor 1221 of the differential amplifier 122. 1212a, the second differential pressure generating circuit 124 is electrically connected to the second gate terminal 1222a of the second NMOS transistor 1222 of the differential amplifier 122. The buffer 130 has a signal output terminal 131 and an input terminal 132. The buffer 130 is electrically connected to the current mirror 121 of the packet recovery circuit 120 and the differential amplifier 122. In this embodiment, the input terminal 132 of the buffer 130 is electrically connected to the second NMOS. The second germanium terminal 1222b of the crystal 1222 and the second PMOS transistor The fourth extreme 1212b of 1212.
Referring to FIG. 1 again, in the embodiment, the first differential voltage circuit 123 of the packet recovery circuit 120 has a third NMOS transistor 1231 and a fourth NMOS transistor 1232. The third NMOS transistor The 1231 system has a fifth gate terminal 1231a, a fifth threshold electrode 1231b, and a fifth source terminal 1231c. The fourth NMOS transistor 1232 has a sixth gate terminal 1232a, a sixth gate terminal 1232b, and a sixth portion. a source terminal 1232c, the fifth gate terminal 1231a is electrically connected to the sixth gate terminal 1232a, and the fifth source terminal 1231c is electrically connected to the sixth gate terminal 1232b and the first gate of the first NMOS transistor 1221. The second voltage difference circuit 124 has a fifth NMOS transistor 1241 and a third PMOS transistor 1242. The fifth NMOS transistor 1241 has a seventh gate terminal 1241a and a seventh node. The second PMOS transistor 1242 has an eighth gate terminal 1242a, an eighth terminal electrode 1242b, and an eighth source terminal 1242c, wherein the seventh gate terminal 1241a is electrically connected to the terminal 1241b and the seventh source terminal 1241c. Connecting the eighth gate terminal 1242a, the seventh antenna terminal 1241b is electrically The drain terminal connected to the eighth and 1242b of the second NMOS transistor 1222 of the second gate terminal 1222a.
Referring to FIG. 1 again, the half-wave rectifier 110 further has a sixth NMOS transistor 112 and a seventh NMOS transistor 113. The sixth NMOS transistor 112 has a ninth gate terminal 112a and a ninth. The NMOS terminal 113 has a tenth gate electrode 113a, a tenth 汲 terminal 113b and a tenth source terminal 113c. The ninth gate terminal 112a is electrically connected. The signal input terminal 111 and the ninth terminal 112b are electrically connected to the tenth source terminal 113c. The ninth source terminal 112c is electrically connected to the tenth gate electrode 113a and the current mirror. The first PMOS transistor 1211, the second PMOS transistor 1212, the fifth gate terminal 1231a of the third NMOS transistor 1231, and the fourth NMOS transistor 1232 of the first differential voltage generating circuit 123 The sixth gate terminal 1232a, the seventh gate terminal 1241a of the fifth NMOS transistor 1241, and the eighth gate terminal 1242a of the third PMOS transistor 1242 of the second differential voltage generating circuit 124, in addition, In an embodiment, the packet recovery circuit 120 of the amplitude shift keying demodulation circuit 100 has another a fourth PMOS transistor 125 having an eleventh gate terminal 125a, an eleventh gate electrode 125b and an eleventh source terminal 125c, wherein the eleventh source terminal 125c is electrically The half-wave rectifier 110 is electrically connected to the eleventh gate electrode 125b. The fourth PMOS transistor 125 is equivalent to a diode to reduce the DC current of the circuit. In addition, the packet recovery circuit 120 further has an eighth NMOS transistor 126 and a ninth NMOS transistor 127. The eighth NMOS transistor 126 has a twelfth gate 126a and a twelfth 汲 terminal. 126b and a twelfth source terminal 126c, the ninth NMOS transistor 127 has a thirteenth gate terminal 127a, a thirteenth 汲 terminal 127b and a thirteenth source terminal 127c, and the twelfth gate terminal 126a Electrically connecting the twelfth pole extreme 126b, the eleventh gate extreme 125a, the eleventh pole extreme 125b and the thirteenth gate extreme 127a, the thirteenth pole extreme 127b is electrically connected to the differential The first source terminal 1221c and the second NMOS transistor 1222 of the first NMOS transistor 1221 of the amplifier 122 The second source terminal 1222c, wherein the eighth NMOS transistor 126 and the ninth NMOS transistor 127 are used as a current mirror to supply the differential amplifier 122.
Referring to Figures 1 and 2, the circuit actuation of the present invention is described as follows. The received amplitude shift keying signal is input to the half wave rectifier 110. In this embodiment, due to the sixth of the half wave rectifier 110. The NMOS transistor 112 and the seventh NMOS transistor 113 can be equivalent to a rectifying diode and a voltage stabilizing capacitor, respectively. Therefore, the present invention does not need to use general passive components such as resistors and capacitors, thereby effectively reducing the power of the circuit. Consumption, increasing the reliability of the differential amplifier 122, and then transmitting the rectified amplitude shift key signal to the packet recovery circuit 120, the packet recovery circuit 120 for converting the amplitude shift key signal into a digital position The signal, when the amplitude shift key signal is high, the first differential pressure generating circuit 123 can enable the first one because the transistor in the second differential pressure generating circuit 123 is a PMOS transistor. The terminal voltage V P of the first gate terminal 1221a of the NMOS transistor 1221 is greater than the terminal voltage V N of the second gate terminal 1222a of the second NMOS transistor 1222, so that the current system passing through the first NMOS transistor 1221 Greater than through the second The current of the NMOS transistor 1222, the current flowing to the buffer 130 is thus greatly increased, so that the digital signal output by the buffer 130 is 1, and relatively, when the amplitude shift key signal is low at this time, The terminal voltage V P of the first gate terminal 1221a is lower than the terminal voltage V N of the second gate terminal 1222a. At this time, the digital signal outputted by the signal output terminal 131 of the buffer 130 is zero.
According to the present invention, the first differential voltage generating circuit 123 and the second differential pressure generating circuit 124 can make the first gate electrode 1221a and the second NMOS transistor 1222 of the first NMOS transistor 1221. A significant potential difference is generated between the two gate terminals 1222a. When the signal output by the half wave rectifier 110 is high, the terminal voltage V P of the first gate terminal 1221a is higher than the terminal voltage V N of the second gate terminal 1222a. At this time, the digital signal outputted by the signal output terminal 131 of the buffer 130 is 1, and when the signal output by the half-wave rectifier 110 is low, the terminal voltage V P of the first gate terminal 1221a is lower than The terminal voltage V N of the second gate terminal 1222a is 0, and the digital signal outputted by the signal output terminal 131 of the buffer 130 is 0. By the above circuit design, a high reliability demodulation signal can be effectively obtained. The demodulation circuit, in addition, because the invention does not need to use general passive components such as resistors and capacitors, thereby effectively reducing the wafer area, the present invention can be effectively applied to a spinal cord stimulation module in the body. .
The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
100．．．幅移鍵控解調變電路100. . . Amplitude shift keying demodulation circuit
110．．．半波整流器110. . . Half wave rectifier
111．．．訊號輸入端111. . . Signal input
112．．．第六NMOS電晶體112. . . Sixth NMOS transistor
112a．．．第九閘極端112a. . . Ninth gate extreme
112b．．．第九汲極端112b. . . Ninth extreme
112c．．．第九源極端112c. . . Ninth source extreme
113．．．第七NMOS電晶體113. . . Seventh NMOS transistor
113a．．．第十閘極端113a. . . Tenth gate extreme
113b．．．第十汲極端113b. . . Tenth extreme
113c．．．第十源極端113c. . . Tenth source extreme
120．．．封包回復電路120. . . Packet reply circuit
121．．．電流鏡121. . . Current mirror
1211．．．第一PMOS電晶體1211. . . First PMOS transistor
1211a．．．第三閘極端1211a. . . Third gate extreme
1211b．．．第三汲極端1211b. . . Third extreme
1211c．．．第三源極端1211c. . . Third source extreme
1212．．．第二PMOS電晶體1212. . . Second PMOS transistor
1212a．．．第四閘極端1212a. . . Fourth gate extreme
1212b．．．第四汲極端1212b. . . Fourth extreme
1212c．．．第四源極端1212c. . . Fourth source extreme
122．．．差動放大器122. . . Differential amplifier
1221．．．第一NMOS電晶體1221. . . First NMOS transistor
1221a．．．第一閘極端1221a. . . First gate extreme
1221b．．．第一汲極端1221b. . . First extreme
1221c．．．第一源極端1221c. . . First source extreme
1222．．．第二NMOS電晶體1222. . . Second NMOS transistor
1222a．．．第二閘極端1222a. . . Second gate extreme
1222b．．．第二汲極端1222b. . . Second extreme
1222c．．．第二源極端1222c. . . Second source extreme
123．．．第一壓差產生電路123. . . First differential pressure generating circuit
1231．．．第三NMOS電晶體1231. . . Third NMOS transistor
1231a．．．第五閘極端1231a. . . Fifth gate extreme
1231b．．．第五汲極端1231b. . . Fifth extreme
1231c．．．第五源極端1231c. . . Fifth source extreme
1232．．．第四NMOS電晶體1232. . . Fourth NMOS transistor
1232a．．．第六閘極端1232a. . . Sixth gate extreme
1232b．．．第六汲極端1232b. . . Sixth extreme
1232c．．．第六源極端1232c. . . Sixth source extreme
124．．．第二壓差產生電路124. . . Second differential pressure generating circuit
1241．．．第五NMOS電晶體1241. . . Fifth NMOS transistor
1241a．．．第七閘極端1241a. . . Seventh gate extreme
1241b．．．第七汲極端1241b. . . Seventh 汲 extreme
1241c．．．第七源極端1241c. . . Seventh source extreme
1242．．．第三PMOS電晶體1242. . . Third PMOS transistor
1242a．．．第八閘極端1242a. . . Eighth gate extreme
1242b．．．第八汲極端1242b. . . Eighth extreme
1242c．．．第八源極端1242c. . . Eighth source extreme
125．．．第四PMOS電晶體125. . . Fourth PMOS transistor
125a．．．第十一閘極端125a. . . Eleventh gate extreme
125b．．．第十一汲極端125b. . . Eleventh extreme
125c．．．第十一源極端125c. . . Eleventh source extreme
126．．．第八NMOS電晶體126. . . Eighth NMOS transistor
126a．．．第十二閘極端126a. . . Twelfth gate extreme
126b．．．第十二汲極端126b. . . Twelfth 汲 extreme
126c．．．第十二源極端126c. . . Twelfth source extreme
127．．．第九NMOS電晶體127. . . Ninth NMOS transistor
127a．．．第十三閘極端127a. . . Thirteenth gate extreme
127b．．．第十三汲極端127b. . . Thirteenth Extreme
127c．．．第十三源極端127c. . . Thirteen source extreme
130．．．緩衝器130. . . buffer
131．．．訊號輸出端131. . . Signal output
132．．．輸入端132. . . Input
200．．．幅移鍵控解調器200. . . Amplitude shift keying demodulator
210．．．偏壓電流供應單元210. . . Bias current supply unit
211．．．參考偏壓供應電路211. . . Reference bias supply circuit
212．．．參考電流控制電路212. . . Reference current control circuit
212a．．．第一RC濾波器212a. . . First RC filter
212b．．．差動放大器212b. . . Differential amplifier
212c．．．第二RC濾波器212c. . . Second RC filter
213．．．參考電流輸出電路213. . . Reference current output circuit
220．．．調變訊號產生器220. . . Modulated signal generator
第1圖：依據本發明之第一較佳實施例，一種幅移鍵控解調變電路之電路圖。
第2圖：依據本發明之第一較佳實施例，該幅移鍵控解調變電路之訊號調變圖。
第3圖：習知幅移鍵控解調器之電路圖。
Figure 1 is a circuit diagram of an amplitude shift keying demodulation circuit in accordance with a first preferred embodiment of the present invention.
Figure 2 is a diagram showing the signal modulation of the amplitude shift keying demodulation circuit in accordance with a first preferred embodiment of the present invention.
Figure 3: Circuit diagram of a conventional amplitude shift keying demodulator.
100．．．幅移鍵控解調變電路100. . . Amplitude shift keying demodulation circuit
110．．．半波整流器110. . . Half wave rectifier
111．．．訊號輸入端111. . . Signal input
112．．．第六NMOS電晶體112. . . Sixth NMOS transistor
112a．．．第九閘極端112a. . . Ninth gate extreme
112b．．．第九汲極端112b. . . Ninth extreme
112c．．．第九源極端112c. . . Ninth source extreme
113．．．第七NMOS電晶體113. . . Seventh NMOS transistor
113a．．．第十閘極端113a. . . Tenth gate extreme
113b．．．第十汲極端113b. . . Tenth extreme
113c．．．第十源極端113c. . . Tenth source extreme
120．．．封包回復電路120. . . Packet reply circuit
121．．．電流鏡121. . . Current mirror
1211．．．第一PMOS電晶體1211. . . First PMOS transistor
1211a．．．第三閘極端1211a. . . Third gate extreme
1211b．．．第三汲極端1211b. . . Third extreme
1211c．．．第三源極端1211c. . . Third source extreme
1212．．．第二PMOS電晶體1212. . . Second PMOS transistor
1212a．．．第四閘極端1212a. . . Fourth gate extreme
1212b．．．第四汲極端1212b. . . Fourth extreme
1212c．．．第四源極端1212c. . . Fourth source extreme
122．．．差動放大器122. . . Differential amplifier
1221．．．第一NMOS電晶體1221. . . First NMOS transistor
1221a．．．第一閘極端1221a. . . First gate extreme
1221b．．．第一汲極端1221b. . . First extreme
1221c．．．第一源極端1221c. . . First source extreme
1222．．．第二NMOS電晶體1222. . . Second NMOS transistor
1222a．．．第二閘極端1222a. . . Second gate extreme
1222b．．．第二汲極端1222b. . . Second extreme
1222c．．．第二源極端1222c. . . Second source extreme
123．．．第一壓差產生電路123. . . First differential pressure generating circuit
1231．．．第三NMOS電晶體1231. . . Third NMOS transistor
1231a．．．第五閘極端1231a. . . Fifth gate extreme
1231b．．．第五汲極端1231b. . . Fifth extreme
1231c．．．第五源極端1231c. . . Fifth source extreme
1232．．．第四NMOS電晶體1232. . . Fourth NMOS transistor
1232a．．．第六閘極端1232a. . . Sixth gate extreme
1232b．．．第六汲極端1232b. . . Sixth extreme
1232c．．．第六源極端1232c. . . Sixth source extreme
124．．．第二壓差產生電路124. . . Second differential pressure generating circuit
1241．．．第五NMOS電晶體1241. . . Fifth NMOS transistor
1241a．．．第七閘極端1241a. . . Seventh gate extreme
1241b．．．第七汲極端1241b. . . Seventh 汲 extreme
1241c．．．第七源極端1241c. . . Seventh source extreme
1242．．．第三PMOS電晶體1242. . . Third PMOS transistor
1242a．．．第八閘極端1242a. . . Eighth gate extreme
1242b．．．第八汲極端1242b. . . Eighth extreme
1242c．．．第八源極端1242c. . . Eighth source extreme
125．．．第四PMOS電晶體125. . . Fourth PMOS transistor
125a．．．第十一閘極端125a. . . Eleventh gate extreme
125b．．．第十一汲極端125b. . . Eleventh extreme
125c．．．第十一源極端125c. . . Eleventh source extreme
126．．．第八NMOS電晶體126. . . Eighth NMOS transistor
126a．．．第十二閘極端126a. . . Twelfth gate extreme
126b．．．第十二汲極端126b. . . Twelfth 汲 extreme
126c．．．第十二源極端126c. . . Twelfth source extreme
127．．．第九NMOS電晶體127. . . Ninth NMOS transistor
127a．．．第十三閘極端127a. . . Thirteenth gate extreme
127b．．．第十三汲極端127b. . . Thirteenth Extreme
127c．．．第十三源極端127c. . . Thirteen source extreme
130．．．緩衝器130. . . buffer
131．．．訊號輸出端131. . . Signal output
132．．．輸入端132. . . Input
Claims (8)
一半波整流器，其係具有一訊號輸入端;
一封包回復電路，其係電性連接該半波整流器，該封包回復電路係具有一電流鏡、一差動放大器、一第一壓差產生電路及一第二壓差產生電路，該差動放大器係具有一第一NMOS電晶體及一電性連接該第一NMOS電晶體之第二NMOS電晶體，該差動放大器係電性連接該電流鏡，該第一壓差產生電路係電性連接該差動放大器之該第一NMOS電晶體之第一閘極端，該第二壓差產生電路係電性連接該差動放大器之該第二NMOS電晶體之第二閘極端；以及
一緩衝器，其係具有一訊號輸出端，該緩衝器係電性連接該封包回復電路之該電流鏡及該差動放大器。An amplitude shift keying demodulation circuit comprising:
a half-wave rectifier having a signal input;
a packet recovery circuit electrically connected to the half-wave rectifier, the packet recovery circuit having a current mirror, a differential amplifier, a first differential pressure generating circuit and a second differential pressure generating circuit, the differential amplifier The first NMOS transistor and a second NMOS transistor electrically connected to the first NMOS transistor, the differential amplifier is electrically connected to the current mirror, and the first differential pressure generating circuit is electrically connected to the a first gate terminal of the first NMOS transistor of the differential amplifier, the second voltage difference generating circuit is electrically connected to the second gate terminal of the second NMOS transistor of the differential amplifier; and a buffer The system has a signal output terminal, and the buffer is electrically connected to the current mirror of the packet recovery circuit and the differential amplifier.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200824376A (en) * | 2006-07-14 | 2008-06-01 | Ibm | Quadrature modulation circuits and systems supporting multiple modulation modes at gigabit data rates |
| WO2008093254A1 (en) * | 2007-01-31 | 2008-08-07 | Nxp B.V. | Demodulation circuit for ask coded or amplitude modulated signals as well as nfc and rfid devices comprising the same |
| US20100158157A1 (en) * | 2008-12-24 | 2010-06-24 | Kabushiki Kaisha Toshiba | Ask demodulator, communication module, communication device, and ask demodulation method |
| US20100164724A1 (en) * | 2008-12-29 | 2010-07-01 | Yuan-Jiang Lee | Amplitude Shift Keying Demodulator and Radio Frequency Identification System using the same |
| TW201119303A (en) * | 2009-11-19 | 2011-06-01 | Univ Nat Sun Yat Sen | Wireless duplex modulation circuit |
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2011
- 2011-08-25 TW TW100130508A patent/TWI482466B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200824376A (en) * | 2006-07-14 | 2008-06-01 | Ibm | Quadrature modulation circuits and systems supporting multiple modulation modes at gigabit data rates |
| WO2008093254A1 (en) * | 2007-01-31 | 2008-08-07 | Nxp B.V. | Demodulation circuit for ask coded or amplitude modulated signals as well as nfc and rfid devices comprising the same |
| US20100158157A1 (en) * | 2008-12-24 | 2010-06-24 | Kabushiki Kaisha Toshiba | Ask demodulator, communication module, communication device, and ask demodulation method |
| US20100164724A1 (en) * | 2008-12-29 | 2010-07-01 | Yuan-Jiang Lee | Amplitude Shift Keying Demodulator and Radio Frequency Identification System using the same |
| TW201119303A (en) * | 2009-11-19 | 2011-06-01 | Univ Nat Sun Yat Sen | Wireless duplex modulation circuit |
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