TWI474595B - Switching mode power supply with a spectrum shaping circuit - Google Patents
Switching mode power supply with a spectrum shaping circuit Download PDFInfo
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Description
本專利申請案所述技術大體上關於切換模式電源供應。此申請案主張2009年5月26日申請之中國專利申請案第200910059429.7號的優先權及權益,其完整內容以引用的方式併入本文中。 The techniques described in this patent application relate generally to switched mode power supplies. The priority and benefit of Chinese Patent Application No. 200910059429.7, filed on May 26, 2009, is hereby incorporated by reference.
在一典型切換模式電源供應中,由切換頻率造成的諧波通常會增添整體系統之電磁干擾(EMI)。這對於具有由一高切換頻率造成之大量諧波增益的電源供應來說特別是個問題。因此最好提供一可以高切換頻率運作且對EMI有一減低效果的切換模式電源供應。 In a typical switched mode power supply, the harmonics caused by the switching frequency typically add to the overall system's electromagnetic interference (EMI). This is especially problematic for power supplies with a large amount of harmonic gain caused by a high switching frequency. Therefore, it is preferable to provide a switched mode power supply that can operate at a high switching frequency and has a reduced effect on EMI.
依據本發明之教示,提出用於切換模式電源供應之系統及方法。 In accordance with the teachings of the present invention, systems and methods for switching mode power supplies are presented.
在一實例中,該切換模式電源供應可包含一變壓器、一切換電路及一切換控制電路。該變壓器在一初級繞組上接收一DC輸入電壓且在一次級繞組上產生一DC輸出電壓。該切換電路(其可包含一MOSFET開關)耦接至該變壓器且經構形用以接通及斷開該變壓器。該切換控制電路產生一切換控制信號用來控制該切換電路以便調節該變壓器之DC輸出電壓。該切換控制電路經構形用以產生該切換控制信號為一具有一變動頻率之一時序信號的函數,其中該時序信號之變動頻率導致該切換電路之一切換 頻率在一段時間當中變動。 In an example, the switched mode power supply can include a transformer, a switching circuit, and a switching control circuit. The transformer receives a DC input voltage on a primary winding and a DC output voltage on a secondary winding. The switching circuit (which may include a MOSFET switch) is coupled to the transformer and configured to turn the transformer on and off. The switching control circuit generates a switching control signal for controlling the switching circuit to adjust the DC output voltage of the transformer. The switching control circuit is configured to generate the switching control signal as a function of a timing signal having a varying frequency, wherein the varying frequency of the timing signal causes one of the switching circuits to switch The frequency changes over time.
在另一實例中,該切換模式電源供應苦包含一整流器、一變壓器、一切換電路、及一切換控制電路。該整流器接收一AC輸入電壓且將該AC輸入電壓轉化成一DC輸入電壓。該變壓器經構形用以將其初級繞組上之一DC輸入電壓轉化成其次級繞組上之一DC輸出電壓。該切換電路耦接至該變壓器之初級繞組且經構形用以基於一切換控制信號控制通過該變壓器之初級繞組的電流。該切換控制電路產生該切換控制信號為一具有一變動頻率之一時序信號的函數,其中該時序信號之變動頻率導致該切換電路之一切換頻率在一段時間當中變動以便減小由該切換電路造成之電磁干擾。 In another example, the switched mode power supply includes a rectifier, a transformer, a switching circuit, and a switching control circuit. The rectifier receives an AC input voltage and converts the AC input voltage to a DC input voltage. The transformer is configured to convert a DC input voltage on its primary winding to a DC output voltage on its secondary winding. The switching circuit is coupled to the primary winding of the transformer and configured to control current through the primary winding of the transformer based on a switching control signal. The switching control circuit generates the switching control signal as a function of a timing signal having a varying frequency, wherein the varying frequency of the timing signal causes a switching frequency of the switching circuit to fluctuate over a period of time to reduce the switching circuit Electromagnetic interference.
一種調節一切換模式電源供應中之一輸出電壓的方法可包含以下步驟:產生一具有一變動頻率的時序信號;監測產生該輸出電壓之一變壓器的一或多個操作特性以產生一反體信號;產生一切換控制信號為該時序信號及該反饋信號之一函數;且利用該切換控制信號接通及斷開該變壓器以調節該輸出電壓,其中該時序信號之變動頻率導致該變壓器之一切換頻率在一段時間當中變動以便減小電磁干擾。 A method of adjusting an output voltage of a switched mode power supply can include the steps of: generating a timing signal having a varying frequency; monitoring one or more operational characteristics of the transformer that produce the output voltage to generate a reverse body signal Generating a switching control signal as a function of the timing signal and the feedback signal; and using the switching control signal to turn the transformer on and off to adjust the output voltage, wherein a varying frequency of the timing signal causes one of the transformers to switch The frequency changes over a period of time to reduce electromagnetic interference.
CLK‧‧‧固定頻率的時鐘輸出 CLK‧‧‧ fixed frequency clock output
Ct‧‧‧充電電容器 Ct‧‧‧Charging capacitor
FB‧‧‧閾值 FB‧‧‧ threshold
G‧‧‧串行輸出信號 G‧‧‧Serial output signal
I0、I1、Í2、I3‧‧‧切換電流源 I0, I1, Í2, I3‧‧‧ switching current source
Ict‧‧‧固定電流源 Ict‧‧‧fixed current source
ISENSE‧‧‧電流感測信號 ISENSE‧‧‧ current sensing signal
Q0-Q7‧‧‧D正反器 Q0-Q7‧‧‧D positive and negative
OR0、OR1、OR2‧‧‧邏輯閘 OR0, OR1, OR2‧‧‧ logic gate
S0、S1、S2、S3‧‧‧開關 S0, S1, S2, S3‧‧‧ switch
St‧‧‧開關 St‧‧ switch
SS‧‧‧類比信號、頻譜整形信號 SS‧‧‧ analog signal, spectrum shaping signal
Vds‧‧‧電壓 Vds‧‧‧ voltage
Vth‧‧‧閾電壓 Vth‧‧‧ threshold voltage
100‧‧‧實例切換模式電源供應 100‧‧‧Instance switching mode power supply
102‧‧‧頻譜整形電路、時序電路 102‧‧‧Spectrum shaping circuit, sequential circuit
104‧‧‧整流器電橋 104‧‧‧Rectifier Bridge
106‧‧‧變壓器 106‧‧‧Transformers
108‧‧‧切換電路 108‧‧‧Switching circuit
110‧‧‧切換控制電路 110‧‧‧Switching control circuit
112‧‧‧RS正反器 112‧‧‧RS forward and reverse
114、116、118‧‧‧反饋電路 114, 116, 118‧‧‧ feedback circuit
120‧‧‧振盪器 120‧‧‧Oscillator
122‧‧‧比較器 122‧‧‧ comparator
126‧‧‧位移暫存器 126‧‧‧Displacement register
128‧‧‧轉換器 128‧‧‧ converter
200‧‧‧接通點 200‧‧‧Connected point
300‧‧‧切換模式電源供應 300‧‧‧Switch mode power supply
302‧‧‧頻譜整形電路 302‧‧‧Spectrum shaping circuit
304‧‧‧時序信號 304‧‧‧ timing signal
306‧‧‧波谷偵測電路 306‧‧‧ Valley Detection Circuit
308‧‧‧電流感測電路 308‧‧‧ Current sensing circuit
310‧‧‧反饋電路 310‧‧‧ Feedback Circuit
312、314‧‧‧變壓器 312, 314‧‧‧ Transformers
316‧‧‧MOSFET開關 316‧‧‧ MOSFET switch
317‧‧‧RS正反器 317‧‧‧RS forward and reverse
318‧‧‧參考電路 318‧‧‧Reference circuit
320、322‧‧‧比較電路 320, 322‧‧‧ comparison circuit
324‧‧‧邏輯閘 324‧‧‧Logic gate
326‧‧‧延時電路 326‧‧‧delay circuit
328‧‧‧電壓調節器 328‧‧‧Voltage regulator
400‧‧‧波谷 400‧‧‧ trough
402‧‧‧閾值 402‧‧‧ threshold
404‧‧‧初始脈衝 404‧‧‧ initial pulse
500‧‧‧振盪器 500‧‧‧Oscillator
502‧‧‧位移暫存器 502‧‧‧Displacement register
504‧‧‧D/A轉換器 504‧‧‧D/A converter
600‧‧‧電壓受控振盪器 600‧‧‧Voltage controlled oscillator
602‧‧‧位移暫存器 602‧‧‧Displacement register
603‧‧‧D/A轉換器 603‧‧‧D/A converter
第1圖是一具有一頻譜整形電路之實例切換模式電源供應的簡圖。 Figure 1 is a simplified diagram of an example switching mode power supply with a spectral shaping circuit.
第2圖是一示出因改變第1圖切換模式電源供應中之切換頻率而獲得之諧波增益減小結果的圖。 Fig. 2 is a diagram showing the result of the harmonic gain reduction obtained by changing the switching frequency in the switching mode power supply of Fig. 1.
第3圖是一用於第1圖切換模式電源供應之實例時序電路的簡圖。 Figure 3 is a simplified diagram of an example sequential circuit for the switched mode power supply of Figure 1.
第4圖例示第1圖頻譜整形電路之一實例運作。 Figure 4 illustrates an example operation of the spectrum shaping circuit of Figure 1.
第5圖示出第1圖切換模式電源供應之切換波形(Vds)之一實例。 Fig. 5 is a view showing an example of the switching waveform (V ds ) of the switching mode power supply of Fig. 1.
第6圖是一具有一頻譜整形電路之另一實例切換模式電源供應的簡圖。 Figure 6 is a simplified diagram of another example switching mode power supply with a spectrum shaping circuit.
第7A圖和第7B圖示出一例示第6圖切換模式電源供應之一實例運作的時序圖。 Fig. 7A and Fig. 7B are timing charts showing an example of the operation of one example of the switching mode power supply of Fig. 6.
第8圖示出第6圖切換模式電源供應之切換波形(Vds)之一實例。 Fig. 8 shows an example of the switching waveform (V ds ) of the switching mode power supply of Fig. 6.
第9圖是一示出因改變第6圖切換模式電源供應中之切換頻率而獲得之諧波增益減小結果的圖。 Fig. 9 is a diagram showing the result of the harmonic gain reduction obtained by changing the switching frequency in the switching mode power supply of Fig. 6.
第10圖例示可供第6圖時序電路使用之實例週期性波形。 Figure 10 illustrates an example periodic waveform that can be used by the sequential circuit of Figure 6.
第11圖是一用於第6圖切換模式電源供應之一實例頻譜整形電路的簡圖。 Figure 11 is a simplified diagram of an example spectrum shaping circuit for a switched mode power supply of Figure 6.
第12圖是一用於第6圖切換模式電源供應之另一實例頻譜整形電路的簡圖。 Figure 12 is a simplified diagram of another example spectrum shaping circuit for the switching mode power supply of Figure 6.
第13圖是一例示第12圖頻譜整形電路之運作的時序圖。 Fig. 13 is a timing chart showing an example of the operation of the spectrum shaping circuit of Fig. 12.
第1圖是一具有一頻譜整形電路102之實例切換模式電源供應100的簡圖。切換模式電源供應100包含一整流器電橋104、一變壓器106、一切換電路108、及一切換控制電路110。運作時,整流器電橋104接收一AC輸入電壓(Vin),將該AC輸入電壓轉化成一被變壓器106之初級繞組接收的DC輸入電壓。變壓器106受切換電路108控制以在次級繞組上產生一DC輸出電壓(Vout)。可包含一MOSFET(如圖所示)或一些其他合適的電子切換器件之切換電路108控制通過變壓器106之初級繞組的電流以有效地接通及斷開變壓器106。第1圖亦例示一儲存 該DC輸入電壓的輸入電容器(Cin)、一儲存該DC輸出電壓的輸出電容器(Cout)、及一防止電流流回次級變壓器繞組內的二極體(D)。 1 is a simplified diagram of an example switched mode power supply 100 having a spectral shaping circuit 102. The switched mode power supply 100 includes a rectifier bridge 104, a transformer 106, a switching circuit 108, and a switching control circuit 110. In operation, bridge rectifier 104 receives an AC input voltage (V in), the AC input voltage is converted to a primary winding of the transformer 106 receives the DC input voltage. Transformer 106 by the switching circuit 108 controls to generate a DC output voltage (V out) on the secondary winding. A switching circuit 108, which may include a MOSFET (as shown) or some other suitable electronic switching device, controls the current through the primary winding of transformer 106 to effectively turn the transformer 106 on and off. Figure 1 also illustrates an input capacitor (C in ) that stores the DC input voltage, an output capacitor (C out ) that stores the DC output voltage, and a diode that prevents current from flowing back into the winding of the secondary transformer (D) ).
切換電路108受一切換控制信號111控制,該切換控制信號係由切換控制電路110產生為一具有一變動頻率之一時序信號的函數。在第1圖所示實例中,該時序信號係經由利用頻譜整形電路102改變一時鐘信號(CLK)之頻率而產生,詳見下文。這導致切換電路108之切換頻率在一段時間當中變動,改變切換頻譜之形狀以包含一較寬頻帶。藉由加大該切換頻率之帶寬,Vds之諧波增益減小從而導致EMI減小。 The switching circuit 108 is controlled by a switching control signal 111 which is generated by the switching control circuit 110 as a function of a timing signal having a varying frequency. In the example shown in Figure 1, the timing signal is generated by varying the frequency of a clock signal (CLK) using spectrum shaping circuit 102, as described below. This causes the switching frequency of the switching circuit 108 to fluctuate over a period of time, changing the shape of the switching spectrum to include a wider frequency band. By increasing the bandwidth of the switching frequency, the harmonic gain of Vds is reduced to cause EMI to decrease.
為幫助例示所得EMI減小度,第2圖提供一具備恆定切換頻率之典型切換模式電源供應中之Vds的諧波增益與第1圖實例之Vds的諧波增益之比較。 To help illustrate resultant EMI reduced degree, Fig. 2 includes a comparator providing a harmonic gain of V ds harmonic typical gain constant switching frequency of the switching mode power supply V ds to the first example of FIG.
在第2圖所示之圖中,三條垂直實線例示一典型切換模式電源供應中之Vds的主要諧波。點線代表第1圖切換模式電源供應中可能發生之減小諧波,其中切換頻率係變動的。如圖所示,藉由改變切換頻率,Vds的諧波散佈於一較寬頻譜當中且尖峰諧波減小。這導致系統EMI減小。 In the diagram shown in Figure 2, three vertical solid lines illustrate the main harmonics of Vds in a typical switched mode power supply. The dotted line represents the reduced harmonics that may occur in the switching mode power supply of Figure 1, where the switching frequency varies. As shown, by changing the switching frequency, the harmonics of Vds are spread over a wider spectrum and the peak harmonics are reduced. This leads to a reduction in system EMI.
再次參照第1圖,圖示實例中之切換電路110包含一RS正反器112、一反饋電路(114、116、118)及一時序電路(102、120)。該反饋電路利用一電流感測電路114、一電壓反饋電路116及一比較電路118產生重設輸入(R)給RS正反器112。該時序電路利用頻譜整形電路102及一振盪器120產生一時鐘信號(CLK)為設定輸入(S)給RS正反器112。RS正反器112讓重設信號(R)有高於設定信號(S)的優先權。因此,在重設輸入(R)處於一高邏輯狀態之時會在該正反器之Q輸出上產生一邏輯低輸 出(亦即切換控制信號111),這導致MOSFET開關108斷開,停止通過變壓器106之初級繞組的電流。設定輸入(S)至該正反器之一高邏輯狀態(在此同時R為低)會在Q產生一邏輯高輸出,導致MOSFET開關108回到接通,允許電流通過該初級繞組。 Referring again to FIG. 1, the switching circuit 110 of the illustrated example includes an RS flip-flop 112, a feedback circuit (114, 116, 118), and a timing circuit (102, 120). The feedback circuit utilizes a current sensing circuit 114, a voltage feedback circuit 116, and a comparison circuit 118 to generate a reset input (R) to the RS flip-flop 112. The timing circuit uses the spectrum shaping circuit 102 and an oscillator 120 to generate a clock signal (CLK) as a set input (S) to the RS flip-flop 112. The RS flip-flop 112 causes the reset signal (R) to have a higher priority than the set signal (S). Therefore, a logic low input is generated on the Q output of the flip-flop when the reset input (R) is in a high logic state. Out (ie, switching control signal 111), which causes MOSFET switch 108 to open, stopping current flow through the primary winding of transformer 106. Setting the input (S) to one of the high logic states of the flip flop (while R is low) will produce a logic high output at Q, causing the MOSFET switch 108 to return to turn on, allowing current to pass through the primary winding.
在該反饋電路中,電流感測電路114產生一與通過變壓器106之初級繞組的電流成正比之電流感測信號(Isense),且電壓反饋電路116產生一反饋信號(FB),該反饋信號提供一閾值以將變壓器106之DC電壓輸出(Vout)調節成一期望值。由比較電路118比較電流感測信號(Isense)與反饋信號(FB)以產生送至正反器112之重設輸入(R),在例示實例中該比較電路係一單一比較器。比較電路118因而在電流感測信號(Isense)達到反饋信號(FB)所設定之閾值時在重設輸入(R)產生一邏輯高脈衝。在該時序電路中,利用一定頻振盪器120產生一時鐘信號(CLK),且由頻譜整形電路102改變時鐘信號(CLK)之頻率以產生作為設定輸入(S)送至RS正反器112之時序信號。依此方式,由於電流感測信號(Isense)導致MOSFET開關108將變壓器106斷開且該時序電路之時鐘脈衝將變壓器106回復成接通,變壓器106持續循環經歷斷開及接通週期。藉由改變時鐘脈衝之頻率,MOSFET開關108之接通點變成可變的,如第5圖所示,這減小系統EMI。 In the feedback circuit, the current sensing circuit 114 generates a current sense signal (I sense ) proportional to the current through the primary winding of the transformer 106, and the voltage feedback circuit 116 generates a feedback signal (FB), the feedback signal providing a threshold value to the DC voltage output of the transformer 106 (V out) is adjusted to a desired value. The current sense signal (I sense ) and the feedback signal (FB) are compared by the comparison circuit 118 to produce a reset input (R) to the flip flop 112, which in the illustrated example is a single comparator. The comparison circuit 118 thus produces a logic high pulse at the reset input (R) when the current sense signal (I sense ) reaches the threshold set by the feedback signal (FB). In the sequential circuit, a clock signal (CLK) is generated by the fixed frequency oscillator 120, and the frequency of the clock signal (CLK) is changed by the spectrum shaping circuit 102 to be sent to the RS flip-flop 112 as a set input (S). Timing signal. In this manner, since the current sense signal (I sense ) causes the MOSFET switch 108 to turn off the transformer 106 and the clock pulse of the sequential circuit returns the transformer 106 to turn on, the transformer 106 continues to cycle through the turn-off and turn-on cycles. By changing the frequency of the clock pulses, the turn-on point of MOSFET switch 108 becomes variable, as shown in Figure 5, which reduces system EMI.
第3圖是一用於第1圖切換模式電源供應之一實例時序電路的簡圖。該時序電路包含一頻譜整形電路102及一振盪器120。在振盪器120中,由一固定電流源(Ict)與一從頻譜整形電路102接收之頻譜整形信號(SS)的組合改變橫跨一充電電容器(Ct)之電壓。由一比較器122在橫跨充電電容器(Ct)之電壓達到一閾電壓(Vth)時產生一時鐘脈衝(CLK)。時鐘信號(CLK)亦控制一開關(St) 以在每一時鐘脈衝使充電電容器(Ct)放電。運作時,振盪器120因為頻譜整形信號(SS)所提供之一變動電流而產生一具有一變動頻率的時鐘信號(CLK)。 Figure 3 is a simplified diagram of an example sequential circuit for a switched mode power supply of Figure 1. The timing circuit includes a spectrum shaping circuit 102 and an oscillator 120. In oscillator 120, the combination of a fixed current source (I ct ) and a spectrally shaped signal (SS) received from spectral shaping circuit 102 varies the voltage across a charging capacitor (C t ). A clock pulse (CLK) is generated by a comparator 122 when the voltage across the charging capacitor ( Ct ) reaches a threshold voltage ( Vth ). The clock signal (CLK) also controls a switch (S t ) to discharge the charging capacitor (C t ) at each clock pulse. In operation, oscillator 120 produces a clock signal (CLK) having a varying frequency due to a varying current provided by the spectral shaping signal (SS).
頻譜整形電路102利用一位移暫存器126產生變動頻譜整形信號(SS),該位移暫存器控制一數位-類比(D/A)轉換器128中之一系列切換電流源(13-10)的輸出。位移暫存器126包含一系列的D正反器(Q0-Q7),該等D正反器係由來自振盪器120之時鐘信號(CLK)驅動且經構形用以使每一時鐘脈衝通過該位移暫存器之一邏輯〝1〞位移。該位移暫存器之輸出(Q0-Q7)被輸入至一系列邏輯閘(OR2-OR0)以產生一個四位元數位控制字元,後者被輸入至D/A轉換器128。在D/A轉換器128中,藉由控制一系列的開關(S0-S3)切換電流源(I3-I0)接通及斷開來改變SS之電流而將該四位元控制字元轉化成一類比頻譜整形(SS)信號。 The spectrum shaping circuit 102 generates a varying spectrum shaping signal (SS) by using a shift register 126 that controls a series of switching current sources (13-10) in a digital-to-analog ratio (D/A) converter 128. Output. The shift register 126 includes a series of D flip-flops (Q0-Q7) that are driven by a clock signal (CLK) from the oscillator 120 and configured to pass each clock pulse. One of the displacement registers is logically 〝1〞 displaced. The output of the shift register (Q0-Q7) is input to a series of logic gates (OR2-OR0) to generate a four-bit digital control word which is input to the D/A converter 128. In the D/A converter 128, the four-bit control word is converted into one by changing the current of the SS by controlling a series of switches (S0-S3) to switch the current source (I3-I0) on and off. Analog spectrum shaping (SS) signal.
頻譜整形電路102經歷該SS信號之一個循環的實例運作例示於第4圖。如第4圖所示,該位移暫存器之每一時鐘(Q7-Q0)導致開關系列(S3-S0)加大SS之電流。特定言之,開關S0係用來供應0.25I,開關S1係用來供應0.5I,開關S2係用來供應0.75I,且開關S3係用來供應I。在該例示實例中,頻譜整形電路102經構形用以依一重複模式將SS從0提高至一峰值(I)然後降回到0。依此方式,改變振盪器120中之電容器(Ct)的該SS信號之電流隨每一時鐘脈衝(CLK)增量,導致時鐘信號(CLK)之頻率依SS之一函數改變。也就是說,時鐘頻率隨著SS電流加大而加大。 An example operation of the spectrum shaping circuit 102 undergoing one cycle of the SS signal is illustrated in FIG. As shown in Figure 4, each clock (Q7-Q0) of the shift register causes the switch series (S3-S0) to increase the current of SS. In particular, switch S0 is used to supply 0.25I, switch S1 is used to supply 0.5I, switch S2 is used to supply 0.75I, and switch S3 is used to supply I. In this illustrative example, spectrum shaping circuit 102 is configured to increase SS from 0 to a peak (I) and then back to zero in a repeating pattern. In this manner, changing the current of the SS signal of the capacitor ( Ct ) in the oscillator 120 with each clock pulse (CLK) increment causes the frequency of the clock signal (CLK) to change according to a function of SS. That is to say, the clock frequency increases as the SS current increases.
第5圖示出橫跨第1圖的MOSFET開關108之電壓(Vds)之一實例,此時該開關為斷開。第5圖例示MOSFET開關108之接通點200如何因時鐘信號(CLK) 之變化而變動(在影線區200內)。開關接通點200之此變化造成一可變切換頻率,其在接通時將Vds之諧波分散於一較寬頻譜當中,導致EMI如前所述減小。 Figure 5 shows an example of the voltage (V ds ) across the MOSFET switch 108 of Figure 1, where the switch is open. Figure 5 illustrates how the turn-on point 200 of the MOSFET switch 108 varies due to changes in the clock signal (CLK) (within the hatch region 200). This change in switch-on point 200 causes a variable switching frequency that, when turned on, disperses the harmonics of Vds across a wider spectrum, resulting in a reduction in EMI as previously described.
第6圖是一具有一頻譜整形電路302之另一實例切換模式電源供應300的簡圖,該頻譜整形電路使該電源供應之切換頻率變動。在此實例中,使切換頻率變動的時序信號304係利用一準共振變換器產生,該準共振變換器包含一波谷偵測電路306以使該切換頻率與切換波形(Vds)中之一波谷對準。此準共振切換技術降低該變壓器中之功率損失,進一步提高系統效率。第6圖亦例示用於電流感測電路308及反饋電路310之實例電路實施,其亦可被用在第1圖之實例中。 Figure 6 is a simplified diagram of another example switched mode power supply 300 having a spectral shaping circuit 302 that varies the switching frequency of the power supply. In this example, the timing signal 304 for varying the switching frequency is generated by a quasi-resonant converter including a valley detecting circuit 306 to cause one of the switching frequency and the switching waveform (V ds ). alignment. This quasi-resonant switching technique reduces power loss in the transformer and further increases system efficiency. FIG. 6 also illustrates an example circuit implementation for current sensing circuit 308 and feedback circuit 310, which may also be used in the example of FIG.
第6圖所示切換模式電源供應包含一整流器電橋312,一具有一個初級繞組及二個次級繞組的變壓器314,一切換電路316,及一具有一RS正反器317、一反饋電路及一時序電路的切換控制電路。在此實例中,該時序電路包含一頻譜整形電路302、一參考電路318、一波谷偵測電路306、及一比較電路320。該反饋電路包含電流感測電路308、反饋電路310、一比較電路322、一邏輯閘324、及一延時電路326。 The switching mode power supply shown in FIG. 6 comprises a rectifier bridge 312, a transformer 314 having a primary winding and two secondary windings, a switching circuit 316, and an RS flip-flop 317, a feedback circuit and A switching control circuit for a sequential circuit. In this example, the timing circuit includes a spectrum shaping circuit 302, a reference circuit 318, a valley detecting circuit 306, and a comparison circuit 320. The feedback circuit includes a current sensing circuit 308, a feedback circuit 310, a comparison circuit 322, a logic gate 324, and a delay circuit 326.
在電流感測電路308中包含一電阻器(Rs)以提供一與通過變壓器314之初級繞組之電流量成正比的電壓(Isense)。在反饋電路310中,一電壓調節器328(例如TL431)經構形用以藉由控制在該時序電路之每一循環期間該變壓器保持接通之時間量的方式維持DC電壓輸出(Vout)之一期望電壓位準而提供一參考電壓(FB)。期望DC電壓輸出(Vout)可藉由改變反饋電路310中之電阻器值以調整閾電壓(FB)之位準的方式予以設定,該閾電壓位準經比較電路322與電流感測信號(Isense)做比較。比 較電路322之輸出透過OR邏輯閘324耦接至正反器317之重設輸入(R)。如第7圖所示,這導致MOSFET開關316在電流感測信號(Isense)達到參考電壓(FB)時斷開(產生一橫跨Vds的電壓)。 It comprises a resistor (R s) in the current sensing circuit 308 to provide a voltage (I sense) proportional to the amount of current through the primary winding of the transformer 314. In the feedback circuit 310, a voltage regulator 328 (e.g., the TL431) via configuration for the transformer by controlling the amount of time it turned a manner to maintain the DC voltage output (V out) during each cycle of the timing circuit One of the desired voltage levels provides a reference voltage (FB). Be set to a desired DC output voltage (V out) can be changed by the feedback circuit 310 of the resistor values to adjust the threshold voltage (FB) of the level of the embodiment, the threshold voltage level by the comparator circuit 322 and current sense signal ( I sense ) to compare. The output of comparison circuit 322 is coupled through OR logic gate 324 to the reset input (R) of flip flop 317. As shown in Figure 7, this causes MOSFET switch 316 to turn off when the current sense signal (I sense ) reaches the reference voltage (FB) (generating a voltage across Vds ).
再次參照第6圖,比較一週期性閾電壓(Vth)與一波谷偵測信號(VD)以產生具有一變動頻率的時序信號304,此信號被設定輸入(S)接收送至正反器317。波谷偵測電路306監測橫跨變壓器314之第三繞組的電壓,該變壓器第三繞組取樣橫跨MOSFET開關308之電壓(Vds)的形狀。波谷偵測電路306包含一RC網路,該RC網路經構形用以在Vds掉到一預設閾電壓以下時於其輸出(VD)上產生一脈衝,該預設閾電壓係由該RC網路中之電阻及電容值決定。週期性閾電壓(Vth)係由頻譜整形電路302及參考電路318產生。週期性閾電壓(Vth)的幾個可能實例例示於第10圖,且頻譜整形電路302之二個實例實施將在下文參照第11圖至第13圖說明。 Referring again to FIG. 6, a periodic threshold voltage ( Vth ) and a valley detection signal (VD) are compared to generate a timing signal 304 having a varying frequency, which is received by the set input (S) and sent to the flip-flop. 317. The valley detection circuit 306 monitors the voltage across the third winding of the transformer 314, which samples the shape of the voltage across the MOSFET switch 308 ( Vds ). The valley detecting circuit 306 includes an RC network configured to generate a pulse on the output (VD) of the Vds when the Vds falls below a predetermined threshold voltage, the predetermined threshold voltage is determined by the The value of the resistor and capacitor in the RC network is determined. The periodic threshold voltage ( Vth ) is generated by the spectral shaping circuit 302 and the reference circuit 318. Several possible examples of periodic threshold voltages ( Vth ) are illustrated in Figure 10, and two example implementations of spectral shaping circuit 302 will be described below with reference to Figures 11 through 13.
再次參照第6圖,頻譜整形電路302產生一頻譜整形信號(SS)以控制頻率變量。頻譜整形信號(SS)由參考電路318添加至一DC參考電壓以產生週期性閾電壓(Vth)。由參考電路318施加的該DC參考電壓舉例來說可為一0伏參考電壓或一正DC電壓譬如50毫伏。 Referring again to Figure 6, spectrum shaping circuit 302 produces a spectrally shaped signal (SS) to control the frequency variable. The spectral shaping signal (SS) is added by reference circuit 318 to a DC reference voltage to produce a periodic threshold voltage ( Vth ). The DC reference voltage applied by reference circuit 318 can be, for example, a zero volt reference voltage or a positive DC voltage, such as 50 millivolts.
第7圖是一例示第6圖所示切換模式電源供應300之實例運作的時序圖。第7圖之上部提供切換電路(Vds)及切換控制電路在時序信號(S)之二個脈衝期間的時序圖。第7圖之下部例示週期性閾電壓(Vth)及時序信號(S)在一段較長時間當中的實例。如圖所示,時序信號(S)之頻率依Vth之一函數變動。第7圖之上部例示的時序信號(S)二個脈衝在第7圖之下部中被圈出。 Fig. 7 is a timing chart showing an example of the operation of the switched mode power supply 300 shown in Fig. 6. The upper part of Fig. 7 provides a timing diagram of the switching circuit ( Vds ) and the switching control circuit during the two pulses of the timing signal (S). The lower part of Fig. 7 illustrates an example of the periodic threshold voltage ( Vth ) and the timing signal (S) over a long period of time. As shown, the frequency of the timing signal (S) varies as a function of Vth . The timing signal (S) exemplified in the upper part of Fig. 7 is circled in the lower part of Fig. 7.
第7圖之時序圖始於t0,此時MOSFET開關 316被接通導致電流流過變壓器312之初級繞組。通過初級繞組的電流隨著Cin被充電而加大,如電流感測信號(Isense)中之斜坡所例示。一旦電流感測信號(Isense)達到在t1反饋電路310所設定之閾值(FB),重設輸入(R)導致MOSFET開關316斷開。再次參照第6圖,延時電路326導致MOSFET開關316保持斷開達一段預設延遲時間(在此實例中為9微秒),這在第7圖中藉由重設信號(R)之斷開時間極限例示。 The timing diagram of FIG. 7 begins at t 0 , at which point MOSFET switch 316 is turned on causing current to flow through the primary winding of transformer 312. The current through the primary winding increases as Cin is charged, as exemplified by the slope in the current sense signal (I sense ). Once the current sense signal (I sense ) reaches the threshold (FB) set by the feedback circuit 310 at t 1 , resetting the input (R) causes the MOSFET switch 316 to open. Referring again to FIG. 6, delay circuit 326 causes MOSFET switch 316 to remain off for a predetermined delay time (9 microseconds in this example), which is broken by reset signal (R) in FIG. Time limit instantiation.
如第7圖所示,切換波形(Vds)在斷開期間包含一波谷400,該波谷係由因與MOSFET開關316之寄生電容共振所致的洩漏造成。當切換波形(Vds)中之波谷400低於閾值402通過,波谷偵測電路306導致一初始脈衝404在設定輸入(S)上發聲。但是,由於此初始脈衝404係在延時電路326之預設延遲期間發生,初始脈衝404不會導致Q輸出改變狀態(R具有高於S之優先權)。MOSFET開關316隨後在該時序信號之下一個前緣被設定輸入(S)再次接通,此係在第7圖之t2發生。 As shown in FIG. 7, the switching waveform ( Vds ) includes a valley 400 during the off period, which is caused by leakage due to resonance with the parasitic capacitance of the MOSFET switch 316. When the valley 400 in the switching waveform ( Vds ) passes below the threshold 402, the valley detecting circuit 306 causes an initial pulse 404 to sound on the set input (S). However, since this initial pulse 404 occurs during the preset delay of the delay circuit 326, the initial pulse 404 does not cause the Q output to change state (R has priority over S). MOSFET switch 316 is then set under a leading edge timing of the input signal (S) is switched on again, this system occurs at t 2 of FIG. 7.
第7圖中之時序參考點t2和t3分別例示在時序信號(S)之最高頻率及最低頻率的接通點。如圖所示,時序信號(S)之頻率改變由延時電路326設定之斷開時間極限與接通點(t2和t3)之間的距離。變壓器接通點的變動亦例示於第8圖所示切換波形(Vds)中。藉由加大切換頻率之帶寬,如第8圖所示,Vds的諧波增益減小導致系統EMI減小。所得Vds諧波增益減小之一實例例示於第9圖。第9圖所示之圖包含例示一典型切換模式電源供應中之Vds主要諧波的三條實線及例示第6圖實例中可能發生之諧波的三條點線。如圖所示,尖峰諧波減低,導致整體EMI減小。 The timing reference points t 2 and t 3 in Fig. 7 illustrate the turn-on points of the highest frequency and the lowest frequency of the timing signal (S), respectively. As shown, the frequency of the timing signal (S) changes the distance between the off time limit set by the delay circuit 326 and the turn-on point (t 2 and t 3 ). The variation of the transformer turn-on point is also exemplified in the switching waveform (V ds ) shown in FIG. By increasing the bandwidth of the switching frequency, as shown in Figure 8, the reduction in harmonic gain of Vds results in a reduction in system EMI. An example of the resulting V ds harmonic gain reduction is illustrated in Figure 9. The diagram shown in Fig. 9 includes three solid lines exemplifying the main harmonics of Vds in a typical switched mode power supply and three dotted lines exemplifying the harmonics that may occur in the example of Fig. 6. As shown, the peak harmonics are reduced, resulting in a reduction in overall EMI.
第11圖是一用於第6圖切換模式電源供應之 一實例頻譜整形電路302的簡圖。該頻譜整形電路包含一振盪器500、一位移暫存器502及一D/A轉換器504。此實例中之振盪器500係一電壓受控振盪器,其產生一具有一由一閾電壓(Vth)設定之固定頻率的時鐘輸出(CLK)。時鐘輸出(CLK)係用於驅動位移暫存器502並且為RS正反器317供應時鐘(圖中未示)。 Figure 11 is a simplified diagram of an example spectral shaping circuit 302 for a switched mode power supply of Figure 6. The spectrum shaping circuit includes an oscillator 500, a shift register 502, and a D/A converter 504. The oscillator 500 in this example is a voltage controlled oscillator that produces a clock output (CLK) having a fixed frequency set by a threshold voltage ( Vth ). The clock output (CLK) is used to drive the shift register 502 and supply a clock (not shown) to the RS flip-flop 317.
位移暫存器502包含一系列的D正反器(Q0-Q7),該等D正反器係由振盪器500之時鐘輸出(CLK)計時且經構形用以使每一時鐘脈衝通過該位移暫存器之一邏輯〝1〞位移。該位移暫存器之輸出(Q0-Q7)被輸入至一系列邏輯閘(OR2-OR0)以產生一個四位元數位控制字元,後者被D/A轉換器504轉化成一類比信號(SS)。經歷SS之一個循環的頻譜整形電路之一實例運作例示於第4圖。如第4圖所示,位移暫存器之每一時鐘(Q7-Q0)導致該D/A轉換器中之開關系列(S3-S0)加大SS之電流,產生一步進波形。此步進SS波形如第6圖所示被輸入至參考電路318以產生一週期性閾電壓(Vth)。 The shift register 502 includes a series of D flip-flops (Q0-Q7) that are clocked by the clock output (CLK) of the oscillator 500 and configured to pass each clock pulse through the One of the displacement registers is a logical 〝1〞 displacement. The output of the shift register (Q0-Q7) is input to a series of logic gates (OR2-OR0) to generate a four-bit digital control character that is converted by the D/A converter 504 into an analog signal (SS). . An example operation of a spectrum shaping circuit that undergoes one cycle of SS is illustrated in FIG. As shown in Fig. 4, each clock (Q7-Q0) of the shift register causes the switch series (S3-S0) in the D/A converter to increase the current of SS to generate a step waveform. This stepped SS waveform is input to reference circuit 318 as shown in FIG. 6 to generate a periodic threshold voltage ( Vth ).
第12圖是一用於第6圖切換模式電源供應之另一實例頻譜整形電路302的簡圖。該頻譜整形電路302包含一電壓受控振盪器600、一位移暫存器602及一D/A轉換器603。電壓受控振盪器600產生一由閾電壓(Vth)設定且驅動位移暫存器602的定頻時鐘信號(CLK)。在此實例中,位移暫存器602包含一系列的D正反器(Q0-Q7),該等D正反器經構形用以產生一串行輸出信號(G)。如第13圖所示,位移暫存器602每八個時鐘循環在串行輸出(G)上產生一單個脈衝。 Figure 12 is a simplified diagram of another example spectrum shaping circuit 302 for the switched mode power supply of Figure 6. The spectrum shaping circuit 302 includes a voltage controlled oscillator 600, a shift register 602, and a D/A converter 603. The voltage controlled oscillator 600 generates a fixed frequency clock signal (CLK) that is set by the threshold voltage ( Vth ) and drives the shift register 602. In this example, the shift register 602 includes a series of D flip-flops (Q0-Q7) that are configured to generate a serial output signal (G). As shown in Fig. 13, the shift register 602 generates a single pulse on the serial output (G) every eight clock cycles.
再次參照第12圖,來自位移暫存器602的串行輸出信號(G)係用於控制來自一D/A轉換器603之SS輸出。特定言之,D/A轉換器603包含一固定電流源(Ict1), 其充電由一充電電容器(Ct1)儲存的電壓。來自位移暫存器602的串行輸出信號(G)控制D/A轉換器603中之一開關(St1)以在每八個時鐘循環放電充電電容器(Ct1),在SS產生一鋸波輸出,如第13圖所示。 Referring again to Fig. 12, the serial output signal (G) from the shift register 602 is used to control the SS output from a D/A converter 603. In particular, D/A converter 603 includes a fixed current source (I ct1 ) that charges the voltage stored by a charging capacitor (C t1 ). The serial output signal (G) from the shift register 602 controls one of the switches (S t1 ) in the D/A converter 603 to discharge the charging capacitor (C t1 ) every eight clock cycles, and generates a saw wave in the SS. The output is shown in Figure 13.
以上說明利用實例揭示本發明,包含最佳模式,並且讓熟習此技藝者能夠製作及使用本發明。本發明之可專利範圍可包含熟習此技藝者想出的其他實例。 The above description of the present invention is intended to be illustrative of the invention, and is intended to The patentable scope of the invention may encompass other examples that are apparent to those skilled in the art.
CLK‧‧‧固定頻率的時鐘輸出 CLK‧‧‧ fixed frequency clock output
FB‧‧‧閾值 FB‧‧‧ threshold
ISENSE‧‧‧電流感測信號 ISENSE‧‧‧ current sensing signal
SS‧‧‧類比信號、頻譜整形信號 SS‧‧‧ analog signal, spectrum shaping signal
Vds‧‧‧電壓 Vds‧‧‧ voltage
100‧‧‧實例切換模式電源供應 100‧‧‧Instance switching mode power supply
102‧‧‧頻譜整形電路、時序電路 102‧‧‧Spectrum shaping circuit, sequential circuit
104‧‧‧整流器電橋 104‧‧‧Rectifier Bridge
106‧‧‧變壓器 106‧‧‧Transformers
108‧‧‧切換電路 108‧‧‧Switching circuit
110‧‧‧切換控制電路 110‧‧‧Switching control circuit
112‧‧‧RS正反器 112‧‧‧RS forward and reverse
114、116、118‧‧‧反饋電路 114, 116, 118‧‧‧ feedback circuit
120‧‧‧振盪器 120‧‧‧Oscillator
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US6249876B1 (en) * | 1998-11-16 | 2001-06-19 | Power Integrations, Inc. | Frequency jittering control for varying the switching frequency of a power supply |
US7208926B2 (en) * | 2003-11-20 | 2007-04-24 | Cosel Co., Ltd. | Switching signal modulation circuit |
US20090231894A1 (en) * | 2008-03-12 | 2009-09-17 | Moon Sang-Cheol | Power Converter and Driving Method Thereof |
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US6249876B1 (en) * | 1998-11-16 | 2001-06-19 | Power Integrations, Inc. | Frequency jittering control for varying the switching frequency of a power supply |
US7208926B2 (en) * | 2003-11-20 | 2007-04-24 | Cosel Co., Ltd. | Switching signal modulation circuit |
US20090231894A1 (en) * | 2008-03-12 | 2009-09-17 | Moon Sang-Cheol | Power Converter and Driving Method Thereof |
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