TWI474522B - Package structure and method of making same - Google Patents

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package, and more particularly to a semiconductor package having an electrical protective layer to improve yield.

With the rapid development of the electronics industry, electronic products tend to be light, thin and short in terms of type, and gradually become a high-performance, high-function, high-speed research and development direction in terms of functions. Among them, in a Light-Emitting Diode (LED) device, in order to avoid damage of static electricity, an ElectroStatic Discharge (ESD) structure is often provided.

In the current high-power LED package, in order to achieve the purpose of electrostatic protection, the LED chip is connected in anti-parallel with a Zener diode or a Schottky Diode to avoid static electricity to the LED chip. Damage. As shown in FIG. 1A, the Zener diode 13 is connected in anti-parallel with the LED chip 15. Generally, the Zener diode 13 is electrically connected to the LED chip 15 by wire bonding. However, the Zener diode 13 or the Schottky diode has a small volume (about 6 mils), so that it is difficult to wire. Process, resulting in poor production capacity and yield.

U.S. Patent No. 7,768,754 provides another LED package having ESD protection, as shown in Fig. 1B, forming a zinc oxide (ZnO) layer 13' in a substrate 10, and then on the upper surface 10a of the substrate 10. The circuit layer 11 is covered with the LED chip 15 and finally encapsulated with the encapsulant 16 to expose the electrical contact pads 12 on the lower surface 10b of the substrate 10. The substrate 10 has conductive vias 14 electrically connected to the circuit layer 11, the electrical contact pads 12 and the zinc oxide layer 13'.

In the conventional LED package, the Zener diode or the Schottky diode is replaced by the zinc oxide layer 13' to avoid the wire bonding process on the Zener diode or the Schottky diode. The zinc oxide layer 13' is built in the substrate 10. When the electrical contact pad 12 is connected to the power source 17, the zinc oxide layer 13' and the LED chip 15 will be in parallel, as shown in FIG. 1B'. It is shown that the purpose of avoiding damage to the LED chip 15 by static electricity can be achieved.

However, in the conventional LED package, the main material of the substrate 10 is a binder, and zinc oxide particles are incorporated into the colloid. This process is too complicated, resulting in an increase in process time, thereby greatly increasing the cost.

Therefore, how to avoid the various problems of the above-mentioned prior art is the current goal to be solved.

In order to overcome the problems of the prior art, the present invention provides a semiconductor package comprising: a substrate having opposite first and second surfaces; a first circuit layer formed on the first surface of the substrate; formed on the substrate And electrically connecting the second circuit layer of the first circuit layer on the second surface, and the second circuit layer has a plurality of electrical contact pads; formed on the second surface of the substrate and electrically connected to the second circuit An electrical protection layer of the layer; a wafer disposed on the first surface of the substrate, electrically connected to the first circuit layer to electrically conduct to the second circuit layer; and an encapsulant formed on the substrate The first surface and the first circuit layer are coated to cover the wafer, and the electrical contact pads are exposed.

The method of manufacturing the semiconductor package of the present invention comprises: providing a substrate having a first surface and a second surface; forming an electrical protective layer on a portion of the second surface of the substrate; forming a first circuit layer Forming a second circuit layer on a portion of the second surface of the substrate and electrically connecting the second protective layer to the second surface of the substrate, wherein the first and second circuit layers are electrically connected to each other by a conductive path Connecting, the second circuit layer has a plurality of electrical contact pads; the wafer is disposed on the first surface of the substrate, and electrically connecting the wafer and the first circuit layer to electrically conduct the wafer to the second line And forming an encapsulant on the first surface of the substrate and the first circuit layer to encapsulate the wafer and exposing each of the electrical contact pads.

In the foregoing semiconductor package and the method of manufacturing the same, the electrical protective layer can be used as an ESD structure, and the material thereof can be a metal oxide such as zinc oxide.

In the foregoing semiconductor package and method of fabricating the same, the substrate may have a conductive layer on a side thereof to serve as a conductive path for electrically connecting the first and second circuit layers.

In another aspect, the substrate has a groove on the first surface, so that the wafer is disposed on the bottom surface of the groove, and the substrate may have a connection between the bottom of the groove and the second surface. A hole and a conductive via formed in the through hole serve as a conductive path.

As can be seen from the above, the semiconductor package of the present invention has an electrical protective layer disposed on the second surface of the substrate, and the encapsulant is exposed, so that it does not need to be incorporated or formed in the substrate. The invention can greatly reduce the cost by incorporating the technology into the process.

Moreover, when the power is connected to the electrical contact pads, the electrical protection layer and the wafer will be in parallel to achieve the ESD electrostatic protection effect, so there is no need to set the Zener diode or the Schottky II. The polar body does not need to be subjected to a wire bonding process on the Zener diode or the Schottky diode, thereby enabling the present invention to increase productivity and yield.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "left", "right", "bottom", "side" and "one" are used in this specification for convenience of description and are not intended to limit the invention. The scope, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.

First embodiment

Please refer to FIGS. 2A to 2E, which are schematic cross-sectional views showing the manufacturing method of the first embodiment of the semiconductor package of the present invention.

As shown in FIG. 2A, firstly, a substrate 20 having a first surface 20a and a second surface 20b is defined. The first surface 20a defines a seeding portion M. Then, through a patterning process, sputtering is performed. An electrical protective layer 23 is formed on a portion of the second surface 20b of the substrate 20 by vapor deposition or chemical vapor deposition.

In this embodiment, the substrate 20 has a side surface 20c adjacent to the first and second surfaces 20a, 20b, as shown in the left and right sides 20c (which may also include front and rear sides). The side surface), and the material of the substrate and the patterning process described above are well known in the art, and therefore will not be described again.

Furthermore, the electrical protective layer 23 is a varistor made of a metal oxide, and a zinc oxide (ZnO) film (about 0.3 um thick) is used as an example for parallel connection with the LED elements.

As shown in FIG. 2B, a first wiring layer 21 is formed on the first surface 20a other than the crystallizing portion M by a patterning process, and a second wiring layer 22 is formed on the electrical protection layer 23 by electroplating. The second surface 20b is electrically connected to the electrical protection layer 23, and the conductive layer 24 may be electroplated on the side surfaces 20c to form a conductive layer across the substrate 20. 23. The first and second circuit layers 21, 22 are electrically connected to each other by the conductive layer 24.

In the embodiment, the second circuit layer 22 has a plurality of electrical contact pads 220, and the conductive layer 24, the first and second circuit layers 21, 22 are integrally formed.

In other embodiments, the conductive path may also be a conductive via 24' extending through the substrate 20, as shown in FIG. 2B'.

As shown in FIG. 2C, a wafer 25 is disposed on the crystallized portion M by the adhesive layer 250, and the wafer 25 is electrically connected to the first portion by wire bonding (wire 251 made of gold (Au) material). The circuit layer 21 electrically connects the wafer 25 to the second circuit layer 22. Of course, the wafer 25 can also be provided in a flip chip manner.

In the embodiment, the wafer 25 is a Light-Emitting Diode (LED) wafer.

As shown in FIG. 2D, the encapsulant 26 is formed on the first surface 20a of the substrate 20, the first wiring layer 21, and the conductive layer 24 to cover the wafer 25, and the electrical protective layer 23 is exposed. Two circuit layers 22 and each of the electrical contact pads 220.

As shown in FIG. 2E, when a power source 27 is connected to the electrical contact pads 220, the electrical protection layer 23 and the wafer 25 will be in a parallel state.

Under normal operation, the voltage is about 3.3 V. At this time, the varistor operates in the leakage current region. When the resistance of the varistor is extremely large (about 10 ^12~13 Ω), it can be regarded as an open circuit, so the current will flow through the LED element.

However, when high-voltage static electricity is generated, when the voltage suddenly increases (beyond the breakdown voltage of the varistor) and enters the non-ohmic region, the impedance of the varistor becomes low (only a few ohms), and according to the law, the current will be low impedance. The place is flowing, so high-voltage static electricity will flow through the varistor, and thus the LED element is electrostatically protected.

In the method of the present invention, the electrical protection layer 23 is disposed on the second surface 20b of the substrate 20 and exposed to the encapsulant 26, so that the electrical protection layer 23 is not disposed in the substrate 20, The invention can greatly reduce the cost by the incorporation process of the prior art.

Furthermore, when the power source 27 is connected, if the voltage is forward biased, the electrical protection layer 23 is not electrically conductive; if an electrostatic voltage is generated, current flows from the negative electrode to the positive electrode via the electrical protection layer 23 to achieve The effect of ESD protection. Therefore, compared with the prior art, the Zener diode or the Schottky diode is provided, and the present invention does not need to perform a wire bonding process on the Zener diode or the Schottky diode, thereby making the process of the present invention simple. Not only reduces process time, but also increases productivity and yield.

Second embodiment

Please refer to FIGS. 3A to 3D, which are a manufacturing method of a second embodiment of the semiconductor package of the present invention. The difference between the second embodiment and the first embodiment is that the structure of the substrate is different, and other related processes are substantially the same, so the same process will not be described again.

As shown in FIG. 3A, the substrate 30 has a recess 300 on the first surface 30a. In this embodiment, a through hole 301 is formed in the substrate 30 to communicate with the bottom surface 300a of the recess 300. The second surface 30b of the substrate 30 is located on a portion of the bottom surface 300a of the recess 300, and the through hole 301 is located around the crystal M.

Next, an electrical protective layer 33 having a thickness of about 0.3 um is formed on a portion of the second surface 30b of the substrate 30, for example, on the edge of the second surface 30b of the substrate 30.

As shown in FIGS. 3B and 3B', a second circuit layer 32 is formed on the second surface 30b other than the electrical protection layer 33, and the second circuit layer 32 is electrically connected to the electrical protection layer 33, and A conductive via 34 is formed in the via 301 as a conductive path; a first wiring layer 31 is formed on the wall surface 300b of the recess 300 and a portion of the bottom surface 300a, and the first wiring layer 31 is electrically conductive. The hole 34 is electrically connected to the second circuit layer 32, and a crystal pad 310 can be formed on the crystal M.

Furthermore, the second circuit layer 32 has an electrical contact pad 320 and a heat dissipation pad 321 , and the material of the second circuit layer 32 is made of titanium (Ti)/gold (Au).

Moreover, in other embodiments, the conductive path may also be a conductive layer formed on a side of the substrate 30 (as in the first embodiment).

As shown in FIG. 3C, a wafer 35 is disposed on the crystal pad 310 by the adhesive layer 350, and the wafer 35 is electrically connected to the first circuit layer 31 by wires 351.

As shown in FIG. 3D, an encapsulant 36 is formed in the recess 300 to cover the wafer 35, the wires 351, the pad 310, and the first wiring layer 31.

In the embodiment, the encapsulant 36 can be coated by phosphor coating, phosphor dispensing, silicone dispensing, lens molding, etc. The process is formed.

Further, a thermal interface material (TIM) may be formed on the heat dissipation pad 321 as a heat dissipation layer 38.

As shown in FIGS. 3E and 3E', when a power source 37 is connected to the electrical contact pads 320, the electrical protection layer 33 and the wafer 35 will be in a parallel state. When the voltage is forward biased, the voltage is low at this time. Therefore, the electrical protective layer 33 is electrically non-conductive, and current flows from the positive electrode of the wafer 35 to the negative electrode to cause the wafer 35 to emit light. When an electrostatic voltage occurs, the voltage is high at this time, so the electrical protection layer 33 is low impedance, and current flows from the negative electrode of the electrical protection layer 33 to the positive electrode, and the high voltage is prevented from damaging the wafer 35 to protect the wafer 35. The effect.

In summary, the semiconductor package of the present invention is formed by disposing an electrical protective layer on the second surface of the substrate and exposing the encapsulant, thereby eliminating the need to provide an electrical protective layer in the substrate. And can significantly reduce costs.

Moreover, by using the electrical protection layer in parallel with the wafer in use, the ESD electrostatic protection effect can be achieved, and thus the wire bonding process is not required on the Zener diode or the Xiaojiji diode, thereby effectively increasing the productivity. And yield.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10,20,30. . . Substrate

10a. . . Upper surface

10b. . . lower surface

11. . . Circuit layer

12,220,320. . . Electrical contact pad

13. . . Zener diode

13’. . . Zinc oxide layer

14,24’, 34. . . Conductive through hole

15. . . LED chip

16,26,36. . . Encapsulant

17,27,37. . . power supply

20a, 30a. . . First surface

20b, 30b. . . Second surface

20c. . . side

21,31. . . First circuit layer

22,32. . . Second circuit layer

23,33. . . Electrical protective layer

twenty four. . . Conductive layer

25,35. . . Wafer

250,350. . . Adhesive layer

251,351. . . wire

300. . . Groove

300a. . . Bottom

300b. . . Wall

301. . . Through hole

310. . . Crystal pad

321. . . Cooling pad

38. . . Heat sink

M. . . Crystallization

1A is a schematic circuit diagram of a conventional LED element and a Zener diode;

1B is a schematic cross-sectional view of a conventional semiconductor package;

The 1B' diagram is a schematic diagram of the circuit of Figure 1B;

2A to 2E are schematic cross-sectional views showing a process of the first embodiment of the semiconductor package of the present invention; wherein the 2B' is another embodiment of the 2B chart;

3A to 3E are schematic cross-sectional views showing a method of fabricating a second embodiment of the semiconductor package of the present invention; wherein, the 3B' is a bottom view of FIG. 3B, and the 3E' is a circuit diagram of FIG. 3E. .

20. . . Substrate

twenty one. . . First circuit layer

220. . . Electrical contact pad

twenty three. . . Electrical protective layer

twenty four. . . Conductive layer

25. . . Wafer

26. . . Encapsulant

27. . . power supply

Claims (25)

A semiconductor package comprising: a substrate having opposite first and second surfaces; a first circuit layer formed on a portion of the first surface of the substrate; and a second circuit layer formed on the substrate a portion of the second surface and having a plurality of electrical contact pads; a conductive path electrically connecting the first and second circuit layers; and an electrical protective layer formed on a portion of the second surface of the substrate and electrically connected The second circuit layer is disposed on the first surface of the substrate and electrically connected to the first circuit layer to electrically conduct to the second circuit layer; and the encapsulant is formed on the substrate The first surface and the first circuit layer are coated to cover the wafer, and each of the electrical contact pads is exposed. The semiconductor package of claim 1, wherein the material of the electrical protective layer is a metal oxide. The semiconductor package of claim 1, wherein the wafer is electrically connected to the first circuit layer by wire bonding or flip chip. The semiconductor package of claim 1, wherein the wafer is a light emitting diode wafer. The semiconductor package of claim 1, wherein the conductive path is through the conductive via of the substrate. The semiconductor package of claim 1, wherein the substrate has a side adjacent to the first and second surfaces, and the conductive path is formed on the conductive layer on the side. The semiconductor package of claim 6, wherein the encapsulant is formed on the conductive layer. The semiconductor package of claim 5 or 6, wherein the substrate has a recess on the first surface, and the wafer is disposed on a bottom surface of the recess, and the first circuit layer The complex is formed on a part of the bottom surface of the groove. The semiconductor package of claim 8, wherein the encapsulant system is formed in the recess. The semiconductor package of claim 1, further comprising a pad placed on the first surface of the substrate to set the wafer. The semiconductor package of claim 1, further comprising a heat dissipation layer disposed on the second circuit layer. The semiconductor package of claim 1, further comprising a power source electrically connecting the electrical contact pads to connect the electrical protection layer in parallel with the wafer. A method of fabricating a semiconductor package, comprising: providing a substrate having a first surface and a second surface; forming an electrical protective layer on a portion of the second surface of the substrate; forming a portion of the first wiring layer on the substrate Forming a second circuit layer on a portion of the second surface of the substrate and electrically connecting the electrical protection layer, the first and second circuit layers are electrically connected to each other by a conductive path, and The second circuit layer has a plurality of electrical contact pads; the wafer is disposed on the first surface of the substrate, and electrically connected to the first circuit layer to electrically electrically connect the wafer to the second circuit layer; and form The encapsulant is on the first surface of the substrate and the first circuit layer to encapsulate the wafer, and each of the electrical contact pads is exposed. The method of fabricating a semiconductor package according to claim 13, wherein the material of the electrical protective layer is a metal oxide. The method of fabricating a semiconductor package according to claim 13 , wherein the wafer is electrically connected to the first circuit layer by wire bonding or flip chip. The method of fabricating a semiconductor package according to claim 13, wherein the wafer is a light emitting diode wafer. The method of fabricating a semiconductor package according to claim 13 , wherein the conductive path is through the conductive via of the substrate. The method of fabricating a semiconductor package according to claim 13 , wherein the substrate has a side adjacent to the first and second surfaces, and the conductive path is a conductive layer formed on the side. The method of fabricating a semiconductor package according to claim 18, wherein the conductive layer, the first and second circuit layers are integrally formed. The method of fabricating a semiconductor package according to claim 18, wherein the encapsulant is formed on the conductive layer. The method of manufacturing the semiconductor package of claim 17 or 18, wherein the substrate has a recess on the first surface, and the wafer is disposed on a bottom surface of the recess, and the A circuit layer is formed on a portion of the bottom surface of the recess. The method of fabricating a semiconductor package according to claim 21, wherein the encapsulant system is formed in the recess. The method of fabricating a semiconductor package according to claim 13 further comprising forming a pad on the first surface of the substrate for providing the wafer. The method of fabricating a semiconductor package according to claim 13 further comprising forming a heat dissipation layer on the second circuit layer. The method for manufacturing a semiconductor package according to claim 13 is characterized in that after forming the encapsulant, a power source is connected to the electrical contact pads to connect the electrical protection layer in parallel with the wafer.