TWI473212B - Integrated circuit structure and method for manufacturing the same - Google Patents

Description

Integrated circuit structure and manufacturing method thereof

The present invention relates to an integrated circuit structure and a method of fabricating the same, and more particularly to an integrated circuit structure that can integrate a Schottky diode and a method of fabricating the same.

In the integrated circuit industry, metal semiconductor contact diodes are one of the most important basic components in electronic systems. In particular, the Schottky diode has the characteristics of fast switching speed, small conduction voltage drop and low noise index, so it can be widely used in power supply switch, motor control, telecommunication switch, electronic automation. Wait.

In the past, the integrated circuit industry utilized various methods and structures to form Schottky diodes. The Schottky diode is a surface contact diode composed of a lightly doped semiconductor layer and a metal layer, which utilizes a work function difference between the two to achieve rectification.

Moreover, a Schottky diode is typically fabricated on a wafer, and then the Schottky diode is combined with other semiconductor components on another wafer by designing and assembling steps.

However, with the rapid development of the integrated circuit process, the size of the components is constantly shrinking, and it is desirable to integrate the Schottky diode and other semiconductor components on the same wafer to improve the integration of the integrated circuits.

Therefore, how to integrate the Schottky diode into the integrated circuit process and form the required Schottky diode with good characteristics without adversely affecting other semiconductor components has become a positive development. One of the goals.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of fabricating an integrated circuit structure capable of integrating a diode-to-integral circuit process and forming a diode of desired good characteristics without affecting other semiconductor components.

Another object of the present invention is to provide an integrated circuit structure which has good element characteristics and can be formed on the same wafer as other semiconductor elements.

The present invention proposes a method of fabricating an integrated circuit structure. In this method, a substrate is provided first, and the substrate has a transistor region and a diode region. A dielectric layer is then formed on the substrate. Next, contact holes and openings are simultaneously formed in the dielectric layer. Wherein, the bottom of the contact hole exposes a portion of the substrate of the transistor region, and the bottom portion of the opening exposes a portion of the substrate of the diode region. Moreover, the size of the opening is larger than the size of the contact hole. Subsequently, a first metal layer is formed to cover the dielectric layer, and the first metal layer fills the contact holes and the openings. Subsequently, a portion of the first metal layer is removed to form a contact plug in the transistor region, and at the same time a metal spacer is formed in the sidewall of the opening. Then, an ion implantation process is performed with the metal spacer as a mask to form a lightly doped region in the substrate at the bottom of the opening. Next, a contact metal layer is formed on the lightly doped region.

In a preferred embodiment of the invention, a barrier layer may be formed to conformally cover the dielectric layer prior to forming the first metal layer. The material of the barrier layer is, for example, titanium, titanium nitride, tantalum, and tantalum nitride. In another embodiment, the forming of the contact metal layer further includes removing a portion of the barrier layer on the dielectric layer. In still another embodiment, when removing a portion of the first metal layer, it further includes removing a portion of the barrier layer.

In a preferred embodiment of the invention, between the contact metal layer and the lightly doped region, a buffer layer is further formed.

In a preferred embodiment of the present invention, the method for forming the contact metal layer is, for example, first conformally forming a second metal layer on the dielectric layer, and then patterning the second metal layer to form a contact metal layer. The material of the second metal layer is different from the material of the first metal layer, and the material of the second metal layer is, for example, aluminum, copper, molybdenum, gold, platinum, or an alloy thereof. In addition, when the second metal layer is patterned, wires can be formed on the contact plug at the same time.

In a preferred embodiment of the present invention, the material of the first metal layer is, for example, tungsten, copper, molybdenum, gold, platinum, or an alloy thereof.

The present invention proposes an integrated circuit structure. The structure includes a substrate, a dielectric layer, a contact window plug, a metal spacer, a lightly doped region, and a contact metal layer. Wherein, the substrate has a transistor region and a diode region. The dielectric layer is disposed on the substrate, and the dielectric layer has contact holes and openings therein, and the size of the openings is larger than the size of the contact holes. The contact hole and the opening respectively expose a part of the substrate of the transistor region and the diode region. In addition, the contact window plug is disposed in the contact hole of the dielectric layer. A metal spacer is disposed on a sidewall of the opening of the dielectric layer. The lightly doped region is disposed in the substrate at the bottom of the opening that is not covered by the metal spacer, and the edge of the lightly doped region is aligned with the edge of the metal spacer. The contact metal layer is disposed on the lightly doped region and is in contact with the lightly doped region.

In a preferred embodiment of the invention, the structure further includes a barrier layer disposed at least on the surface of the contact hole and at least between the metal spacer, the substrate and the dielectric layer. The material of the barrier layer is, for example, titanium, titanium nitride, tantalum, and tantalum nitride.

In a preferred embodiment of the present invention, the above structure may further include a buffer layer disposed between the contact metal layer and the lightly doped region.

In a preferred embodiment of the invention, the above structure may further comprise a wire disposed on the contact window plug. The wire is made of the same material as the contact metal layer, and is made of, for example, aluminum, copper, molybdenum, gold, platinum, or an alloy thereof.

In a preferred embodiment of the present invention, the contact window plug is made of the same material as the metal spacer, and is made of, for example, tungsten, copper, molybdenum, gold, platinum, or an alloy thereof.

In the method of the present invention, the contact hole and the opening of a larger size are simultaneously formed, and the bottom of the opening is used as the junction of the diode. Moreover, in the subsequent process of forming the contact window, a contact metal layer and a lightly doped region are formed above and below the bottom of the opening to form a Schottky diode. Therefore, the present invention can integrate the Schottky diode into the integrated circuit process, which not only saves the cost of design and assembly, but also improves the integration of components.

In addition, the present invention does not require the use of a mask, and the metal spacer can be used as a mask for the ion implantation process to form a lightly doped region at the bottom of the opening. Moreover, by controlling the process conditions of the ion implantation process, a desired diode having good characteristics can be formed without adversely affecting other semiconductor elements.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1A-1F are cross-sectional views showing a manufacturing process of an integrated circuit structure according to an embodiment of the invention.

Referring to FIG. 1A, the manufacturing method of the integrated circuit structure is, for example, first providing a substrate 100 having a transistor region 102 and a diode region 104. The substrate 100 of the transistor region 102 is provided with a general logic component such as a MOS component or a memory component (not shown). In addition, the substrate 100 may also be formed with an inner dielectric layer or a metal interlayer dielectric layer (not shown), the number of layers and the configuration being designed according to the requirements of the components.

Subsequently, a dielectric layer 106 is formed on the substrate 100. The material of the dielectric layer 106 is, for example, ruthenium oxide, and the formation method thereof is, for example, a chemical vapor deposition method.

Next, referring to FIG. 1B, the dielectric layer 106 is patterned to simultaneously form the contact hole 108 and the opening 110, and the size of the opening 110 is larger than the size of the contact hole 108. The bottom of the contact hole 108 is a portion of the substrate 100 exposing the transistor region 102, which is, for example, a conductive element that exposes a gate, a source/drain region or an interconnect of a logic element. The bottom of the opening 110 is a portion of the substrate 100 exposing the diode region 104, and the bottom surface of the opening 110 serves as the junction of the subsequently preformed metal semiconductor contact diode.

In addition, the method of patterning the dielectric layer 106 is, for example, forming a patterned photoresist layer (not shown) on the dielectric layer 106 to expose a portion of the dielectric layer 102 and the dielectric layer of the diode region 104. 106. Thereafter, the exposed photoresist layer 106 is removed by using the patterned photoresist layer as a mask to form the contact hole 108 and the opening 110. The method of removing the exposed dielectric layer 106 is, for example, a dry etching method or a wet etching method.

Then, referring to FIG. 1C, a metal layer 112 is formed over the substrate 100. The metal layer 112 covers the dielectric layer 106 and fills the contact hole 108 and the opening 110. The material of the metal layer 112 is, for example, tungsten, copper, molybdenum, gold, platinum, or an alloy thereof, and the method of forming the metal layer 112 is, for example, a chemical vapor deposition method.

In an embodiment, a barrier layer 111 may be further formed before the formation of the metal layer 112 to block the interdiffusion between the metal and the germanium. The material of the barrier layer 111 is, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, titanium tungsten nitride, nickel, zinc, zinc nitride, chromium or chromium nitride, etc., and the formation method thereof is, for example, chemistry. Vapor deposition method.

Then, referring to FIG. 1D, a portion of the metal layer 112 is removed, leaving a portion of the metal layer 112 in the contact hole 108 of the transistor region 102 to form the contact window plug 113a. In addition, since the size of the opening 110 is larger than the size of the contact hole 108, not only the contact plug 113a but also the metal spacer 113b is formed on the side wall of the opening 110 after the partial metal layer 112 is removed.

In the above, the method of removing a part of the metal layer 112 is performed by, for example, an etch back method or a chemical mechanical polishing method followed by an etch back method.

It should be noted that when a part of the metal layer 112 is removed, the barrier layer 111 in the opening 110 may be left, or a part of the barrier layer 111 in the opening 110 may be removed together, depending on the requirements of the component. .

Subsequently, referring to FIG. 1E, the ion implantation process 114 is performed with the metal spacer 113b as a mask to form the lightly doped region 116 in the diode region 104. In detail, the lightly doped region 116 is formed in the substrate 100 which is not covered by the metal spacer 113b at the bottom of the opening 110.

It is worth mentioning that by using the metal spacer 113b as a hard mask, the dopant can be implanted in the substrate 100 at the bottom of the opening 110 to form the lightly doped region 116 without additionally using a mask. In addition, in this step, the process conditions of the ion implantation process 114 can be directly controlled to form a desired diode having good characteristics without adversely affecting other semiconductor elements.

Next, referring to FIG. 1F, a contact metal layer 118 is formed on the lightly doped region 116. However, when the contact metal layer 118 is formed, it further includes removing a portion of the barrier layer 111 on the dielectric layer 106. In particular, the contact metal layer 118 and the lightly doped region 116 underneath thereof may constitute a Schottky diode, which is a so-called metal semiconductor contact diode.

The method for forming the contact metal layer 118 is formed by forming a metal layer 119, covering the entire wafer, and then patterning the metal layer 119 to form a contact metal layer 118 in the opening 110 of the diode region 104. Moreover, when the metal layer 119 is patterned, the wires 120 may be simultaneously formed on the contact plug 113a of the transistor region 102. The material of the metal layer 119 is different from the material of the metal layer 112, and is, for example, aluminum, copper, molybdenum, gold, platinum, or an alloy thereof, or an aluminum-niobium alloy. The method of forming the metal layer 119 is, for example, a physical vapor deposition method or a chemical vapor deposition method.

In an embodiment, a buffer layer 122 may also be formed between the contact metal layer 118 and the lightly doped region 116 to avoid cross-diffusion between the metal and the germanium to cause contamination problems. A buffer layer 122 may also be formed between the wire 120 and the contact window plug 113a. The material of the buffer layer 122 is, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, titanium tungsten nitride, nickel, zinc, zinc nitride, chromium or chromium nitride. The buffer layer 122 is formed by, for example, forming a buffer material layer (not shown) by chemical vapor deposition before forming the metal layer 119, and then removing a portion of the buffer material layer when the metal layer 119 is patterned. To form it. Of course, the buffer layer 122 can be selectively disposed depending on the component requirements.

According to the method of the present invention, the fabrication of the Schottky diode can be simultaneously performed in the process of forming the contact window. That is, the Schottky diode can be integrated into the integrated circuit process so that the Schottky diode can be formed on the same wafer as the general logic components.

In this way, the method of the present invention can not only save the cost of design and assembly, but also greatly improve the integration of components.

In particular, the method of the present invention can adjust the ion implantation process conditions to form the desired diode without additional use of a mask without affecting the efficiency of other semiconductor components.

Next, an integrated circuit structure of an embodiment of the present invention will be described with reference to Fig. 1F. As for the detailed method and material for forming the structure, it will be described in detail above, and will not be described below.

Referring again to FIG. 1F, the integrated circuit structure includes a substrate 100, a dielectric layer 106, a contact window plug 113a, a metal spacer 113b, a lightly doped region 116, and a metal contact layer 118. The substrate 100 has a transistor region 102 and a diode region 104.

The dielectric layer 106 is disposed on the substrate 100, and the dielectric layer 106 has contact holes 108 and openings 110 therein, and the size of the openings 110 is larger than the size of the contact holes 108. Wherein, the bottom of the contact hole 108 exposes a portion of the substrate 100 of the transistor region 102, and the bottom portion of the opening 110 exposes a portion of the substrate 100 of the diode region 104.

A metal spacer 113b is provided on the side wall of the opening 110, and a contact plug 113a is provided in the contact hole 108. The metal spacer 113b is made of the same material as the contact plug 113a and is formed at the same time.

In an embodiment, at least the barrier layer 111 may be disposed on the surface of the contact hole 108, and at least the barrier layer 111 may be disposed between the metal spacer 113b and the substrate 100 and the dielectric layer 106. The barrier layer 111 blocks the interaction between the metal and the crucible.

In addition, the lightly doped region 116 and the contact metal layer 118 constitute a Schottky diode. The lightly doped region 116 is disposed in the substrate 100 at the bottom of the opening 110, and the lightly doped region 116 is not covered by the metal spacer 113b, and the edge of the lightly doped region 116 is aligned with the edge of the metal spacer 113b. The contact metal layer 118 is disposed on the lightly doped region 116 and is in contact with the lightly doped region 116. The material of the contact metal layer 118 is different from the material of the metal spacer 113b.

In another embodiment, the wire 120 is disposed on the contact plug 113a, and the wire 120 is made of the same material as the contact metal layer 118 and is formed at the same time.

In addition, a buffer layer 122 may be disposed between the contact metal layer 118 and the lightly doped region 116, and a buffer layer 122 may be disposed between the wire 120 and the contact window plug 113a. The function of the buffer layer 122 is also to block the interaction between the metal and the crucible.

In summary, the present invention can integrate the Schottky diode into the integrated circuit process to save process cost and improve component accumulation. Moreover, by adjusting the ion implantation process conditions without the need for an additional mask, the desired diode can be formed without affecting the efficiency of other semiconductor components.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100. . . Base

102. . . Transistor region

104. . . Dipolar region

106. . . Dielectric layer

108. . . Contact hole

110. . . Opening

111. . . Barrier layer

112, 119. . . Metal layer

113a. . . Contact window plug

113b. . . Metal spacer

114. . . Ion implantation process

116. . . Lightly doped area

118. . . Contact metal layer

120. . . wire

122. . . The buffer layer

1A-1F are cross-sectional views showing a manufacturing process of an integrated circuit structure according to an embodiment of the invention.

100‧‧‧Base

102‧‧‧Optocrystalline area

104‧‧‧Dipolar Region

106‧‧‧Dielectric layer

108‧‧‧Contact hole

110‧‧‧ openings

111‧‧‧Barrier layer

113a‧‧‧Contact window plug

113b‧‧‧Metal spacer

114‧‧‧Ion implantation process

116‧‧‧Lightly doped area

Claims (20)

A method of fabricating an integrated circuit structure, comprising: forming a dielectric layer on a substrate, wherein the substrate has a transistor region and a diode region; and the dielectric region and the diode region A contact hole and an opening exposing a portion of the substrate are simultaneously formed in the electrical layer, wherein the opening has a size larger than a size of the contact hole; forming a first metal layer covering the dielectric layer and filling the contact a hole and the opening; removing a portion of the first metal layer to form a contact plug in the contact hole of the dielectric layer, and simultaneously forming a metal spacer on a sidewall of the opening of the dielectric layer; Using the metal spacer as a mask, an ion implantation process is performed to form a lightly doped region in the substrate at the bottom of the opening not covered by the metal spacer, and the edge of the lightly doped region An edge of the metal spacer is aligned; and a contact metal layer in contact with the lightly doped region is formed on the lightly doped region. The method of manufacturing the integrated circuit structure of claim 1, wherein before forming the first metal layer, further comprising: forming a barrier layer conformally covering the dielectric layer. The method of fabricating an integrated circuit structure according to claim 2, wherein when the contact metal layer is formed, the removing of a portion of the barrier layer on the dielectric layer is further included. The method of manufacturing an integrated circuit structure according to claim 2, wherein when the portion of the first metal layer is removed, the portion of the barrier layer is further removed. The manufacturer of the integrated circuit structure as described in claim 2 The method, wherein the material of the barrier layer comprises titanium, titanium nitride, tantalum and tantalum nitride. The method of fabricating an integrated circuit structure according to claim 1, wherein a buffer layer is further formed between the contact metal layer and the lightly doped region. The method for fabricating an integrated circuit structure according to claim 1, wherein the method for forming the contact metal layer comprises: forming a second metal layer on the dielectric layer in compliance; and patterning the second A metal layer to form the contact metal layer. The method of manufacturing the integrated circuit structure of claim 7, wherein the patterning the second metal layer further comprises: simultaneously forming a wire on the contact window plug. The method of manufacturing an integrated circuit structure according to claim 7, wherein the second metal layer is different in material from the first metal layer. The method for manufacturing an integrated circuit structure according to claim 7, wherein the material of the second metal layer comprises aluminum, copper, molybdenum, gold, platinum, and alloys thereof. The method for manufacturing an integrated circuit structure according to claim 1, wherein the material of the first metal layer comprises tungsten, copper, molybdenum, gold, platinum, and alloys thereof. An integrated circuit structure comprising: a substrate having a transistor region and a diode region; a dielectric layer disposed on the substrate, the dielectric layer having a contact hole and an opening to Exposing the portion of the crystal region and the portion of the diode region respectively, wherein the opening has a size larger than a size of the contact hole; a contact window plug is disposed in the contact hole of the dielectric layer; a metal a spacer disposed on a sidewall of the opening of the dielectric layer; a lightly doped region disposed in the substrate at the bottom of the opening not covered by the metal spacer, and an edge of the lightly doped region is aligned with an edge of the metal spacer; and a contact metal layer is disposed on The lightly doped region is in contact with the lightly doped region. The integrated circuit structure of claim 12, further comprising a barrier layer disposed at least on the contact hole surface, and at least disposed between the metal spacer, the substrate and the dielectric layer. The integrated circuit structure of claim 13, wherein the material of the barrier layer comprises titanium, titanium nitride, tantalum and tantalum nitride. The integrated circuit structure of claim 12, further comprising a buffer layer disposed between the contact metal layer and the lightly doped region. The integrated circuit structure of claim 12, further comprising a wire disposed on the contact plug. The integrated circuit structure of claim 16, wherein the wire is made of the same material as the contact metal layer. The integrated circuit structure of claim 16, wherein the material of the wire and the contact metal layer comprises aluminum, copper, molybdenum, gold, platinum and alloys thereof. The integrated circuit structure according to claim 12, wherein the contact window plug is made of the same material as the metal spacer. The integrated circuit structure of claim 19, wherein the material of the contact plug and the metal spacer comprises tungsten, copper, molybdenum, gold, platinum and alloys thereof.