TWI813294B - Semiconductor structure and methods for manufacturing the same - Google Patents

Abstract

A semiconductor structure includes a substrate, several gate structures formed in the substrate, dielectric portions formed on the respective gate structures, spacers adjacent to and extending along the sidewalls of the dielectric portions, source regions formed between the substrate and the spacers, and contact plugs formed between adjacent gate structures and contact the respective source regions. The source regions are adjacent to the gate structures. The sidewalls of the spacers are aligned with the sidewalls of the underlying source regions.

Description

Semiconductor structures and manufacturing methods

The present invention relates to semiconductor structures and manufacturing methods thereof, and in particular to semiconductor structures having self-aligned contact plugs and manufacturing methods thereof.

The semiconductor industry continues to improve the integration density of different electronic components by continuing to reduce the minimum component size, allowing more components to be integrated in a given area. For example, trench gate metal oxide semiconductor field effect transistors, which are widely used in power switch components, use vertical structure design to increase functional density. It uses the back side of the chip as the drain, and makes the sources and gates of multiple transistors on the front side of the chip.

However, as the functional density of semiconductor devices continues to increase, the complexity of processing and manufacturing the semiconductor devices also increases. For example, due to limitations in the alignment capabilities of traditional lithography exposure machines, the characteristic size of the contact structure of trench-type gate metal oxide semiconductor field effect transistors cannot be reduced, and the on-resistance (on-resistance) of the device cannot be effectively reduced. -resistance; Ron). Furthermore, due to machine capacity or process limitations, the overlay of the formed components may be inaccurate, causing many problems and making the electrical performance of the semiconductor device unstable.

Some embodiments of the present disclosure provide a semiconductor structure, including a substrate, gate structures located in the substrate, dielectric portions respectively located on corresponding gate structures, adjacent to sidewalls of the dielectric portions and along the dielectric portions. Spacers extending from the sidewalls of the electrical portion, source regions located between the substrate and the spacers, and contact plugs located between adjacent gate structures and in contact with the corresponding source regions (contact plugs). The source regions are adjacent to the gate structures. The side walls of the spacers are respectively flush with the side walls of the corresponding source regions below.

Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including providing a substrate; forming a plurality of gate structures in the substrate; forming a plurality of mask strips in a first direction of the substrate are spaced apart, and the gate structures and the mask strips do not overlap in a vertical projection direction; a spacer layer is formed, and on both sides of the mask strips, each mask strip and the spacer layer form a spacer layer. Patterning the mask layer; forming a plurality of dielectric portions to cover the gate structures and the patterned mask layer; removing the mask strips to form a plurality of openings; and forming a plurality of contact plugs to fill in the Some openings.

The following disclosure provides numerous embodiments or examples for implementing different elements of the provided semiconductor structures. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, or may include an additional element formed between the first and second elements. , so that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numbers and/or letters in different examples. This repetition is for the sake of brevity and clarity and is not intended to indicate the relationship between the various embodiments discussed.

Furthermore, spatially related expressions may be used in the following descriptions, such as "under", "under", "below", "above", "above" and other similar terms A term used to simplify the statement of the relationship between one element or component and other elements or other components as shown in the figure. Such spatially relative terms include, in addition to the directions depicted in the drawings, various orientations of the device during use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Some variations of the embodiments are described below. Similar reference numbers are used to identify similar elements in the various drawings and illustrated embodiments. It will be appreciated that additional steps may be provided before, during, and after the method, and some of the recited steps may be replaced or deleted for other embodiments of the method.

Embodiments of the present disclosure provide semiconductor structures and fabrication methods that can fabricate self-aligned contact plugs and self-aligned gate structures with acceptable overlay offset process windows. overlay-misaligned window) can be expanded, making the electrical performance of the semiconductor structure more stable, thereby improving the electronic characteristics and reliability of the semiconductor structure. The contents of the embodiments may be applied to metal-oxide-semiconductor (MOS) devices, such as metal-oxide-semiconductor field effect transistors (MOSFETs). In some of the following embodiments, trench gate metal oxide semiconductor field effect transistors are used as examples of relevant components in the semiconductor structure.

1A-1K are cross-sectional schematic diagrams of semiconductor structures at various intermediate manufacturing stages according to some embodiments of the present disclosure.

Referring to Figure 1A, according to some embodiments, a substrate 10 is provided. In some embodiments, the substrate 10 can be a piece of semiconductor substrate, such as a semiconductor wafer. For example, the substrate 10 is a silicon wafer. Substrate 10 may include silicon or other elemental semiconductor materials, such as germanium. In some embodiments, the substrate 10 may include a sapphire substrate, a silicon substrate, or a silicon carbide substrate. In some embodiments, the substrate 10 may include a layer or multi-layer structure composed of a semiconductor material, an insulator material, a conductor material, or a combination thereof. For example, the substrate 10 may be formed of at least one semiconductor material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In another embodiment, the substrate 10 may also include silicon on insulator (SOI). The SOI substrate can be formed using an oxygen implant isolation (SIMOX) process, a wafer bonding process, other applicable methods, or a combination of the foregoing. In another embodiment, the substrate 10 may also be composed of multi-layer materials, such as Si/SiGe, Si/SiC. In another embodiment, the substrate 10 may include an insulator material, such as an organic insulator, an inorganic insulator, or a combination thereof to form a layer or multi-layer structure. In another embodiment, the substrate 10 may also include a conductive material, such as polycrystalline silicon, metal, alloy, or a combination thereof to form a layer or multi-layer structure.

According to some embodiments, the first implantation layer 11 and the second implantation layer 12 are sequentially formed above the substrate 10 . The doping concentration of the second implantation layer 12 is higher than the doping concentration of the first implantation layer 11 . In some embodiments, according to subsequent processes (as described later), the first implant layer 11 is patterned into body regions between gate structures, and the second implant layer 12 is patterned into body regions. The source regions on the region, so the first implant layer 11 can also be called the body implant layer, and the second implant layer 12 can also be called the source implant layer. layer).

In some examples, a substrate is doped to inject the dopant onto the top of the substrate, and the dopant atoms are thermally activated to drive the dopant to diffuse. The conductivity type of the dopant ions is opposite to that of the substrate. In some embodiments for N-channel components, the dopant ions may be boron ions. In some embodiments for P-channel components, the dopant ions may be phosphorus or arsenic ions. In some examples, dopant diffusion with a first doping concentration may be performed, and then dopant diffusion with a second doping concentration in this diffusion region, the second doping concentration being greater than the first doping concentration, To form a first implantation layer (eg, body implantation layer) 11 and a second implantation layer (eg, source implantation layer) 12 as shown in FIG. 1 respectively.

Next, according to some embodiments, a patterned mask layer 15 is formed over the substrate 10 (FIG. 1C) to form a plurality of gate trenches 16 in the substrate 10 (FIG. 1C). 1D diagram).

As shown in FIG. 1B , in some embodiments, a hard mask 130 is formed above the substrate 10 , such as the second implant layer 12 . The hard mask 130 is, for example, composed of alternating layers of two different insulating materials. The hard mask 130 includes a first mask layer 131 located on the second implant layer 12 , a second mask layer 132 located on the first mask layer 131 , and a third mask located on the second mask layer 132 Layer 133. In one example, the first mask layer 131 and the third mask layer 133 include, but are not limited to, an oxide, which may be silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, or other suitable materials. Dielectric material. The second mask layer 132 includes, for example, but is not limited to, nitride. For example, it can be silicon nitride, aluminum nitride, silicon oxynitride or other suitable dielectric materials. The hard mask in this example 130 can also be called an ONO layer.

Then, referring to FIG. 1B , in some embodiments, the hard mask 130 is patterned through, for example, an optical lithography process to form a patterned hard mask. In one example, the third mask layer 133 including oxide and the second mask layer 132 including nitride are etched to form a patterned hard mask.

As shown in Figure 1B, the patterned hard mask formed includes a plurality of mask strips 13, and these mask strips 13 are spaced apart in the first direction D1. In this example, the material layers of the mask strip 13 are stacked in the second direction D2 and extend in the third direction D3. Each mask strip 13 includes a second patterned mask layer 132' located on the first mask layer 131 and a third patterned mask layer 133' located on the second patterned mask layer 132'. According to some embodiments, the position of these mask strips 13 determines the position of subsequently formed contact plugs (Fig. 1K, contact plugs 195).

Next, referring to Figure 1C, in some embodiments, a spacer layer 14 is formed on the side walls of the mask strips 13. In one example, the method of forming the spacer layer 14 is to first conformably deposit a spacer material (not shown) on the sidewalls 13s and the top surface 13a of the mask strips 13; and then etch the spacer material. , to remove the portion of the spacer material located above the top surface 13 a of the mask strip 13 to expose the third patterned mask layer 133 ′, and the remaining portion of the spacer material is the spacer layer 14 . When etching the spacer material, the portion of the first mask layer 131 other than the spacer layer 14 (that is, the portion of the first mask layer 131 not covered by the spacer layer 14) is also removed to expose the underlying substrate. Material. In this example, after etching the spacer material, the top surface 12a of the second implant layer (eg, the source implant layer) 12 is exposed.

In some embodiments, the spacer layer 14, the first patterned mask layer 131', the second patterned mask layer 132' and the third patterned mask layer 133' together form a patterned mask layer ( patterned mask layer)15. The patterned mask layer 15 includes a plurality of openings 152 exposing the top surface 12a of the second implant layer (eg, the source implant layer) 12 .

Referring to Figure 1D, in some embodiments, through the opening 152 of the patterned mask layer 15, the underlying material layer includes a second implantation layer (eg, source implantation layer) 12, a first implantation layer (eg, body implantation layer) The implant layer 11 and the substrate 10 are etched to form a plurality of gate trenches 16 . The gate trenches 16 are, for example, spaced apart in the first direction D1 and extend downward along the second direction D2. The first direction D1 is different from the second direction D2. In this example, the first direction D1 is perpendicular to the second direction D2. Specifically, the gate trench 16 continues the opening 152 of the patterned mask layer 15 , and sequentially penetrates the second implantation layer 12 and the first implantation layer 11 , as well as the removed portion of the substrate 10 . Furthermore, in this example, the width of the opening 152 of the patterned mask layer 15 in the first direction D1 is substantially the same as the width of the gate trench 16 in the first direction D1.

Then, according to some embodiments, a gate structure (such as gate structure 166 shown in FIG. 1F ) is formed in gate trench 16 . Each gate structure may include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer.

Referring to FIG. 1E , according to some embodiments, a gate dielectric layer 162 is formed in the gate trench 16 . The gate dielectric layer 162 can be formed by, for example, using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation (thermal oxidation) process, a physical vapor deposition (PVD) process, or other applicable processes. Or formed by a combination of the aforementioned processes. In some embodiments, the gate dielectric layer 162 may be composed of silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum hafnium dioxide alloy, silicon hafnium dioxide, silicon hafnium oxynitride, tantalum hafnium oxide, titanium hafnium oxide, It is formed of zirconium and hafnium, other suitable high-k dielectric materials, or a combination of the foregoing materials.

In this example, the materials of the substrate 10 , the first implant layer 11 ′ and the second implant layer 12 ′ are oxidized, for example, through a thermal oxidation process, so that the substrate 10 ′ exposed in the gate trench 16 A gate dielectric layer 162 is formed on the surface, the sidewalls of the first implantation layer 11' and the sidewalls of the second implantation layer 12'. The gate dielectric layer 162 of this example may also be called a gate oxide layer.

Referring to FIG. 1F , according to some embodiments, a gate electrode 164 is formed on the gate dielectric layer 162 in the gate trench 16 . In some embodiments, a conductive material (not shown) may be deposited over the substrate 10' and fill the gate trenches 16. The conductive material may be in-situ doping or undoped polycrystalline silicon. Afterwards, the top surface 164a of the gate electrode 164 is formed, for example, by etching back. In one embodiment, the top surface 164a of the gate electrode 164 does not exceed the second implantation layer (such as the source implantation layer) 12 The top surface 12a of ' or both are substantially flush (for example, as shown in Figure 1F), but the present invention is not limited to this. The gate dielectric layer 162 and the gate electrode 164 in each gate trench 16 together form a gate structure 166 . In this example, the gate structures 166 are spaced apart in the first direction D1 and extend downward along the second direction D2. The first direction D1 is, for example, perpendicular to the second direction D2.

Furthermore, according to some embodiments, the top surface 164a of the gate electrode 164 is preferably higher than the bottom surface 12b of the second implant layer 12'. Since the second implant layer 12' will form a source region in the subsequent process, the source region will better control the gate electrode 164 to improve the electrical performance of the semiconductor structure (for example, improve the breakdown voltage).

1G, according to some embodiments, a dielectric material layer 170 is formed over the substrate 10', and the dielectric material layer 170 covers the gate structure 166 and the patterned mask layer 15. The dielectric material layer 170 may provide isolation between the active region and subsequently formed conductive features such as contact plugs and metal lines. In some embodiments, the dielectric material layer 170 is thick enough to cover the patterned mask layer 15 and can fill the gaps between the patterned mask layers 15 above the gate structure 166 . It can be formed by any suitable method, such as chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), flow chemical vapor deposition (FCVD), a combination of the foregoing methods, or other suitable methods. A layer of dielectric material 170 is deposited. The dielectric material layer 170 may include, for example, tetraethoxy silane (TEOS) oxide, or phospho-silicate glass (PSG), boro-silicate glass (BSG), boron Boron-doped phospho-silicate glass; BPSG), or oxide of undoped silicon glass (undoped Silicone Glass; USG), or similar substances. Dielectric material layer 170 may also include other insulating materials formed by any acceptable method. Furthermore, in some embodiments, the material of the dielectric material layer 170 is the same as the material of the spacer layer 14 . In some other embodiments, the material of dielectric material layer 170 is different from the material of spacer layer 14 .

Next, referring to FIG. 1H , according to some embodiments, part of the dielectric material layer 170 and part of the patterned mask layer 15 are removed, and dielectric portions 17 are formed above the gate structure 166 and in the dielectric layer 170 . Spacers 143 are formed on the side walls 17s of the electrical part 17.

According to some embodiments, a portion of the dielectric material layer 170 and a portion of the patterned mask layer 15 are removed through a photolithographic patterning process and an etching process. In some embodiments, the lithography patterning process includes photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning, and drying (e.g., hard coating). baking), other suitable processes, or a combination of the foregoing, to form a patterned photoresist layer PR above the dielectric material layer 170. Then, according to the patterned photoresist layer PR, the dielectric material layer 170 and the portion of the patterned mask layer 15 not covered by the patterned photoresist layer PR are etched. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching (RIE) process, other suitable processes, or a combination of the foregoing processes. The etching process stops on the top surface 132a of the second patterned mask layer (e.g., nitride layer) 132', as shown in Figure 1H. Therefore, in this example, the second patterned mask layer 132' can serve as an etch stop layer for the etching process used to form the dielectric portion 17 and the spacer 143.

Referring again to FIG. 1H , according to some embodiments, after removing part of the dielectric material layer 170 and part of the patterned mask layer 15 through an etching process, the remaining part of the dielectric material layer 170 is tied to the gate structure 166 The dielectric portion 17 is formed above, and the remaining portion of the spacer layer 14 forms spacers 143 on the sidewalls 17s of the dielectric portion 17 . Furthermore, after the etching process is completed, openings 18 are formed between adjacent dielectric portions 17 .

According to some embodiments of the present disclosure, these openings 18 expose the top surface 132a of the corresponding second patterned mask layer 132'. Specifically, these openings 18 expose the top surface 132a of the second patterned mask layer 132' and the upper portion of the sidewall 17s of the dielectric portion 17. In the figure, two openings are taken as an example, including a first opening 181 and a second opening 182, to illustrate different situations of openings formed according to some embodiments. Furthermore, the figures take two sets of spacers as an example, including a first set of spacers 141 and a second set of spacers 142, to illustrate the opening of the opening according to some embodiments. The spacer 143 formed below 18.

In actual applications, due to the machine's alignment capabilities or process limitations, the position of the upper and lower components may shift during the mask alignment, exposure, and development processes. The first opening 181 shown in FIG. 1H is used to represent an ideal opening, wherein the symmetrical center line of the first opening 181 along the second direction D2 is along the second patterned mask layer 132' below. A pair of symmetrical center lines in the second direction D2 roughly coincide. The second opening 182 shown in FIG. 1H is used to represent an offset opening, wherein the symmetric centerline of the second opening 182 along the second direction D2 is offset from the second patterned mask layer 132' below. A center line of symmetry along the second direction D2.

According to some embodiments of the present disclosure, as long as the formed opening 18 can completely expose the top surface 132a of the corresponding second patterned mask layer 132' below to facilitate subsequent processes, the opening 18 is acceptable. Implementation style. Therefore, whether the ideal first opening 181 or the offset second opening 182 is formed as shown in FIG. 1H , the subsequent processes of the embodiment can be continued through these openings, including removing the second pattern mask. Cap layer 132' (FIG. 1I), contact hole formation is completed (FIG. 1J), and self-aligned contact plugs are formed (FIG. 1K, contact plug 195).

According to some embodiments, after completing the above etching process, the patterned photoresist layer PR is removed through an acceptable ashing process.

Referring to FIG. 1I , after the openings 18 are formed, according to some embodiments, the remaining portions of the mask strips 13 between the spacers 143 are removed to form holes between the spacers 143 . Specifically, in this example, the underlying second patterned mask layer 132' is removed through the first opening 181 and the second opening 182 to form holes 183A and 184A respectively. The holes 183A and 184A are, for example, exposing the top surface of the first patterned mask layer 131'. The second patterned mask layer 132 can be removed through a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching (RIE) process, other suitable processes, or a combination of the foregoing processes. '. In some embodiments, a wet etching process is used to remove the second patterned mask layer 132', and the etchant used can selectively etch the material of the second patterned mask layer 132', but generally The material of dielectric portion 17 and spacer 143 is not etched.

According to some embodiments, as shown in FIG. 1I , the formed dielectric portions 17 are respectively in direct contact with the corresponding gate structures 166 below. Specifically, the top surface 164a of the gate electrode 164 (the top surface 166a of the gate structure 166) is completely covered by the dielectric portion 17. Furthermore, in some embodiments, the formed spacers 143 are in direct contact with the sidewalls 17s of the corresponding dielectric portion 17 respectively.

Referring again to FIG. 1I, the first opening 181 is an ideal opening, and the formation position is not offset. After removing the second patterned mask layer 132' below through the first opening 181, the dielectric portion 17 located on both sides of the hole 183A The first group of spacers 141 on the side walls 17s are spacers with approximately the same width, that is, the width W11 and the width W12 are approximately the same (W11=W12). Moreover, according to the manufacturing method of the embodiment, even if the second opening 182 may be slightly offset due to limitations of the machine alignment capability or other process factors, the second patterning underneath is removed through the second opening 182 After the mask layer 132', the second set of spacers 142 located on the sidewalls 17s of the dielectric portion 17 on both sides of the hole 184A still have spacers with approximately the same width, that is, the width W21 and the width W22 are approximately the same (W21=W22 ).

Next, referring to FIG. 1J , according to some embodiments, the formed spacers 143 (eg, the first group of spacers 141 and the second group of spacers 142 ) and the dielectric portion 17 are used as an etching mask. The material layer below holes 183A and 184A is etched to form self-aligned contact holes 183 and 184 . According to some embodiments, holes 183A and 184A are extended by etching through the first patterned mask layer 131' and the second implanted layer 12' and portions of the first implanted layer 11' are removed to form holes 183A and 184A through etching. Holes 183B and holes 184B are formed successively below the holes 184A. As shown in FIG. 1J , the upper holes 183A and 184A are generally located between adjacent dielectric portions 17 , while the lower holes 183B and 184B are generally located between two adjacent gate structures 166 . In this example, holes 183A and 183B constitute contact holes 183 , and holes 184A and 184B constitute contact holes 184 .

According to some embodiments, the etching process used is highly selective for spacers 143 (eg, first set of spacers 141 and second set of spacers 142) and second implant layer 12', and for spacers 143 and The substrate 10' has high selectivity to selectively etch the second implant layer 12' and the substrate 10' without etching the spacers 143. In some embodiments, the etching process may be a dry etching process, such as a reactive ion etch (RIE) process, a plasma etching process, other suitable anisotropic etching processes, or any of the foregoing processes. combination.

Furthermore, according to some embodiments, in this step of forming the contact hole 183 and the contact hole 184, the source region 120 is also formed. These contact holes (eg, 183 and 184) expose the sidewalls 120s of the source region 120. As shown in Figure 1J, after extending the holes 183A and the holes 184A to penetrate the first patterned mask layer 131' and the second implantation layer 12', the remaining portions of the second implantation layer 12' form these sources. Polar area 120. In some embodiments, the top surface 164a of the gate electrode 164 is higher than the bottom surface 120b of the source region 120, but does not exceed (eg, is lower than or flush with) the top surface 120a of the source region 120.

According to some embodiments, the source region 120 is located between the substrate 10' and corresponding spacers 143 (e.g., the first set of spacers 141 or the second set of spacers 142). In this example, since the source region 120 is formed by etching downwards using the spacers 143 as an etching mask, the sidewalls of the spacers 143 located above the source region 120, such as the sidewalls 141s of the first group of spacers 141 or The sidewalls 142s of the second set of spacers 142 are respectively aligned with the sidewalls 120s of the source region 120 below.

As discussed above, in some embodiments, the spacers located on both sides of the holes 183A and 184A have substantially the same width, so that the source regions 120 on both sides of each contact hole 183 or 184 are formed along the first Direction D1 also has the same width. Please refer to Figures 1I and 1J at the same time. In this example, the width of the source region 120 on both sides of the contact hole 183 corresponds to the width W11 and the width W12 of the spacer 143, and the width W11 and the width W12 are approximately the same; The width of the source region 120 on both sides of the contact hole 184 is, for example, corresponding to the width W21 and the width W22 of the spacer 143 , and the width W21 and the width W22 are substantially the same.

Next, referring to FIG. 1K , according to some embodiments, contact plugs 195 and 196 are formed in the contact holes 183 and 184 respectively. In some embodiments, a contact barrier layer 192 is conformally deposited in the structure as shown in FIG. 1J, and the contact barrier layer 192 forms a lining in the contact holes 183, 184. Specifically, the contact barrier layer 192 is formed on the exposed surface of the dielectric portion 17 (such as the top surface 17a and part of the sidewalls 17s), the exposed sidewalls of the spacer 143 (such as the sidewalls 141s and 142s), and the source region 120. The sidewalls 120s and the exposed surface of the base 10' are exposed.

In some embodiments, the material of the contact barrier layer 192 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), cobalt tungsten phosphide (CoWP) , ruthenium (Ru), other suitable materials, or combinations of the foregoing materials. In some embodiments, the contact barrier may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or a combination of the foregoing processes. Layer 192.

After the contact barrier layer 192 is formed, a conductive material (not shown) is deposited above the contact barrier layer 192 , where the conductive material fills the first opening 181 , the second opening 182 , the contact hole 183 and the contact hole. 184. Then, the conductive material is etched back to a specific depth (for example, the top surface of the remaining conductive material is lower than the first opening 181 and the second opening 182 ). As shown in FIG. 1K , in this example, the conductive portion 193 formed after etching back the conductive material forms a contact plug 195 with the portion 1921 of the contact barrier layer 192 in the contact hole 183 . The conductive portion 194 formed by etching back the conductive material forms a contact plug 196 with the portion 1922 of the contact barrier layer 192 in the contact hole 184 .

Furthermore, according to some embodiments, the uppermost surfaces of the spacers are higher than the top surfaces of the contact plugs 195, 196. For example, in this example, the topmost surface 141a of the first group of spacers 141 is higher than the top surface 193a of the conductive portion 193 (also serving as the top surface of the contact plug 195), and the topmost surface of the second group of spacers 142 142a is higher than the top surface 194a of the conductive portion 194 (also serving as the top surface of the contact plug 196). Furthermore, according to some embodiments, the top surfaces (eg, the topmost surfaces 141a, 142a) of the first group of spacers 141 and the second group of spacers 142 do not exceed (eg, are lower than) the top surface 17a of the dielectric portion 17 .

In some embodiments, the conductive material forming the conductive portion 193 and the conductive portion 194 may include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (Titanium nitride) ,TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride, TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (titanium aluminide nitride, TiAlN), other suitable metals or combinations of the above. In this example, conductive portion 193 and conductive portion 194 include tungsten. Furthermore, in some embodiments, chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process, physical The conductive material is formed by a vapor phase deposition (PVD) process, other suitable processes, or a combination of the foregoing processes.

In some embodiments, as shown in Figure 1K, before forming the contact barrier layer 192, an ion implantation process may be performed to form the contact doping region 191 in the first implantation layer 11'. The doping concentration of the contact doped region 191 is higher than the doping concentration of the first implant layer 11'. According to some embodiments, these contact doped regions 191 are located under and in contact with the contact plugs 195 and 196 to reduce on-resistance (Ron).

Furthermore, according to some embodiments, after the contact plugs 195, 196 are formed, a metal layer 197 is deposited over the substrate 10'. As shown in Figure 1K, the metal layer 197 is deposited on the contact barrier layer 192 and the contact plugs 195 and 196 for subsequent interconnection. In some embodiments, the metal layer 197 may be aluminum (Al), aluminum copper (AlCu), or other suitable metal materials.

According to some embodiments, the method of fabricating a semiconductor structure as illustrated in FIGS. 1A to 1K can produce a semiconductor structure having a self-aligned gate structure 166 and self-aligned contact plugs (eg, contact plugs 195, 196). Semiconductor structures. According to some embodiments, as shown in Figures 1H-1K, the portion of the metal layer 197 (which can also be called a metal portion) in the first opening 181 (as mentioned above, is an ideal opening), is along the second The center line of symmetry (not shown) in direction D2 coincides with the center line of symmetry (not shown) of the lower contact plug 195 along the second direction D2. The center line of symmetry L1 of the metal portion in the second opening 182 (as mentioned above, an offset opening) along the second direction D2 is offset from the center of symmetry of the lower contact plug 196 along the second direction D2. Line L2. However, regardless of whether the opening of the metal layer 197 housing the portion above the contact plug is in an ideal position or is offset position, in the semiconductor structure produced according to the embodiment, the distance between the opposite side walls of each contact plug and the adjacent gate structure 166 in the first direction D1 is approximately equal. According to some embodiments, the distance along the first direction D1 between one side wall of each contact plug and an adjacent gate structure 166 is defined by the width of the source region 120 along the first direction D1, as shown in Shown in Figure 1K. In some embodiments, the source regions 120 on both sides of each contact plug have the same width in the first direction D1. In other words, each contact plug of the embodiment is located between adjacent gate structures 166 without offset.

Therefore, compared with components formed in traditional processes, there are many problems caused by inaccurate overlay, such as between semiconductor structures (such as dies) of different wafers and/or the center position and position of the same wafer. There may be electrical differences between the semiconductor structures at the edges or affect their electrical performance, such as causing unstable critical voltage, unstable on-resistance, or unclamped inductive load (UIS) test failure, or even between conductive components. Direct contact between (such as contact plug and gate structure) may cause short circuit and other problems. The manufacturing method proposed in the embodiment can expand the acceptable overlay-misaligned process window (acceptable overlay-misaligned window) and form self-aligned contact plugs without offset to avoid overlay-misaligned windows in traditional processes. To solve the above problems caused by inaccuracy, the stability of the semiconductor structure is improved. Therefore, the semiconductor structure of the embodiment can have stable electrical performance and good reliability.

In addition to the above-mentioned manufacturing method as shown in Figures 1A-1K, the semiconductor structure of the present invention can also be manufactured by other manufacturing methods to prepare self-aligned gate trenches and self-aligned contact plugs. 2A-2E are schematic cross-sectional views of semiconductor structures at various intermediate manufacturing stages according to some embodiments of the present disclosure. Components in Figures 2A-2E that are identical or similar to those in Figures 1A-1K above have the same or similar reference numbers and may Refer to the content of these components in the above embodiments.

Referring to Figure 2A, a structure as shown in Figure 1G is first provided, including a plurality of gate structures 166 spaced apart from each other in the first direction D1 and extending downward along the second direction D2 in the substrate 10' to define the gate. The patterned mask layer 15 (including the first patterned mask layer 131', the second patterned mask layer 132', the third patterned mask layer 133' and the spacer layer 14) at the location of the structure 166 and the intervening Layer 170 of electrical material. Furthermore, the structure in Figure 2A also includes a first implantation layer (such as a body implantation layer) 11' and a second implantation layer (such as a source implantation layer) 12' on the substrate 10'. For details of the configuration, materials and manufacturing methods of the components shown in Figure 2A, please refer to the description related to the above Figure 1G and will not be repeated here.

The manufacturing method proposed in the above-mentioned Figures 1H-1K is to use a photolithography process and an etching process to remove part of the dielectric material layer 170 and part of the patterned mask layer 15 to expose the second patterned mask layer 132'. Different from the method in Figures 1H-1K, the manufacturing method proposed in Figures 2A-2E is to directly perform a planarization process on the dielectric material layer 170 to expose the second patterned mask layer 132'.

Referring to FIG. 2B, according to some embodiments, a planarization process is performed on the dielectric material layer 170 until the second patterned mask layer 132' is exposed. During this planarization process, part of the dielectric material layer 170 and part of the patterned mask layer 15 are removed. After the planarization process, the remaining portion of the dielectric material layer 170 forms the dielectric portion 172 above the gate structure 166 , and the remaining portion of the spacer layer 14 forms a space on the sidewalls 172s of the dielectric portion 172 Things 145 and 146. According to some embodiments, the top surfaces of spacers 145 and 146 may be formed to be substantially flush with top surface 172 a of dielectric portion 172 .

Specifically, as shown in FIG. 2B , in this example, the planarization process removes part of the dielectric material layer 170 , part of the spacer layer 14 and the third patterned mask layer 133 ′, and exposes the third patterned mask layer 133 ′. Two patterned mask layers 132'. Therefore, in this example, the second patterned mask layer 132' can serve as a stop layer for the planarization process. Furthermore, the planarization process may cause the top surface 172a of the dielectric portion 172 and the top surfaces 145a and 146a of the spacers 145 and 146 to be slightly dished, but this does not affect the subsequent formation of self-aligned contact plugs. process.

In some embodiments, the planarization process may include a chemical mechanical planarization (CMP) process, a mechanical polishing process, an etching process, other suitable processes, or a combination of the foregoing processes. In this example, a chemical mechanical polishing process is used to remove part of the dielectric material layer 170 and part of the patterned mask layer 15 .

Next, referring to Figure 2C, according to some embodiments, the second patterned mask layer 132' is removed to form holes 183A and 184A. The holes 183A and 184A are, for example, exposing the top surface of the first patterned mask layer 131'. The second patterned mask layer 132 can be removed through a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching (RIE) process, other suitable processes, or a combination of the foregoing processes. '. In some embodiments, a wet etching process is used to remove the second patterned mask layer 132', and the etchant used can selectively etch the material of the second patterned mask layer 132', but generally The material of dielectric portion 172 and spacers 145, 146 is not etched.

For other relevant details of the configuration, materials and manufacturing methods of the components shown in Figure 2C, please refer to the description of the relevant content in Figure 1I above and will not be repeated here. Furthermore, Compared with the manufacturing method proposed in Figures 1A-1K, the manufacturing method proposed in Figures 2A-2E does not form openings above the holes 183A and 184A (such as the first openings shown in Figures 1H, 1I, and 1J). 181 and second opening 182). However, according to the manufacturing method proposed in Figures 2A-2E, which is the same as the manufacturing method in Figures 1A-1K, spacers with substantially the same width can be formed on both sides of each hole (eg, 183A and 184A).

Specifically, as shown in FIG. 2C , the spacers 145 located on the side walls 172s of the dielectric portion 172 on both sides of the hole 183A are spacers with substantially the same width, that is, the width W11 and the width W12 are substantially the same; The spacers 146 on the side walls 172s of the dielectric portion 172 on both sides of 184A are spacers with substantially the same width, that is, the width W21 and the width W22 are substantially the same.

Next, referring to Figure 2D, according to some embodiments, the formed spacers 145, 146 and dielectric portion 172 are used as an etching mask to etch the material layer below the hole 183A and the hole 184A to form a self-contained layer. Self-aligned contact holes 183 and 184 . According to some embodiments, holes 183A and 184A are extended by etching to penetrate the first patterned mask layer 131' and the second implanted layer 12', and a portion of the first implanted layer 11' is removed. After etching, holes 183B and holes 184B are successively formed below the holes 183A and 184A, respectively. As shown in FIG. 2D , the upper holes 183A and 184A are generally located between adjacent dielectric portions 172 , while the lower holes 183B and 184B are generally located between two adjacent gate structures 166 . In this example, holes 183A and 183B constitute contact holes 183 , and holes 184A and 184B constitute contact holes 184 . The etching process used is, for example, highly selective for the spacers 145, 146 and the second implant layer 12', and highly selective for the spacers 145, 146 and the substrate 10', to selectively etch the second implant layer 12' and the substrate 10' without etching the spacers 145, 146.

For other relevant details of the configuration, materials and manufacturing methods of the components shown in Figure 2D, please refer to the description of the relevant content in Figure 1J above and will not be repeated here.

Furthermore, according to some embodiments, during the step of forming the contact hole 183 and the contact hole 184, the source region 120 is also formed. These contact holes 183 and 184 expose the sidewalls 120s of the source region 120 . As shown in Figure 2D, after extending the holes 183A and the holes 184A to penetrate the first patterned mask layer 131' and the second implantation layer 12', the remaining portions of the second implantation layer 12' form these sources. Polar area 120. According to some embodiments, source region 120 is located between substrate 10' and corresponding spacers 145, 146.

In this example, since the source region 120 is formed by etching downwards using the spacers 145 and 146 as etching masks, the sidewalls 145s of the spacer 145 and the sidewalls 146s of the spacer 146 are aligned with respectively. On the sidewall 120s of the lower source region 120. Furthermore, in some embodiments, since the spacers on both sides of the holes 183A and 184A have approximately the same width, the source regions 120 on both sides of each contact hole 183 or 184 are formed along the first direction. D1 also has the same width.

Next, referring to FIG. 2E , according to some embodiments, contact plugs 195 and 196 are formed in contact holes 183 and 184 respectively. In this example, the conductive portion 193 in the contact hole 183 and the portion 1921 of the contact barrier layer 192 in the contact hole 183 together form the contact plug 195 . The conductive portion 194 in the contact hole 184 and the portion 1922 of the contact barrier layer 192 in the contact hole 184 together form a contact plug 196 . For the materials and formation methods of the contact barrier layer 192, the conductive portion 193, and the conductive portion 194, please refer to the description related to the above-mentioned Figure 1K and will not be repeated here.

In some embodiments, before forming the contact barrier layer 192, an ion implantation process may be performed to form a heavily doped contact doping region 191 in the first implantation layer 11'. These contact doped regions 191 are located under and in contact with the contact plugs 195 and 196, which can reduce the on-resistance (Ron).

Furthermore, according to some embodiments, after the contact plugs 195, 196 are formed, a metal layer 197 is deposited over the substrate 10'. As shown in FIG. 2E, the metal layer 197 is deposited on the contact barrier layer 192 and the contact plugs 195 and 196 for subsequent interconnection. In some embodiments, the metal layer 197 may be aluminum (Al), aluminum copper (AlCu), or other suitable metal materials.

In summary, according to some embodiments of the present disclosure, such as the manufacturing method of the semiconductor structure illustrated in FIGS. 1A-1K and 2A-2E, contact plugs (such as contact plugs 195, 196) with self-alignment can be produced. ) semiconductor structure, and the formed self-aligned contact plug can maintain a substantially equal distance from the gate structures on both sides (such as the self-aligned gate structure 166), thereby enabling acceptable overlay. The offset process window is expanded, making the electrical performance of the semiconductor structure more stable, thereby improving the electronic characteristics and reliability of the semiconductor structure. When the manufacturing method and the semiconductor structure produced in the embodiment are applied to trench-type MOS devices, especially MOS devices with trench-type gates with small pitches, they can improve the tendency of components formed in traditional manufacturing methods to overlay. Inaccurate defects, thereby avoiding various problems caused by inaccurate overlay, such as avoiding between semiconductor structures (such as dies) on different wafers and/or between semiconductor structures at the center and edge of the same wafer The electrical performance is unstable (including possible critical voltage instability, unstable on-resistance, unclamped inductive load (UIS) test failure, etc.), or even between conductive parts (such as contact plugs and gates) pole structure) in direct contact, causing short circuit and other poor reliability problems. Therefore, the electronic characteristics and reliability of MOS devices, especially MOS devices with small-pitch gate structures, can be improved by applying the manufacturing methods and semiconductor structures produced in the embodiments.

10,10’: Base

11,11’: first planting layer

12,12’: Second planting layer

12a,120a,13a,132a,141a,142a,145a,146a,164a,166a,17a,193a,194a: top surface

12b,120b: Bottom surface

120: Source area

120s,13s,141s,142s,17s: side wall

13: Mask strip

130:Hard mask

131: First mask layer

131’: First patterned mask layer

132: Second mask layer

132’: Second patterned mask layer

133: The third mask layer

133’: The third patterned mask layer

14: Spacer layer

141: The first set of spacers

142: The second set of spacers

143,145,146: spacer

15: Patterned mask layer

152,18:Open your mouth

16: Gate trench

162: Gate dielectric layer

164: Gate electrode

166: Gate structure

17,172:Dielectric Department

170: Dielectric material layer

181:First opening

182:Second opening

183A, 184A, 183B, 184B: holes

183,184:Contact hole

191:Contact doped area

192,1921,1922: Contact barrier layer

193,194: Conductive Department

195,196: Contact plug

197:Metal layer

PR: Patterned photoresist layer

W11, W12, W21, W22: Width

D1: first direction

D2: second direction

D3: Third direction

L1, L2: Center line of symmetry

1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J, and 1K are cross-sectional schematic diagrams of semiconductor structures at various intermediate manufacturing stages according to some embodiments of the present disclosure. Figures 2A, 2B, 2C, 2D, and 2E are schematic cross-sectional views of semiconductor structures at various intermediate manufacturing stages according to some embodiments of the present disclosure.

10’: Base

11’: The first planting layer

120a,141a,142a,164a,166a,193a,194a: top surface

120b: Bottom surface

120: Source area

120s,17s: side wall

131’: First patterned mask layer

141: The first set of spacers

142: The second set of spacers

143: spacer

162: Gate dielectric layer

164: Gate electrode

166: Gate structure

17:Dielectric Department

191:Contact doped area

192,1921,1922: Contact barrier layer

193,194: Conductive Department

195,196: Contact plug

197:Metal layer

D1: first direction

D2: second direction

D3: Third direction

L1, L2: Center line of symmetry

Claims (15)

A semiconductor structure includes: a substrate; a plurality of gate structures (gate structures) located in the substrate; a plurality of dielectric portions (dielectric portions) located on the corresponding gate structures; a plurality of spacers ( spacers adjacent to and extending along the sidewalls of the dielectric portions; a plurality of source regions located between the substrate and the spacers, and the The source regions are adjacent to the gate structures; a plurality of contact plugs are located between the adjacent gate structures and in contact with the corresponding source regions; and in the contacts A metal part is respectively formed on the plug, and the metal parts are located between the adjacent dielectric parts, and one of the metal parts is offset from the corresponding contact plug below; wherein , the side walls of the spacers are respectively flush with the side walls of the corresponding source regions below. The semiconductor structure of claim 1, wherein the dielectric parts are in direct contact with the corresponding gate structures respectively. The semiconductor structure of claim 1, wherein the spacers are in direct contact with the sidewalls of the corresponding dielectric parts, and the top surfaces of the spacers do not exceed the top surfaces of the dielectric parts. The semiconductor structure of claim 1, wherein the tops of the gate structures The surface is no higher than the top surface of the source regions or higher than the bottom surface of the source regions. The semiconductor structure of claim 1, wherein the distances from the opposite side walls of each of the contact plugs to the adjacent gate structures are equal. The semiconductor structure of claim 1, wherein the gate structures are separated in a first direction, and the source regions contacted by both sides of each contact plug are along the first direction. Directional systems have the same width. The semiconductor structure of claim 1, wherein a topmost surface of the spacers is higher than a top surface of the contact plugs. The semiconductor structure of claim 1 further includes a implant layer, the source regions are located on the implant layer, and the contact plugs extend into the implant layer. A method of manufacturing a semiconductor structure, including: providing a substrate; forming a plurality of gate structures in the substrate; forming a plurality of mask strips, the mask strips being spaced apart in a first direction on the substrate, And the gate structures and the mask strips do not overlap in a vertical projection direction; a spacer layer is formed, and on both sides of the mask strips, each of the mask strips and the spacer layer form a pattern Patterning the mask layer; forming a plurality of dielectric portions to cover the gate structures and the patterned mask layer; removing the mask strips to form a plurality of openings; and forming a plurality of contact plugs to fill the Open your mouth. The manufacturing method of a semiconductor structure as claimed in claim 9, wherein forming the gate structures includes: forming a plurality of gate trenches in the substrate; depositing a conductive material on top of the substrate and filling the substrate some gate trenches; and Etch back the conductive material to form the gate structures in the gate trenches; wherein the top surfaces of the gate structures are higher than the bottom surfaces of the plurality of source regions and do not exceed The top surfaces of the source regions. The manufacturing method of a semiconductor structure as claimed in claim 10, before forming the gate structures, further comprising: forming a first implantation layer on the substrate; and forming a second implantation layer on the first implantation layer. Implantation layer, wherein the doping concentration of the second implantation layer is higher than the doping concentration of the first implantation layer; wherein the gate trenches penetrate the second implantation layer and the first implantation layer and extend into the base. The manufacturing method of a semiconductor structure as claimed in claim 11, wherein forming the mask strips includes: sequentially forming a first mask layer, a second mask layer and a third mask layer above the substrate; and The first mask layer, the second mask layer and the third mask layer are patterned to form the mask strips. The manufacturing method of a semiconductor structure as claimed in claim 12, wherein forming the gate structures includes: using the patterned mask layer as an etching mask, the second implantation layer, the first implantation layer and the substrate Etching is performed to form the gate trenches. As claimed in claim 13, the manufacturing method of a semiconductor structure, wherein forming the dielectric portions above the gate structures includes: Forming a dielectric material layer over the gate structures and the patterned mask layer; and removing part of the dielectric material layer and part of the patterned mask layer; wherein the remaining part of the dielectric material layer The lower portion is the dielectric portions on the gate structures, and the remaining portions of the spacer layer form a plurality of spacers on the sidewalls of the dielectric portions. The manufacturing method of a semiconductor structure as claimed in claim 14, wherein forming the contact plugs includes: removing remaining portions of the mask strips between the spacers to form holes between the spacers; extending The holes penetrate the second implantation layer and the removed portion of the first implantation layer to form contact holes; wherein the remaining portions of the second implantation layer form the source regions, The contact holes expose a plurality of sidewalls of the source regions; and another conductive material is filled in the contact holes to form the contact plugs.

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