TWI473207B - Method for filling a physical isolation trench - Google Patents

Description

Method of filling a physical isolation trench

Embodiments of the present invention relate to processes for forming integrated circuit devices, and more particularly to methods for avoiding stylized interference in memory arrays.

In the semiconductor industry, the trend today is to continuously shrink the dimensions of various components in the manufacturing process of electronic devices. When the two have roughly the same function, smaller electronic devices will be larger and more popular. Therefore, in order to manufacture smaller devices, it is of course also necessary to make the components used in these devices smaller. However, the size of the component is reduced and the distance between them is also required to be small, which causes a problem of isolation.

In a memory device that includes a tightly packed memory cell array, stylized interference and a second bit effect are phenomena that affect the bits stored in the memory cell. Improving the isolation mechanism can reduce the impact of these phenomena. However, when having a smaller component size, the isolation mechanism must also be adjusted.

Because of the complexity of device integration and the large number of circuits in a single wafer, interconnects are typically no longer implemented using a single layer of interconnect. Rather, it is carried out in at least two or more layers of conductor interconnections, each having a pattern of conductor trenches and separated from each other by an insulating layer. Ditch can also be used for isolation. However, in the case where some of the trenches are also small in size, it becomes difficult to fill in this small space.

Accordingly, there is a need to provide an improved mechanism for filling a smaller space in a semiconductor device such as a memory array.

The present invention provides a method and apparatus that provides a relatively simple and cost effective way to fill a small space in a memory array. More particularly, in some example embodiments, it may be used to fill a physical isolation trench between active structures of a vertical channel memory array.

In an exemplary embodiment, a method of fabricating a semiconductor structure is provided. The method includes preparing a vertical channel memory structure to fill a physical isolation trench defined therebetween, the physical isolation trench is defined between adjacent active structures and extending in a first direction, the active structure also defining a channel located Adjacent to the active structure isolates the sides of the trench relative to the entity. The method also includes applying a plurality of dielectric layers (e.g., a yttria-tantalum nitride-yttria (ONO) layer), a polysilicon layer, and/or an oxide film to fill the physical isolation trench.

In another exemplary embodiment, a vertical channel memory structure is provided. The vertical channel memory structure includes at least one active structure extending in a first direction, the active structures being placed adjacent to each other and having a physical isolation trench therebetween, the physical isolation trench also extending in the first direction; Adjacent to the side of the active structure, it is adjacent to the active structure to isolate the sides of the trench for the entity. A fill material fills the solid isolation trench, which may be a multilayer dielectric material (eg, a tantalum-niobium nitride-anthracene oxide (ONO) layer), a polysilicon germanium layer, and/or a hafnium oxide film.

The objects, features, and embodiments of the present invention will be described in the accompanying drawings.

Certain embodiments of the invention are described in the following description of the embodiments of the invention, in which only some, but not all, embodiments are shown. However, different embodiments of the invention may have different types and should not be considered as limiting the present invention. The embodiments are provided so that the disclosure of this specification satisfies the requirements of the patent law.

The present invention discloses a vertical channel N-bit technology that allows for further component miniaturization. This miniaturization can provide a means for the device to store more data, for example, four bits in a memory cell, and can be further miniaturized for the foreseeable future. In order to provide improved stylized interference, a physical isolation trench (PIT) is proposed for use with vertical channel structures. This vertical channel structure is aligned along the first direction in which the channels are formed using the active stack structure. The word line is generally perpendicular to the channel and has a portion extending into the channel. In some embodiments, the memory cell formation is between the word line and the active structure. A physical isolation trench (PIT) can be involved in trench isolation within the active structure. However, filling a physical isolation trench (PIT) can be difficult because of the relatively small size of the physical isolation trench (PIT), such as in some cases less than 30 nanometers. Accordingly, certain example embodiments provided herein can provide a low cost and simple process to fill a physical isolation trench (PIT) with a dielectric or semiconductor material.

Figure 1 including Figures 1A-1E shows a schematic representation of many, but not all, of the exemplary embodiments that can be used to fill a physical isolation trench. As shown, the active structure 10 is formed on a substrate comprising an N-type material layer or a P-type material layer. In an exemplary embodiment, physical isolation trenches 20 may be formed between active structures 10 to provide isolation therebetween. The active structure 10 can extend linearly into and out of the page orientation of Figure 1 with linearly extending channels 22 on either side. This channel 22 can be formed on each side of the active structure 10 on the opposite side of the active structure 10 from the physical isolation trench 20.

FIG. 1A shows a cross-sectional view of the active structure 10 and the physical isolation trench 20 after an etching process for forming a vertical channel array. As shown in FIG. 1A, an oxide layer 13 is initially placed over the active structure 10 and the physical isolation trench 20, and a high density plasma (HDP) oxide 18 can be deposited over the physical isolation trench 20. A cleaning process can be used to remove oxide layer 13 and high density plasma (HDP) oxide 18, The active structure 10 is left exposed along the physical isolation trench 20 and the channel 22, as shown in FIG. 1B. An oxidation process can then be used in conjunction with Buried Diffusion (BD). In the beginning, the oxidized material 15 can be filled into the solid isolation trench 20 and cover the exposed areas and bottom of the active area to protect the channel area 22 as shown in FIG. 1C. Thereafter, a buried diffusion (BD) implant material 26 can be formed over the active structure and at the bottom of the channel 22, as also shown in FIG. 1C. Thereafter, a cleaning process can be performed to remove oxides from the sidewalls of the active structure, as shown in FIG. 1D, while remaining in the buried structure (BD) implant material 26 above the active structure and at the bottom of the channel 22. Figure 1E shows the completed structure of yttrium oxide-tantalum nitride-anthracene oxide (ONO) deposited in the physical isolation trench 20 and over the exposed active structure and buried diffusion (BD) implant material 26; Above the active structure and filled into the channel 22. The deposited yttria-tantalum nitride-anthracene oxide (ONO) substantially fills the physical isolation trench 20 as shown in Figure 1E. It must be noted that the word line 28 may be longitudinally extending and perpendicular (orthogonal) to the longitudinally extending channel 22. In some embodiments, the word line 28 can cover, for example, a chemical vapor deposition process or a metallization process in other semi-integral circuit processes (eg, in a process in which a contact pad or other portion of an integrated circuit is connected). Formed tungsten germanium (WSi).

In some cases, if the yttrium oxide-tantalum nitride-anthracene oxide (ONO) deposited in FIG. 1E is not well filled into the physical isolation trench 20, the physical isolation trench 20 may not be completely ruthenium-doped by ruthenium.矽-Oxide oxide (ONO) filling. If this happens, there is a risk that the physical isolation trench 20 will open to some extent. Thus, for example, polysilicon in word line 28 may be formed in a portion of physical isolation trench 20 when forming word lines. This condition creates the risk of word line bridging after the word line is patterned. In this case, as shown in FIG. 2, the vertical channel 22 extending in the first direction has a word line 28 above it and above the active structure 10. The solid isolation trenches 20 are also shown in Figure 2, and if a portion of the physical isolation trenches 20 are not completely filled, polycrystalline germanium may fill in this region to create a bridge between the word lines 28.

To prevent such word line 28 from bridging, certain embodiments may include a polysilicon (PL) pad and/or an oxide film in the physical isolation trench 20 to help fill the physical isolation trench 20 and reduce physical isolation trench open circuits. risk. Figure 3, including Figures 3A-3E, shows a number of (but not all) operational schematics that can be used to fill a physical isolation trench in accordance with an exemplary embodiment of the present invention, which can reduce the risk of physically isolating the trench opening. Figure 3A shows a schematic cross-sectional view of the active structure 10 and the physical isolation trench 20 used to form a pattern similar to Figure 1A. As shown in FIG. 3B, a thin oxide layer 100 can be formed over the exposed active structures 10 and channels 22 and within the physical isolation trenches 20. A polysilicon layer 102 is then formed over the thin oxide layer 100 and includes completely filling the entire physical isolation trench 20. Figure 3C shows the results of a chemical dry etchback etch process performed to remove the exposed polysilicon layer 102 (e.g., the portion of the polysilicon layer 102 outside the bulk isolation trench 20), leaving only the polysilicon germanium layer 104 within the physical isolation trench 20. . As shown in FIG. 3C, in some cases, the polysilicon layer 104 may not completely fill the physical isolation trench 20. However, in some cases, it is not necessary to completely fill the physical isolation trenches 20 with the polysilicon germanium layer 104.

Thereafter, an oxidation process and a buried diffusion (BD) implant are performed, and a buried diffusion (BD) implant material 26 can be formed over the active structure 10 and at the bottom of the channel 22, and the polysilicon cushion 104 is still filled with physical isolation. The inside of the trench 20 and the oxide layer 106 entirely cover the exposed surface as shown in Fig. 3D. A yttria-tantalum nitride-yttria (ONO) layer 110 can be deposited on the exposed surface and thus the polycrystalline germanium underlayer 104 within the trenches 20. Thus, when the word line 28 is formed in a direction substantially perpendicular to the channel 22, the physical isolation trench 20 is also substantially filled without the problem of physically isolating the trench opening, and thus bridging between the word lines The chances are also reduced. The metallization process can then be performed without worrying about the problem of word line bridging, as shown in Figure 3E.

The use of polysilicon layer 104 is only one example of a mechanism for reducing the probability of word line bridging. In some embodiments (eg, the example in FIG. 4), an oxide film 200 is used instead of a polysilicon (PL) pad 104 to substantially fill the physical isolation trench 20. For example, the oxide film 200 originally used to fill the physical isolation trench 20 may be retained to cover the open area of the physical isolation trench 20 using high density plasma oxide 240 to reduce word line bridging or eliminate physical isolation trench openings. The problem. Figure 4, including Figures 4A-4C, shows a schematic of many, but not all, operations that can be used to fill a physical isolation trench in accordance with an exemplary embodiment of the present invention, which can reduce the risk of physically isolating the trench opening. 4A is a cross-sectional view showing the active structure 10 and the physical isolation trench 20 used to form a pattern similar to FIGS. 1A and 3A. Here, the top buried diffusion (TBD) implant material 228 is formed prior to the vertical channel process. As shown in FIG. 4B, an oxidation process and a buried diffusion (BD) implant are performed, such that a bottom buried diffusion (BBD) implant material 226 can be deposited on the bottom of the channel 22. The oxide layer 236 can entirely cover the exposed surface, as shown in FIG. 4B, including filling the physical isolation trench 20 (using an oxidizing material 200 and an oxide 240 that covers the deposition of high density plasma). Thereafter, as shown in FIG. 4C, yttrium oxide-yttria-yttria (ONO) 244 is deposited on the exposed surface to coat the entire high density plasma deposited oxide 240 (eg, after a cleaning process) Not shown in Figure 4C). The ONO layer 244 can have a problem in which the word lines are formed in a direction substantially perpendicular to the channels 24, and the physical isolation trenches 20 are also substantially filled without physical isolation of the trench openings. Therefore, the probability of bridging between word lines is also reduced. The metallization process can then be performed without worrying about the problem of word line bridging.

The exemplary embodiments described herein, and other examples that follow, may enable the memory process to be filled with small areas and effectively fill such areas in a relatively inexpensive and reliable manner. For example, a small space of a physical isolation trench formed in an active structure of a vertical channel memory array can be filled with ONO, a polysilicon layer and/or a hafnium oxide film. In the context of this illustrative embodiment, the ONO deposition may include oxygen Materials such as bismuth-tantalum nitride-ytterbium oxide, energy gap engineering 矽-yttria-tantalum nitride-BE-SONOS, nanocrystals and/or other possible storage media. Meanwhile, as the polycrystalline germanium layer, materials such as amorphous germanium, polycrystalline germanium, and/or single crystal germanium may be used. As the ruthenium oxide film, for example, a material such as high temperature oxidation, tetraethoxy decane (TEOS), isotopic vapor generation (ISSG), and/or other oxide film having a step coverage ability can be used.

Some embodiments of the present invention may provide a stylized interference mechanism that is encountered in memory arrays that are, for example, multi-level memory cells (MLCs). In this case, some embodiments may provide an isolation improvement between the active structures that can achieve charge storage (and its memory function).

Figure 5 shows a process flow diagram for forming a semiconductor structure in accordance with an exemplary embodiment. The method can include preparing a vertical channel memory structure to fill the physical isolation trench. The physical isolation trench is formed between the active structures to provide isolation therebetween, the active structure may extend in a first direction and have channels on opposite sides of the adjacent physical isolation trench. This method further includes using the ONO layer to fill the physical isolation trench.

In some embodiments, certain operations may be adjusted and further simplified as follows. Moreover, in some embodiments, additional selective operations may also be included (an example shows these operations as the dashed lines in Figure 5). It will be appreciated that each of the following adjustments, enhancements, or additional selective operations can be used alone or in combination with the operations previously described. In this case, for example, the method further includes patterning the word lines of the vertical channel memory structure. The word lines may extend in a second direction that is perpendicular to one of the first directions. The word line can extend above the active structure and the physical isolation trench and fill the corresponding portion of the access channel.

In some embodiments, wherein the patterned word lines are performed after the physical isolation trench fills to prevent word line bridging due to physical isolation trench opening conditions. In an exemplary embodiment, the filling of the physical isolation trench may include filling the physical isolation trench with ONO when forming the ONO layer. In such an example, filling the physical isolation trench with ONO during formation of the ONO layer can include performing a cleaning process prior to the reoxidation layer and performing a buried diffusion implant over the active structure and at the bottom of the channel. Thereafter, an ONO cleaning process can be performed prior to forming the ONO layer. In some cases, the use of ONO to fill the physical isolation trench during the formation of the ONO layer may include the use of yttrium oxide-tantalum nitride-yttria, energy gap engineering yttrium-yttria-yttrium nitride-yttrium oxide-yttrium (BE- SONOS) or nanocrystals are filled into the physical isolation trench.

In some embodiments, the filling of the physical isolation trench can include filling the physical isolation trench with an oxide film. In such an example, the use of an oxide film to fill the physical isolation trench may include the use of high temperature oxidation, tetraethoxy decane (TEOS) or isotopic vapor generation (ISSG). In some cases, the use of an oxide film to fill the physical isolation trench may include providing an oxide film to fill the physical isolation trench with a high density plasma deposited oxide over the active structure and the oxide film in the physical isolation trench.

In some embodiments, the filling of the physical isolation trenches can include filling the physical isolation trenches with a polysilicon crucible. In such an example, the use of a polysilicon crucible to fill the physical isolation trench may include the use of amorphous germanium, polycrystalline germanium or single crystal germanium. In an exemplary embodiment, filling the physical isolation trench with the polysilicon layer may include providing an oxide film over the active structure and the via, and then forming a polysilicon layer over the oxide film and filling into the physical isolation trench. A chemical dry etch process is then performed to etch back the polysilicon germanium layer in substantially all of the physical isolation trenches in the vertical channel memory structure. In some embodiments, the filling of the physical isolation trench with the polysilicon layer may further include performing a cleaning process before the reoxidation layer and performing burying diffusion over the active structure and at the bottom of the channel, and then forming an ONO layer. An ONO cleaning process was performed before.

As previously described, it may be desirable to integrate a vertical channel array with a planar channel perimeter in some cases. In an exemplary embodiment, vertical The channel array portion can be subjected to chemical mechanical polishing and tantalum nitride removal process processing to achieve a reverse tone defined by the vertical channel. Therefore, the dark tone of the array becomes a vertical channel. For a planar channel metal oxide half (MOS) device, current planarization techniques can be used to make the dark tone in the peripheral region into the active region.

Fig. 6 including Figs. 6A to 6B shows a side view (Fig. 6A) and a top view (Fig. 6B) of an intersection of a vertical channel array portion 450 and a peripheral portion 460 in the semiconductor device of an exemplary embodiment. In this vertical channel array portion 450, photoresist lithography and implantation operations can be performed to provide threshold voltage Vt control and suppression of hot carrier generation and breakdown. Thereafter, tantalum nitride deposition and yttrium oxide deposition are performed. Execution of the hard mask 480 prevents the tantalum nitride 470 from being damaged during subsequent spacer etching processes.

Figure 7 is a cross-sectional view showing the intersection of a vertical channel array portion 450 and a peripheral portion 460 in a semiconductor device after performing a peripheral oxide layer deposition and etching operation, which is used to open the space of the spacer. To define a physical isolation trench. Figure 8, including Figures 8A-8B, shows an exemplary embodiment that simultaneously defines a side view (Fig. 8A) and a top view (Fig. 8B) of the trench associated with the physical isolation trench and the surrounding trench. Accordingly, certain embodiments provide for the formation of trench structures (eg, physical isolation trenches 485 and perimeter trenches 486) simultaneously with vertical channel array portion 450 and a peripheral portion 460. As shown in FIG. 8A, a physical isolation trench 485 is formed between the dark-tuned regions in the vertical channel array portion 450, wherein the photoresist 490 is placed over a portion of the array adjacent the peripheral region 460.

As shown in FIG. 9, single or multiple layers of oxidized material 498 can be used to simultaneously fill any vertical channel array portion 450 and a physical isolation trench and/or shallow trench isolation in a peripheral portion 460. A shallow trench isolation CMP process can be performed, but stops when the tantalum nitride deposit 470 is reached to deposit tantalum nitride 470 Bare out. As shown in FIG. 10, the tantalum nitride deposit 470 can then be removed. Fig. 11 including Figs. 11A-11B shows a side view (Fig. 11A) and a top view (Fig. 11B) after the vertical channel 500 is formed, having an array of photoresist 492 applied to the peripheral portion 460 and the adjacent peripheral region 460. A portion of area 450 is above.

A vertical channel cleaning and re-oxidation layer is then applied to protect the sidewalls of the vertical channel 500 and enclose the physical isolation trench 485 (e.g., as previously described in Figures 1-5). Fig. 12, including Figs. 12A-12B, shows the side view (Fig. 12A) and the top view (Fig. 12B) of the buried diffusion (BD) region 510 after the buried diffusion (BD) lithography and the implantation process. Thereafter, as shown in FIG. 13 (e.g., as previously described with respect to vertical channel array portion 450 in FIGS. 1 through 5), ONO cleaning, deposition, densification, lithography, and etching processes are performed to provide ONO layer 520 in a vertical direction. Above the channel array portion 450. Thereafter, an ONO post-etch is performed in the peripheral region 460 to perform a plurality of photoresist lithography, implantation, and annealing processes for defining the well region and controlling the threshold voltage of the MOS transistor. In some embodiments, a gate oxide layer, a polysilicon deposition, and a tungsten germanium deposition operation may also be performed, followed by patterning and metallization of the word lines.

The above-described embodiments are merely illustrative of some of the process examples that may be used and are not intended to limit the invention. Thus in some embodiments, certain additional operations may be implemented. Moreover, in some embodiments, certain operations may be further adjusted or omitted. For example, in some cases, as shown in Figure 14, there is no physical isolation trench (eg, by skipping the spacer and the physical isolation trench etch process). In some embodiments, both MOS and polysilicon can be used to help flow current. The resistor is therefore a generic term for MOS and polysilicon in a circuit arrangement. Further, as described earlier, the dark tone can be used as a general term for the vertical channel of the vertical channel array portion, and as a general term for the active portion of the peripheral portion.

Figure 15 shows an example method of integrating a vertical channel array with a planar channel perimeter. The method includes forming a vertical channel memory array in a first portion of a semiconductor device having a dim tone corresponding to a region of the vertical channel to be formed. The method also includes forming a planar perimeter around a second portion of the semiconductor device, the second portion having a dark tint corresponding to one of the active structural regions of the planar perimeter. In some embodiments, the method further includes simultaneously forming a trench structure in the first region and the second region. In an exemplary embodiment, forming the vertical channel memory array and forming the planar perimeter each further includes providing tantalum nitride deposited in the first portion and the second portion such that the trench structure is formed between the deposited nitrogen Between phlegm. In some cases, forming the vertical channel memory array and forming the planar perimeter each further includes providing a yttrium oxide material to fill the trench structure and removing the nitriding between the exposed portions of the yttria material Hey. In an exemplary embodiment, forming the vertical channel memory array includes forming a vertical channel extending in a first direction that is substantially parallel to a boundary defining a boundary between the first portion and the second portion. In some embodiments, forming the vertical channel memory array includes forming a word line extending longitudinally in a second direction that is substantially perpendicular to the first direction and into and out of the vertical channel.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such equivalents and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

10‧‧‧Active structure

13‧‧‧Oxide layer

15, 106, 236‧‧ ‧ oxide layer

18, 240‧‧‧ High Density Plasma (HDP) Sedimentary Layer

20‧‧‧Physical isolation trench

22‧‧‧ channel

26‧‧‧ Buried Diffusion Planting (BD) Area

28‧‧‧ character line

30, 110, 244, 520‧‧‧ONO layers

100‧‧‧thin oxide layer

102‧‧‧Polysilicon layer

104‧‧‧Polysilicon cushion

200‧‧‧Oxide layer

226‧‧‧Bottom buried diffusion implant (BBD) area

228‧‧‧Top Buried Diffusion Planting (TBD) Area

450‧‧‧Vertical channel array section

460‧‧‧ peripheral parts

470‧‧‧ tantalum nitride layer

480‧‧‧hard mask

485‧‧‧Physical isolation trench

486‧‧‧ surrounding ditches

490, 492‧‧‧ photoresist layer

498‧‧‧Oxidized materials

500‧‧‧ channel

510‧‧‧buried diffusion (BD) area

530‧‧‧ Well Area

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

Figure 1 includes Figures 1A-1E showing an operational diagram of an exemplary embodiment that can be used to fill a physical isolation trench.

Figure 2 is a top view of a vertical channel array in accordance with an exemplary embodiment that creates the risk of word line bridges between adjacent word lines.

Figure 3, including Figures 3A-3E, shows an operational diagram that can be used to fill a physical isolation trench in accordance with an exemplary embodiment of the present invention, which can reduce the risk of physically isolating the trench opening.

Figure 4, including Figures 4A-4C, shows an operational diagram that can be used to fill a physical isolation trench in accordance with an exemplary embodiment of the present invention, which can reduce the risk of physically isolating the trench opening.

Figure 5 shows a process flow diagram for forming a semiconductor structure in accordance with an exemplary embodiment.

Fig. 6 includes a cross-sectional view (Fig. 6A) and a top view (Fig. 6B) showing a portion of a vertical channel array portion and a peripheral portion in a semiconductor device of an exemplary embodiment, as shown in Figs. 6A to 6B.

Figure 7 is a cross-sectional view showing the intersection of a vertical channel array portion and a peripheral portion in a semiconductor device after performing a peripheral oxide layer deposition and etching operation, in an exemplary embodiment.

Figure 8 includes Figures 8A-8B showing a cross-sectional view (Fig. 8A) and a top view (Fig. 8B) of an exemplary embodiment simultaneously defining trenches associated with physical isolation trenches and shallow trench isolation.

Figure 9 shows a cross-sectional view of a physical isolation trench and surrounding trenches using oxides in accordance with an exemplary embodiment.

Figure 10 shows a cross-sectional view of the removal of tantalum nitride in accordance with an exemplary embodiment.

Figure 11 includes sections 11A-11B showing a cross-sectional view (Fig. 8A) and a top view (Fig. 8B) of a vertical channel formed by an exemplary embodiment.

Figure 12 includes sections 12A-12B showing a cross-sectional view (Fig. 12A) and a top view (Fig. 12B) of an exemplary embodiment of the closed solid isolation trench and the formation of the buried diffusion region.

Figure 13 is a cross-sectional view showing an exemplary embodiment prior to patterning and metallization of word lines.

Figure 14 is a cross-sectional view showing a vertical channel array portion and a peripheral portion of a semiconductor device having no physical isolation trenches, according to an exemplary embodiment.

Figure 15 shows an example method of integrating a vertical channel array with a planar channel perimeter.

10‧‧‧Active structure

20‧‧‧Physical isolation trench

26‧‧‧ Buried Diffusion Planting (BD) Area

28‧‧‧ character line

30‧‧‧ONO layer

Claims (19)

A method of fabricating a semiconductor structure, the method comprising: preparing a vertical channel memory structure to fill a physical isolation trench defined therebetween, the physical isolation trench being defined between adjacent active structures and in a first direction Extending, the active structure also defines a channel located adjacent to the active structure on opposite sides of the physical isolation trench; applying a dielectric material to fill the physical isolation trench; and configuring a buried diffusion implant material over the active structure and The bottom of the equal channel. The method of claim 1, further comprising: patterning word lines on the vertical channel memory structure, the word lines being parallel to each other in a second direction substantially perpendicular to the first direction Extending, the word lines extend over the active structure and the physical isolation trench and fill corresponding channel portions. The method of claim 2, wherein the patterned word line is performed after filling the physical isolation trench to prevent word line bridging of the word line due to physical isolation of the trench opening condition. The method of claim 1, wherein the dielectric material is a yttria-tantalum nitride-anthracene oxide (ONO) layer. The method of claim 4, wherein the filling the physical isolation trench comprises filling the physical isolation trench with the ONO layer when the yttria-tantalum nitride-anthracene oxide (ONO) layer is formed. The method of claim 5, wherein filling the physical isolation trench with the ONO layer when the yttria-tantalum nitride-anthracene oxide (ONO) layer is formed further comprises performing a cleaning process for performing a re-oxidation layer Previously, a buried diffusion was implanted over the active structure and at the bottom of the channel, and then an ONO cleaning process was performed prior to forming the ONO layer. The method of claim 5, wherein the solid isolation trench is filled with the ONO layer when the yttria-tantalum nitride-yttria (ONO) layer is formed to comprise yttrium oxide-yttria-yttrium oxide At least one of the energy gap engineering 矽-矽-矽-矽 矽-矽-矽 (BE-SONOS) or nano crystals is filled into the physical isolation trench. The method of claim 1, wherein filling the physical isolation trench comprises filling the physical isolation trench with yttrium oxide. The method of claim 8, wherein the solid isolation trench filled with yttrium oxide comprises at least one of high temperature oxidation, tetraethoxy decane (TEOS) or isotopic vapor generation (ISSG) filled into the physical isolation trench Inside. The method of claim 8, wherein the solid isolation trench filled with yttrium oxide comprises a yttrium oxide film filled in the physical isolation trench with high density plasma deposition oxide over the active structure and an oxide film In the physical isolation trench. The method of claim 1, wherein filling the physical isolation trench comprises filling the physical isolation trench with a polysilicon layer. The method of claim 11, wherein filling the physical isolation trench with a polysilicon layer comprises filling at least one of an amorphous germanium, a polycrystalline germanium or a single crystal germanium into the physical isolation trench. The method of claim 11, wherein filling the physical isolation trench with a polysilicon layer comprises: providing a yttrium oxide film over the active structure and the channel, and then forming a polysilicon layer over the yttrium oxide film. And filling the physical isolation trench; performing a chemical dry etching process to etch back the polysilicon germanium layer in substantially all portions of the physical isolation trench in the vertical channel memory structure. The method of claim 11, wherein filling the physical isolation trench with a polysilicon layer further comprises performing a cleaning process before performing the reoxidation layer, and performing burying diffusion on the active structure and the channel At the bottom, and thereafter, an ONO cleaning process is performed prior to forming the ONO layer. A vertical channel memory structure includes: at least one active structure extending in a first direction, the active structures being placed adjacent to each other and having a physical isolation trench therebetween, the physical isolation trench also extending in the first direction; The channel is disposed adjacent to a side of the active structure, and is located adjacent to the active structure on opposite sides of the physical isolation trench; a filling material is filled in the physical isolation trench, and is combined with applying a multilayer dielectric layer, a polysilicon layer and And/or an oxide film; and a buried diffusion implant material disposed above the active structure and at the bottom of the channels. The vertical channel memory structure as described in claim 15 of the patent application further includes: Patterning word lines extending parallel to each other in a second direction substantially perpendicular to the first direction, the word lines extending over the active structure and the physical isolation trench and filling corresponding Channel section. The vertical channel memory structure according to claim 15, wherein the filling material comprises yttrium oxide-tantalum nitride-yttria, energy gap engineering yttrium-yttria-yttrium nitride-yttrium oxide-yttrium (BE-SONOS) Or at least one of the nanocrystals is filled into the physical isolation trench when the multilayer dielectric layer is applied. The vertical channel memory structure of claim 15, wherein the filler material comprises at least one of high temperature oxidation, tetraethoxy decane (TEOS) or isotopic vapor generation (ISSG) for applying the multilayer dielectric layer. Previously deposited in the physical isolation trench. The vertical channel memory structure of claim 15 wherein the filler material comprises amorphous germanium, polycrystalline germanium or single crystal germanium deposited in the physical isolation trench prior to application of the multilayer dielectric layer.