TWI472158B - Starting circuit for crystal oscillator - Google Patents
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- TWI472158B TWI472158B TW101105606A TW101105606A TWI472158B TW I472158 B TWI472158 B TW I472158B TW 101105606 A TW101105606 A TW 101105606A TW 101105606 A TW101105606 A TW 101105606A TW I472158 B TWI472158 B TW I472158B
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Description
本發明係有關於起振電路的設計，尤指一種與訊號處理電路共用連接墊的起振電路。The present invention relates to the design of a vibrating circuit, and more particularly to a vibrating circuit that shares a connection pad with a signal processing circuit.
在傳統的數位電路設計中，由於晶體振盪器與數位電路本身係使用不同的電源、接地路徑、靜電防護電路(electrostatic discharge，ESD)以及連接墊(pad)，所以無論是在晶片的大小、封裝的繞線以及針腳的數量上都受到很大的影響，也因此提高晶片的製作成本以及封裝成本。In the traditional digital circuit design, since the crystal oscillator and the digital circuit itself use different power sources, ground paths, electrostatic discharge (ESD) and pad, it is in the size and package of the chip. The number of windings and the number of stitches are greatly affected, thereby increasing the manufacturing cost of the wafer and the cost of packaging.
舉例來說，相較於其他電路元件，由於連接墊在晶片中佔有相對大的面積，因此在電路設計中使用越多的連接墊，就會佔用越大的晶片面積，換句話說，真正可以用來實作電路的晶片面積也隨之減少。For example, compared to other circuit components, since the connection pads occupy a relatively large area in the wafer, the more connection pads used in the circuit design, the larger the wafer area is occupied, in other words, The area of the wafer used to implement the circuit is also reduced.
因此，有需要一種整合晶體振盪器與數位電路之連接墊的設計，以降低晶片的製作成本與封裝的成本。Therefore, there is a need for a design that integrates the connection pads of a crystal oscillator and a digital circuit to reduce the cost of fabrication and packaging of the wafer.
依據本發明之實施例，其提出一種與訊號處理電路共用連接墊的起振電路，以解決上述之問題。According to an embodiment of the present invention, a vibrating circuit for sharing a connection pad with a signal processing circuit is proposed to solve the above problems.
依據本發明之實施例，其揭示一種起振電路。該起振電路包含有一起振單元以及至少一連接墊。該起振單元用來起振一可振盪元件，包含有複數個開關以及一靜電防護電路。該複數個開關用來根據一控制訊號來控制該起振單元在一第一操作模式與一第二操作模式之間進行切換。該靜電防護電路用來提供靜電防護。該連接墊，耦接於該起振單元與至少一訊號處理電路，用來於該起振單元操作於該第一操作模式下時，作為該起振電路之一輸出端使用，以及於該起振單元操作於該第二操作模式下時，作為該訊號處理電路之一輸入輸出端使用。In accordance with an embodiment of the present invention, a vibrating circuit is disclosed. The oscillating circuit includes a vibration unit and at least one connection pad. The oscillating unit is configured to oscillate an oscillatable element, and includes a plurality of switches and an electrostatic protection circuit. The plurality of switches are configured to control the vibrating unit to switch between a first operating mode and a second operating mode according to a control signal. This electrostatic protection circuit is used to provide electrostatic protection. The connection pad is coupled to the oscillating unit and the at least one signal processing circuit for use as an output end of the oscillating circuit when the oscillating unit is operated in the first operating mode, and When the vibration unit operates in the second operation mode, it is used as one of the input and output ends of the signal processing circuit.
透過連接墊的共用，本發明可大幅減少晶片面積，並降低繞線與針腳的數量，進而有效地減少晶片生產與封裝的成本。Through the sharing of the connection pads, the invention can greatly reduce the wafer area and reduce the number of windings and pins, thereby effectively reducing the cost of wafer production and packaging.
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解，硬體製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。另外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接於一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that hardware manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.
請參考第1圖，第1圖為本發明起振電路之一實施例的示意圖。起振電路100包含有(但不侷限於)一起振單元110以及至少一連接墊(例如一第一連接墊122與一第二連接墊124)。起振單元110係用來起振一可振盪元件140(例如，一石英器)，並包含有(但不侷限於)複數個開關112、114、116、118以及一靜電防護電路120。開關112、114、116、118用來根據一控制訊號EN來控制起振單元110在一第一操作模式與一第二操作模式之間進行切換。靜電防護電路120用來提供靜電防護。連接墊(例如第二連接墊124)耦接於起振單元110與一訊號處理電路130間，當起振單元110操作於該第一操作模式下時，作為起振單元110之一輸出端使用，並且當起振單元110操作於該第二操作模式下時，用來作為訊號處理電路130之一輸入/輸出端使用。請注意，在本實施例中，訊號處理電路130是一數位電路，且開關112、114、116、118為金氧半場效電晶體開關，其中，開關112、114與116是互補式金氧半場效電晶體(complementary MOS，CMOS)開關，而開關118則是N通道金氧半場效電晶體開關(NMOS)，然而，此僅作為範例說明之用，本發明不以此為限。此外，為了簡潔起見，第1圖僅繪示出一個訊號處理電路130，然而，於另一實施例中，另一連接墊(例如第一連接墊122)亦可用以耦接起振單元110與另一訊號處理電路(未顯示)，因此，當起振單元110操作於該第一操作模式下時，作為起振單元110之另一輸出端使用，而當起振單元110操作於該第二操作模式下時，則作為該另一訊號處理電路之一輸入/輸出端使用。Please refer to FIG. 1 , which is a schematic diagram of an embodiment of a vibrating circuit of the present invention. The oscillating circuit 100 includes, but is not limited to, a vibration unit 110 and at least one connection pad (for example, a first connection pad 122 and a second connection pad 124). The oscillating unit 110 is configured to oscillate an oscillatable element 140 (eg, a quartz) and includes, but is not limited to, a plurality of switches 112, 114, 116, 118 and an electrostatic protection circuit 120. The switches 112, 114, 116, 118 are used to control the start-up unit 110 to switch between a first mode of operation and a second mode of operation based on a control signal EN. The static electricity protection circuit 120 is used to provide electrostatic protection. The connection pad (for example, the second connection pad 124) is coupled between the excitation unit 110 and a signal processing circuit 130. When the vibration unit 110 is operated in the first operation mode, it is used as an output end of the vibration unit 110. And when the oscillating unit 110 is operated in the second operation mode, it is used as an input/output terminal of the signal processing circuit 130. Please note that in this embodiment, the signal processing circuit 130 is a digital circuit, and the switches 112, 114, 116, and 118 are gold-oxygen half-field transistor switches, wherein the switches 112, 114, and 116 are complementary metal oxide half fields. The switch 218 is an N-channel MOS field-effect transistor switch (NMOS). However, this is for illustrative purposes only, and the invention is not limited thereto. In addition, for the sake of brevity, only one signal processing circuit 130 is shown in FIG. 1 . However, in another embodiment, another connection pad (eg, the first connection pad 122 ) may be coupled to the vibration unit 110 . And another signal processing circuit (not shown), therefore, when the oscillating unit 110 is operated in the first operation mode, it is used as another output end of the oscillating unit 110, and when the oscillating unit 110 is operated at the In the second operation mode, it is used as one of the input/output terminals of the other signal processing circuit.
在本實施例中，當開關112導通時，第一連接墊122透過一第一端點E1耦接於一電阻R1 ；當開關114導通時，電阻R1 耦接於一電阻R2 ；以及當開關116導通時，電阻R2 則透過一第二端點E2耦接於第二連接墊124。進一步來說，開關112、114與116分別具有一第一連接端N1、一第二連接端N2、一第一控制端C1以及一第二控制端C2，且開關118包含有一第一連接端N1、一第二連接端N2以及一控制端C。開關112的第一連接端N1耦接於第一連接墊122，且開關112的第二連接端N2耦接於第一端點E1，以用來選擇性地連接第一連接墊122與第一端點E1。開關114的第一連接端N1耦接於電阻R1 與電阻R2 之間，用來選擇性地連接第一端點E1與第二端點E2。開關116的第一連接端N1耦接於第二端點E2，且開關116的第二連接端N2耦接於第二連接墊124，用來選擇性地連接第二端點E2與第二連接墊124。開關118的第一連接端N1耦接於第一端點E1，且開關118的第二連接端N2耦接於一第一參考電壓(例如，接地電壓GND)，用來選擇性地連接第一參考電壓GND與第一端點E1。In this embodiment, when the switch 112 is turned on, the first connection pad 122 is coupled to a resistor R 1 through a first terminal E1; when the switch 114 is turned on, the resistor R 1 is coupled to a resistor R 2 ; When the switch 116 is turned on, the resistor R 2 is coupled to the second connection pad 124 through a second end point E2. Further, the switches 112, 114, and 116 respectively have a first connection end N1, a second connection end N2, a first control end C1, and a second control end C2, and the switch 118 includes a first connection end N1. a second connection end N2 and a control end C. The first connection end N1 of the switch 112 is coupled to the first connection pad 122, and the second connection end N2 of the switch 112 is coupled to the first end point E1 for selectively connecting the first connection pad 122 with the first Endpoint E1. The first terminal N1 of the switch 114 is coupled between the resistor R 1 and the resistor R 2 for selectively connecting the first terminal E1 and the second terminal E2. The first connection end N1 of the switch 116 is coupled to the second end point E2, and the second connection end N2 of the switch 116 is coupled to the second connection pad 124 for selectively connecting the second end point E2 with the second connection. Pad 124. The first connection end N1 of the switch 118 is coupled to the first end point E1, and the second connection end N2 of the switch 118 is coupled to a first reference voltage (eg, the ground voltage GND) for selectively connecting the first The reference voltage GND is coupled to the first terminal E1.
此外，開關112、114與116的第一控制端C1皆耦接於控制訊號EN，開關112、114與116的第二控制端C2以及開關118的控制端C皆耦接於控制訊號EN之一反向訊號ENB。如此一來，控制訊號EN控制開關112、開關114以及開關116為開啟，且控制開關118為關閉時(亦即，控制訊號EN指示開啟，且反向訊號ENB指示關閉時)，起振單元110便會操作於該第一操作模式下；以及當控制訊號EN控制開關112、開關114以及開關116為關閉，且控制開關118為開啟時(亦即，控制訊號EN指示關閉，且反向訊號ENB指示開啟時)，起振單元110則會操作於該第二操作模式下。The first control terminal C1 of the switches 112, 114 and 116 is coupled to the control signal EN, and the second control terminal C2 of the switches 112, 114 and 116 and the control terminal C of the switch 118 are coupled to one of the control signals EN. Reverse signal ENB. In this way, when the control signal EN control switch 112, the switch 114, and the switch 116 are turned on, and the control switch 118 is turned off (that is, when the control signal EN is turned on, and the reverse signal ENB is turned off), the vibrating unit 110 is turned on. Operating in the first mode of operation; and when the control signal EN controls the switch 112, the switch 114, and the switch 116 to be off, and the control switch 118 is on (ie, the control signal EN indicates off, and the reverse signal ENB When the indication is turned on, the vibrating unit 110 operates in the second mode of operation.
靜電防護電路120包含有一第一電晶體M1 以及一第二電晶體M2 。電晶體M1 與電晶體M2 分別具有一第一連接端N1、一第二連接端N2以及一控制端C。電晶體M1 的第一連接端N1耦接於一第二參考電壓(例如，供應電壓VDD)，電晶體M1 的第二連接端N2耦接於第二端點E2，電晶體M1 的控制端C耦接於第一端點E1。電晶體M2 的第一連接端N1耦接於第二端點E2，電晶體M2 的第二連接端N2耦接於第一參考電壓GND，電晶體M2 的控制端C耦接於第一端點E1。請注意，靜電防護電路120在實作上需符合靜電防護標準的規範，以使得起振電路100以及訊號處理電路130中的靜電荷可透過靜電防護電路120充電/放電的操作來得到消除。另外，由於靜電防護電路120係透過電路中之寄生電容(亦即，不是透過訊號的路徑)來進行充電/放電的操作，因此，開關112～118的開啟/關閉與靜電防護電路120的運作無關，換句話說，當起振單元110操作於該第二操作模式下時，靜電防護電路120仍然可以對訊號處理電路130提供靜電防護。The static electricity protection circuit 120 includes a first transistor M 1 and a second transistor M 2 . The transistor M 1 and the transistor M 2 respectively have a first connection end N1, a second connection end N2 and a control end C. The first connection end N1 of the transistor M 1 is coupled to a second reference voltage (eg, the supply voltage VDD), and the second connection end N2 of the transistor M 1 is coupled to the second end point E2, the transistor M 1 The control terminal C is coupled to the first endpoint E1. The first connection end N1 of the transistor M 2 is coupled to the second end point E2, the second connection end N2 of the transistor M 2 is coupled to the first reference voltage GND, and the control end C of the transistor M 2 is coupled to the One endpoint E1. Please note that the ESD protection circuit 120 is required to comply with the specifications of the ESD protection standard so that the static charge in the oscillation circuit 100 and the signal processing circuit 130 can be eliminated by the operation of charging/discharging the ESD protection circuit 120. In addition, since the static electricity protection circuit 120 performs the charging/discharging operation through the parasitic capacitance in the circuit (that is, the path that does not pass through the signal), the opening/closing of the switches 112 to 118 is independent of the operation of the static electricity protection circuit 120. In other words, when the vibrating unit 110 is operated in the second mode of operation, the ESD protection circuit 120 can still provide ESD protection to the signal processing circuit 130.
請參考第2圖，第2圖為第1圖所示之訊號處理電路130之一實施例的示意圖。訊號處理電路230可用以實現第1圖中的訊號處理電路130，並包含有一邏輯單元232、一接收單元234以及一緩衝單元236，其中緩衝單元236耦接於邏輯單元232以及接收單元234。邏輯單元232具有一控制端，用來接收一控制訊號OEN，並據以控制邏輯單元232是否致能。接收單元234具有一控制端，用來接收一控制訊號IE，並據以控制接收單元234是否致能。緩衝單元136透過第二連接墊124耦接於起振電路100，用來暫存透過邏輯單元232輸出的訊號。當控制訊號OEN開啟邏輯單元232，且控制訊號IE關閉接收單元234時，此時訊號處理電路230操作在輸出模式。當控制訊號OEN關閉邏輯單元232，且控制訊號IE開啟接收單元234時，此時訊號處理電路230操作在輸入模式。請注意，控制訊號OEN與控制訊號IE需適當地搭配控制訊號EN來使用，舉例來說，當起振單元110操作於該第一操作模式下時，且訊號處理電路230不致能(亦即，控制訊號OEN與控制訊號IE皆關閉相對應的邏輯單元232與接收單元234)；另一方面，當起振單元110操作於該第二操作模式下時，訊號處理電路230可操作在輸出模式或輸入模式。然而，訊號處理電路230的設計僅作為範例說明之用，本發明不以此為限。本發明之精神在於訊號處理電路230可配合控制訊號EN來致能/不致能，以配合起振單元110的操作，凡依第2圖所述之內容所作出之變化與修飾，皆應屬本發明之範圍。Please refer to FIG. 2, which is a schematic diagram of an embodiment of the signal processing circuit 130 shown in FIG. The signal processing circuit 230 can be used to implement the signal processing circuit 130 in FIG. 1 and includes a logic unit 232, a receiving unit 234, and a buffer unit 236. The buffer unit 236 is coupled to the logic unit 232 and the receiving unit 234. The logic unit 232 has a control terminal for receiving a control signal OEN and controlling whether the logic unit 232 is enabled. The receiving unit 234 has a control terminal for receiving a control signal IE and accordingly controlling whether the receiving unit 234 is enabled. The buffer unit 136 is coupled to the oscillating circuit 100 through the second connection pad 124 for temporarily storing the signal output through the logic unit 232. When the control signal OEN turns on the logic unit 232, and the control signal IE turns off the receiving unit 234, then the signal processing circuit 230 operates in the output mode. When the control signal OEN turns off the logic unit 232 and the control signal IE turns on the receiving unit 234, the signal processing circuit 230 operates in the input mode. Please note that the control signal OEN and the control signal IE need to be properly used with the control signal EN. For example, when the vibrating unit 110 is operated in the first operation mode, and the signal processing circuit 230 is disabled (ie, The control signal OEN and the control signal IE both turn off the corresponding logic unit 232 and the receiving unit 234); on the other hand, when the vibration unit 110 operates in the second operation mode, the signal processing circuit 230 can operate in the output mode or Input mode. However, the design of the signal processing circuit 230 is for illustrative purposes only, and the invention is not limited thereto. The spirit of the present invention is that the signal processing circuit 230 can be enabled/disabled in conjunction with the control signal EN to cooperate with the operation of the vibrating unit 110. Any changes and modifications made in accordance with the contents of FIG. 2 should belong to the present invention. The scope of the invention.
請參考第3圖，第3圖為本發明起振電路搭配訊號處理電路使用之一第一實施例的示意圖。在第3圖中，控制訊號EN會處於開啟狀態，而控制訊號OEN與控制訊號IE皆處於關閉狀態，此時，起振單元110操作於該第一操作模式下，且訊號處理電路230不致能，因此，起振單元110會用來起振可振盪元件140，且連接墊(例如第二連接墊124)用來作為起振電路100之輸出端來使用。Please refer to FIG. 3, which is a schematic diagram of a first embodiment of the use of the oscillating circuit and the signal processing circuit of the present invention. In the third figure, the control signal EN is turned on, and the control signal OEN and the control signal IE are both in the off state. At this time, the vibrating unit 110 operates in the first operation mode, and the signal processing circuit 230 is disabled. Therefore, the vibrating unit 110 is used to oscillate the oscillatable element 140, and a connection pad (for example, the second connection pad 124) is used as the output end of the oscillating circuit 100.
請參考第4圖，第4圖為本發明起振電路搭配訊號處理電路使用之一第二實施例的示意圖。在第4圖中，控制訊號OEN處於開啟狀態，而控制訊號EN與控制訊號IE皆處於關閉狀態，此時，起振單元110操作於該第二操作模式下，且訊號處理電路230致能且操作在輸出模式之下，故連接墊(例如第二連接墊124)便用來作為訊號處理電路230之訊號輸出端來使用。Please refer to FIG. 4, which is a schematic diagram of a second embodiment of the use of the oscillating circuit and the signal processing circuit of the present invention. In the fourth figure, the control signal OEN is in the on state, and the control signal EN and the control signal IE are both in the off state. At this time, the vibrating unit 110 operates in the second operation mode, and the signal processing circuit 230 is enabled. The operation is in the output mode, so that a connection pad (for example, the second connection pad 124) is used as the signal output terminal of the signal processing circuit 230.
請參考第5圖，第5圖為本發明起振電路搭配訊號處理電路使用之一第三實施例的示意圖。在第5圖中，控制訊號IE處於開啟狀態，而控制訊號EN與控制訊號OEN皆處於關閉狀態，此時，起振單元110操作於該第二操作模式下，且訊號處理電路230致能且操作在輸入模式之下，故連接墊(例如第二連接墊124)便用來作為訊號處理電路230之訊號輸入端來使用。Please refer to FIG. 5, which is a schematic diagram of a third embodiment of the use of the oscillating circuit with signal processing circuit of the present invention. In the fifth figure, the control signal IE is in the on state, and the control signal EN and the control signal OEN are both in the off state. At this time, the vibrating unit 110 operates in the second operation mode, and the signal processing circuit 230 is enabled. The operation is in the input mode, so that a connection pad (e.g., the second connection pad 124) is used as the signal input terminal of the signal processing circuit 230.
綜上所述，本發明起振電路的連接墊設計可使得一晶體振盪器與一數位電路共用連接墊，進而大幅減少晶片面積，且降低繞線與針腳的數量，因此可以有效地減少晶片生產與封裝的成本。In summary, the connection pad design of the oscillation circuit of the present invention can make a crystal oscillator share a connection pad with a digital circuit, thereby greatly reducing the wafer area and reducing the number of windings and pins, thereby effectively reducing wafer production. The cost with the package.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100．．．起振電路100. . . Start-up circuit
110．．．起振單元110. . . Starting unit
112、114、116、118．．．開關112, 114, 116, 118. . . switch
120．．．靜電防護電路120. . . Electrostatic protection circuit
122．．．第一連接墊122. . . First connection pad
124．．．第二連接墊124. . . Second connection pad
130、230．．．訊號處理電路130, 230. . . Signal processing circuit
140．．．可振盪元件140. . . Oscillable component
232．．．邏輯單元232. . . Logical unit
234．．．接收單元234. . . Receiving unit
236．．．緩衝單元236. . . Buffer unit
第1圖為本發明起振電路之一實施例的示意圖。Fig. 1 is a schematic view showing an embodiment of a vibrating circuit of the present invention.
第2圖為第1圖中之訊號處理電路之一實施例的示意圖。Figure 2 is a schematic diagram of one embodiment of the signal processing circuit of Figure 1.
第3圖為本發明起振電路搭配訊號處理電路使用之一第一實施例的示意圖。FIG. 3 is a schematic view showing a first embodiment of the use of the oscillating circuit and the signal processing circuit of the present invention.
第4圖為本發明起振電路搭配訊號處理電路使用之一第二實施例的示意圖。Fig. 4 is a schematic view showing a second embodiment of the use of the oscillating circuit and the signal processing circuit of the present invention.
第5圖為本發明起振電路搭配訊號處理電路使用之一第三實施例的示意圖。Fig. 5 is a schematic view showing a third embodiment of the use of the oscillating circuit with signal processing circuit of the present invention.
100．．．起振電路100. . . Start-up circuit
110．．．起振單元110. . . Starting unit
112、114、116、118．．．開關112, 114, 116, 118. . . switch
120．．．靜電防護電路120. . . Electrostatic protection circuit
122．．．第一連接墊122. . . First connection pad
124．．．第二連接墊124. . . Second connection pad
130．．．訊號處理電路130. . . Signal processing circuit
140．．．可振盪元件140. . . Oscillable component
Claims (5)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101105606A TWI472158B (en) | 2012-02-21 | 2012-02-21 | Starting circuit for crystal oscillator |
| CN2012102132294A CN103259491A (en) | 2012-02-21 | 2012-06-26 | Oscillation starting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101105606A TWI472158B (en) | 2012-02-21 | 2012-02-21 | Starting circuit for crystal oscillator |
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|---|---|
| TW201336231A TW201336231A (en) | 2013-09-01 |
| TWI472158B true TWI472158B (en) | 2015-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW101105606A TWI472158B (en) | 2012-02-21 | 2012-02-21 | Starting circuit for crystal oscillator |
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| TW (1) | TWI472158B (en) |
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| CN113437950B (en) * | 2021-07-29 | 2023-12-01 | 广东华芯微特集成电路有限公司 | Low-power consumption architecture |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW439351B (en) * | 1999-04-26 | 2001-06-07 | Faraday Tech Corp | The universal crystal oscillation input/output circuit for enhanced charge device mode (CDM) electrostatic discharge (ESD) protection |
| US6320473B1 (en) * | 1999-09-30 | 2001-11-20 | Stmicroelectronics, Inc. | Integrated oscillator circuit apparatus with capacitive coupling for reducing start-up voltage |
| TW591888B (en) * | 2001-08-13 | 2004-06-11 | Em Microelectronic Marin Sa | Oscillator circuit with an inverter amplifier having reduced consumption |
| US20080018515A1 (en) * | 2006-07-21 | 2008-01-24 | Microchip Technology Incorporated | Integrated Circuit Device Having at Least One Bond Pad With a Selectable Plurality of Input-Output Functionalities |
| TW201012046A (en) * | 2008-09-12 | 2010-03-16 | Phison Electronics Corp | Oscillator and driving circuit and oscillation method thereof |
| TW201106609A (en) * | 2009-08-14 | 2011-02-16 | Realtek Semiconductor Corp | Crystal oscillator |
| TW201134102A (en) * | 2010-03-31 | 2011-10-01 | Silicon Motion Inc | Osicillatting signal generatting device and related method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006295362A (en) * | 2005-04-07 | 2006-10-26 | Matsushita Electric Ind Co Ltd | Applied voltage control circuit for voltage controlled oscillator circuit |
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2012
- 2012-02-21 TW TW101105606A patent/TWI472158B/en active
- 2012-06-26 CN CN2012102132294A patent/CN103259491A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW439351B (en) * | 1999-04-26 | 2001-06-07 | Faraday Tech Corp | The universal crystal oscillation input/output circuit for enhanced charge device mode (CDM) electrostatic discharge (ESD) protection |
| US6320473B1 (en) * | 1999-09-30 | 2001-11-20 | Stmicroelectronics, Inc. | Integrated oscillator circuit apparatus with capacitive coupling for reducing start-up voltage |
| TW591888B (en) * | 2001-08-13 | 2004-06-11 | Em Microelectronic Marin Sa | Oscillator circuit with an inverter amplifier having reduced consumption |
| US20080018515A1 (en) * | 2006-07-21 | 2008-01-24 | Microchip Technology Incorporated | Integrated Circuit Device Having at Least One Bond Pad With a Selectable Plurality of Input-Output Functionalities |
| TW201012046A (en) * | 2008-09-12 | 2010-03-16 | Phison Electronics Corp | Oscillator and driving circuit and oscillation method thereof |
| TW201106609A (en) * | 2009-08-14 | 2011-02-16 | Realtek Semiconductor Corp | Crystal oscillator |
| TW201134102A (en) * | 2010-03-31 | 2011-10-01 | Silicon Motion Inc | Osicillatting signal generatting device and related method |
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| Publication number | Publication date |
|---|---|
| CN103259491A (en) | 2013-08-21 |
| TW201336231A (en) | 2013-09-01 |
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