TWI471929B - Plasma etching equipment and method of etching a wafer - Google Patents

Plasma etching equipment and method of etching a wafer Download PDF

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TWI471929B
TWI471929B TW97126446A TW97126446A TWI471929B TW I471929 B TWI471929 B TW I471929B TW 97126446 A TW97126446 A TW 97126446A TW 97126446 A TW97126446 A TW 97126446A TW I471929 B TWI471929 B TW I471929B
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wafer
plasma
gas
chamber
etching
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TW97126446A
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TW200919580A (en
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Kwan Goo Rha
Jung Hee Lee
Chul Hee Jang
Gil Hun Lee
Young Ki Han
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Sosul Co Ltd
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Priority claimed from KR1020070069704A external-priority patent/KR101372356B1/en
Priority claimed from KR1020070069705A external-priority patent/KR20090006401A/en
Priority claimed from KR1020070076695A external-priority patent/KR101423554B1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)

Description

電漿蝕刻設備與蝕刻晶圓之方法Plasma etching apparatus and method of etching wafer

本發明係關於一種電漿蝕刻設備以及一種蝕刻晶圓之方法,更具體而言,係關於一種電漿蝕刻設備以及一種蝕刻一晶圓以自該晶圓之一斜面區域移除薄層及微粒之方法。The present invention relates to a plasma etching apparatus and a method of etching a wafer, and more particularly to a plasma etching apparatus and an etching of a wafer to remove thin layers and particles from a beveled area of the wafer The method.

裝置或電路圖案一般不形成於晶圓之邊緣區域中,乃因邊緣區域係供傳送晶圓之用,且該邊緣區域被稱為斜面區域。然而,於用於在晶圓上形成半導體裝置及電路圖案之製造製程中,非所欲之層或微粒可沉積於晶圓之斜面區域上。若不從晶圓之斜面區域移除該等非所欲之層或微粒即繼續進行用於形成半導體裝置及電路圖案之製造製程,則可造成諸多問題:舉例而言,晶圓可發生變形、因該等非所欲之層或微粒可於後續製程中造成缺陷而導致製造良率(yield)降低、或者可致使難以對齊晶圓。The device or circuit pattern is typically not formed in the edge regions of the wafer because the edge regions are for transporting the wafer and the edge regions are referred to as bevel regions. However, in a fabrication process for forming semiconductor devices and circuit patterns on a wafer, undesired layers or particles can be deposited on the bevel regions of the wafer. If the undesired layers or particles are not removed from the bevel area of the wafer, the manufacturing process for forming the semiconductor device and the circuit pattern is continued, which may cause problems: for example, the wafer may be deformed, Such undesired layers or particles can cause defects in manufacturing yields due to defects in subsequent processes, or can result in difficulty in aligning wafers.

為此,需要透過某一後處理來移除非所欲之層或微粒。於一新近之方法中,選擇性地供應電漿至晶圓之邊緣區域,以移除晶圓邊緣區域上之非所欲之層或微粒。To do so, it is necessary to remove undesired layers or particles through a certain post-treatment. In a more recent approach, plasma is selectively supplied to the edge regions of the wafer to remove undesired layers or particles on the edge regions of the wafer.

此一習知之晶圓斜面區域電漿蝕刻製程係利用例如含氯(Cl)之氣體實施。然而,作為腐蝕性氣體之氯氣會留存於晶圓之整個表面上。當氯氣暴露於大氣中時,氯氣會與空氣中所含之水分發生反應並進而腐蝕形成於晶圓上之層、尤其是金屬層。因此,於晶圓斜面區域蝕刻製程完成後,應實施一後蝕刻處理製程,以移除留存於晶圓上之氯氣。使一晶圓邊緣蝕刻腔室與一後蝕刻處理腔室形成於同一模組中,以避免使晶圓暴露於大氣中。此外,於晶圓蝕刻製程完成後,降低晶圓邊緣蝕刻腔室之溫度並將晶圓移至後蝕刻處理腔室中。然後,升高後蝕刻處理腔室之溫度,以實施後蝕刻處理製程。這些程序使得該模組應構造有可被單獨加熱之一後蝕刻處理腔室,因而會浪費該模組之空間並使製造成本升高。This conventional wafer bevel region plasma etching process is carried out using, for example, a gas containing chlorine (Cl). However, chlorine as a corrosive gas remains on the entire surface of the wafer. When chlorine is exposed to the atmosphere, the chlorine reacts with the moisture contained in the air and corrodes the layers formed on the wafer, especially the metal layer. Therefore, after the wafer bevel region etching process is completed, a post-etching process should be performed to remove the chlorine remaining on the wafer. A wafer edge etch chamber is formed in the same module as a post etch process chamber to avoid exposing the wafer to the atmosphere. In addition, after the wafer etch process is completed, the temperature of the wafer edge etch chamber is lowered and the wafer is moved into the post etch processing chamber. Then, the temperature of the processing chamber is etched after raising to perform a post-etching process. These procedures allow the module to be constructed with one that can be individually heated to etch the processing chamber, thereby wasting the space of the module and increasing manufacturing costs.

而且,習知晶圓斜面區域電漿蝕刻製程因電漿密度低而具有低之蝕刻速率,進而因蝕刻速率低而需要較長之處理時間,並且不能蝕刻斜面區域中之某些層。此外,因處理溫度較低,難以移除晶圓斜面區域中之金屬層。特別地,無法容易地蝕刻掉銅層,且即使銅層被蝕刻掉,也無法完全移除銅離子。留存於晶圓斜面區域上之此等銅離子可與一下伏之反擴散層(anti-diffusion layer)發生反應,或者擴散入晶圓之一中央部並滲透入例如一層間絕緣層內,進而可降低裝置之可靠性。Moreover, conventional wafer bevel plasma etching processes have a low etch rate due to low plasma density, which in turn requires a long processing time due to low etch rate and does not etch certain layers in the bevel region. In addition, it is difficult to remove the metal layer in the bevel area of the wafer due to the lower processing temperature. In particular, the copper layer cannot be easily etched away, and even if the copper layer is etched away, the copper ions cannot be completely removed. The copper ions remaining on the bevel area of the wafer may react with the anti-diffusion layer of the underlying layer or diffuse into a central portion of the wafer and penetrate into, for example, an interlayer insulating layer, thereby Reduce the reliability of the device.

本發明提供一種電漿蝕刻設備以及一種蝕刻晶圓之方法,其能夠利用一現有電漿產生裝置或一遠端電漿產生系統,於同一蝕刻設備中實施一晶圓斜面區域蝕刻製程及一後處理製程。The present invention provides a plasma etching apparatus and a method of etching a wafer, which can implement a wafer bevel area etching process and a subsequent etching process in a same etching apparatus using an existing plasma generating apparatus or a remote plasma generating system. Process the process.

本發明亦提供一種電漿蝕刻設備以及一種蝕刻晶圓之方法,其能夠藉由產生高密度電漿、使電漿集中於斜面區域上、並加熱包含一晶圓支架之一腔室之內部,而容易地移除晶圓斜面區域中之金屬層。The present invention also provides a plasma etching apparatus and a method of etching a wafer capable of generating a high density plasma, concentrating the plasma on the bevel area, and heating the interior of a chamber including a wafer holder. It is easy to remove the metal layer in the bevel area of the wafer.

本發明亦提供一種電漿蝕刻設備以及一種蝕刻晶圓之方法,其移除留存於斜面區域上之各層之一預定厚度,直到暴露出晶圓,藉以完全移除銅離子。The present invention also provides a plasma etching apparatus and a method of etching a wafer that removes a predetermined thickness of each of the layers remaining on the bevel area until the wafer is exposed, thereby completely removing copper ions.

根據本發明之一實施例,一種電漿蝕刻設備,包含:一腔室,具有一電漿反應隔間,被構造成閉合的;一晶圓支架,設置於該腔室內並用以支撐一晶圓及垂直地移動該晶圓,藉以將該晶圓載入或載出該腔室;一蝕刻氣體供應單元,用以供應一蝕刻氣體至該腔室內,以蝕刻該晶圓之某一區域;一電漿產生單元,用以產生該蝕刻氣體之電漿至該腔室;以及一加熱單元,設置於該腔室之一壁上,用以加熱該電漿反應隔間及該晶圓其中之一或加熱該電漿反應隔間與該晶圓至活化一電漿反應之一溫度。According to an embodiment of the invention, a plasma etching apparatus includes: a chamber having a plasma reaction compartment configured to be closed; a wafer holder disposed in the chamber and supporting a wafer And vertically moving the wafer to load or load the wafer into the chamber; an etching gas supply unit for supplying an etching gas into the chamber to etch a certain area of the wafer; a plasma generating unit for generating a plasma of the etching gas to the chamber; and a heating unit disposed on a wall of the chamber for heating the plasma reaction compartment and one of the wafers Or heating the temperature of the plasma reaction compartment to the wafer to activate a plasma reaction.

該加熱單元可設置於該反應隔間之一給定壁或一側面上。The heating unit can be disposed on a given wall or one side of the reaction compartment.

該電漿蝕刻設備可更包含一晶圓支架加熱單元,設置於該晶圓支架中,用以加熱該晶圓支架。The plasma etching apparatus may further include a wafer holder heating unit disposed in the wafer holder to heat the wafer holder.

該加熱單元可包含一加熱絲以及一電源供應器,該電源供應器用以供應電源至該加熱絲。The heating unit may include a heating wire and a power supply for supplying power to the heating wire.

活化該電漿反應之該溫度之範圍可係自室溫至約350℃。The temperature at which the plasma reaction is activated can range from room temperature to about 350 °C.

該晶圓之該某一區域可包含一斜面區域,於該斜面區域上形成一包含一金屬層之薄層。The region of the wafer may include a beveled region on which a thin layer comprising a metal layer is formed.

於產生該電漿之前,可由該加熱單元加熱該晶圓。The wafer can be heated by the heating unit prior to producing the plasma.

該金屬層可係為一銅層、一鋁層、及一鎢層其中之一。The metal layer can be one of a copper layer, an aluminum layer, and a tungsten layer.

若該金屬層係為銅層,則該晶圓可被加熱至自約250℃至約350℃之溫度範圍,若該金屬層係為該鋁層,則該晶圓可被加熱至自約40℃至約80℃之溫度範圍,且若該金屬層係為該鎢層,則該晶圓可被加熱至自約30℃至約50℃之溫度範圍。If the metal layer is a copper layer, the wafer can be heated to a temperature ranging from about 250 ° C to about 350 ° C. If the metal layer is the aluminum layer, the wafer can be heated to about 40 From °C to a temperature range of about 80 ° C, and if the metal layer is the tungsten layer, the wafer can be heated to a temperature ranging from about 30 ° C to about 50 ° C.

該電漿蝕刻設備可更包含一遠端電漿產生單元,用以將一後處理氣體激發至一電漿狀態並供應該電漿狀態之後處理氣體至該腔室內。The plasma etching apparatus may further include a remote plasma generating unit for exciting a post-treatment gas to a plasma state and supplying the plasma state to the processing chamber to the chamber.

該遠端電漿產生單元可包含:一後處理氣體罐,用以儲存該後處理氣體;一電漿產生器,用以將該後處理氣體激發至該電漿狀態;以及一電源供應器,用以供應高頻電源至該遠端電漿產生單元之該電漿產生器。The remote plasma generating unit may include: a post-processing gas tank for storing the post-processing gas; a plasma generator for exciting the post-processing gas to the plasma state; and a power supply, The plasma generator for supplying a high frequency power source to the remote plasma generating unit.

該遠端電漿產生單元可更包含一蒸發器,用以蒸發一液態之後處理材料。The remote plasma generating unit may further comprise an evaporator for evaporating a liquid to process the material.

根據本發明之另一實施例,提供一種用以蝕刻一晶圓之方法,該方法包含:放置一晶圓於一腔室中之一晶圓支架上;供應一蝕刻氣體至該腔室內;以及藉由於該腔室中產生電漿,蝕刻該晶圓之一預定區域,其中於產生該電漿之前,加熱該晶圓。According to another embodiment of the present invention, a method for etching a wafer is provided, the method comprising: placing a wafer on a wafer holder in a chamber; supplying an etching gas into the chamber; A predetermined area of the wafer is etched by the generation of plasma in the chamber, wherein the wafer is heated prior to generating the plasma.

該晶圓之該預定區域可包含一斜面區域。The predetermined area of the wafer may include a beveled area.

該晶圓可被加熱至自室溫至約350℃之溫度範圍。The wafer can be heated to a temperature ranging from room temperature to about 350 °C.

可藉由執行一加熱該晶圓支架之製程、一加熱該腔室之內部之製程其中之一或同時執行該二製程,以加熱該晶圓。The wafer can be heated by performing one of a process of heating the wafer holder, a process of heating the interior of the chamber, or simultaneously performing the two processes.

一金屬層及一絕緣層可堆疊於該斜面區域上。A metal layer and an insulating layer may be stacked on the slope area.

該方法可更包含:自該斜面區域移除該金屬層;以及利用電漿、透過一局部蝕刻製程自該斜面區域移除該絕緣層之一部分,以移除留存於該斜面區域中之金屬離子或微粒。The method may further include: removing the metal layer from the bevel region; and removing a portion of the insulating layer from the bevel region by using a plasma, through a partial etching process, to remove metal ions remaining in the bevel region Or particles.

可藉由使用CF4 、SF6 、O2 、及He氣體所產生之電漿,移除該絕緣層。The insulating layer can be removed by using a plasma generated by CF 4 , SF 6 , O 2 , and He gas.

該金屬層可係為一銅層、一鋁層、及一鎢層其中之一。The metal layer can be one of a copper layer, an aluminum layer, and a tungsten layer.

可利用Cl2 及BCl3 作為一反應氣體及利用Ar作為一惰性氣體蝕刻該銅層,利用Cl2 、BCl3 、及O2 作為一反應氣體及利用Ar作為一惰性氣體蝕刻該鋁層,並利用SF6 或NF3 作為一反應氣體及利用Ar作為一惰性氣體蝕刻該鎢層。The copper layer can be etched by using Cl 2 and BCl 3 as a reactive gas and Ar as an inert gas, using Cl 2 , BCl 3 , and O 2 as a reactive gas and etching the aluminum layer using Ar as an inert gas, and The tungsten layer is etched using SF 6 or NF 3 as a reactive gas and using Ar as an inert gas.

於蝕刻該晶圓之該預定區域之後,該方法可更包含:於該腔室中利用一電漿狀態之後處理氣體自該晶圓之一整個頂面移除殘留物;以及於移除該等殘留物之後,排放一剩餘氣體。After etching the predetermined region of the wafer, the method may further include: removing the residue from the entire top surface of the wafer after the plasma state is utilized in the chamber; and removing the residue After the residue, a residual gas is discharged.

可利用一遠端電漿製程產生該電漿狀態之後處理氣體。The process gas can be processed after the plasma state is generated using a remote plasma process.

可藉由混合一惰性氣體與H2 O、H2 O2 、NH3 其中之一或一H2 與N2 之混合氣體,來製備該後處理氣體。The post-treatment gas can be prepared by mixing an inert gas with one of H 2 O, H 2 O 2 , NH 3 or a mixed gas of H 2 and N 2 .

根據本發明,藉由利用電漿蝕刻設備中已經包含的用於利用電漿蝕刻晶圓斜面區域之電漿產生裝置,或者藉由利用一遠端電漿產生系統,可在實施一斜面區域蝕刻製程之後,在用於該斜面區域蝕刻製程之同一蝕刻設備中實施一用於移除氯氣之後處理,進而可縮短處理時間。此外,不需要將一後處理腔室包含於一個模組中,因而可節約模組之空間並可降低製造成本。In accordance with the present invention, a beveled region etch can be performed by utilizing a plasma generating device already included in the plasma etching apparatus for etching the wafer bevel region with plasma, or by utilizing a remote plasma generating system. After the process, a process for removing chlorine gas is performed in the same etching apparatus for the bevel area etching process, thereby shortening the processing time. In addition, there is no need to include a post-processing chamber in one module, thereby saving space in the module and reducing manufacturing costs.

而且,藉由產生高密度電漿並將均勻之高密度電漿集中於斜面區域上,可更高效地蝕刻斜面區域並可完全移除留存於斜面區域上之金屬離子,因而可防止裝置之可靠性降低。Moreover, by producing a high-density plasma and concentrating a uniform high-density plasma on the bevel area, the bevel area can be more efficiently etched and the metal ions remaining on the bevel area can be completely removed, thereby preventing the device from being reliable. Reduced sex.

下文將參照附圖更詳細地說明本發明之具體實施例。然而,本發明可實施為不同之形式,而不應認為僅限於本文所述之實施例。而是,提供該等實施例旨在使本揭露內容透徹、完整並將本發明之範圍全面傳達給熟習此項技藝者。Specific embodiments of the present invention will be described in more detail hereinafter with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as being limited to the embodiments described herein. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention is fully disclosed.

第1圖係為一示意性剖視圖,其例示根據本發明之一實施例之電漿蝕刻設備。1 is a schematic cross-sectional view illustrating a plasma etching apparatus according to an embodiment of the present invention.

參見第1圖,該電漿蝕刻設備包含一腔室100、一屏蔽部件200、一遮罩部件300、一電漿產生器400、以及一晶圓支架500。屏蔽部件200將腔室100劃分成一反應隔間(A)與一分隔隔間(D)。遮罩部件300設置於屏蔽部件200之反應隔間(A)中。電漿產生器400設置於屏蔽部件200之分隔隔間(D)中。晶圓支架500設置於遮罩部件300下面。一晶圓10之一中央區域被遮罩部件300及晶圓支架500屏蔽,而晶圓10之一斜面區域則被暴露。該電漿蝕刻設備更包含位於遮罩部件300與電漿產生器400間之一法拉第屏蔽600、以及一蝕刻氣體供應單元700,該蝕刻氣體供應單元700係用以於一斜面區域蝕刻製程中供應反應氣體。Referring to FIG. 1, the plasma etching apparatus includes a chamber 100, a shield member 200, a mask member 300, a plasma generator 400, and a wafer holder 500. The shield member 200 divides the chamber 100 into a reaction compartment (A) and a compartment (D). The mask member 300 is disposed in the reaction compartment (A) of the shield member 200. The plasma generator 400 is disposed in the partition compartment (D) of the shield member 200. The wafer holder 500 is disposed under the mask member 300. A central region of a wafer 10 is shielded by the mask member 300 and the wafer holder 500, and one of the bevel regions of the wafer 10 is exposed. The plasma etching apparatus further includes a Faraday shield 600 between the mask member 300 and the plasma generator 400, and an etching gas supply unit 700 for supplying in a bevel region etching process. Reaction gas.

腔室100包含一下室110及一上室122,其中下室110具有一下加熱單元112,上室120則具有一上加熱單元122。The chamber 100 includes a lower chamber 110 and an upper chamber 122, wherein the lower chamber 110 has a lower heating unit 112 and the upper chamber 120 has an upper heating unit 122.

下室110包含一下本體111、下加熱單元112、以及一貫穿開口113。下本體111具有一中空之矩形盒形狀。下加熱單元112設置於下本體111之至少一側壁中。貫穿開口113係貫穿下本體111之一頂壁形成。亦即,下本體111形似一矩形支柱,具有矩形之頂面及底面以及四側壁。然而,下本體111並不限於矩形支柱形狀。另一選擇為,下本體111可形似一圓柱體或多面體,且下本體111之每一表面皆可具有一多邊形形狀。用以支撐晶圓10之晶圓支架500係於下本體111之一內部空間內垂直移動。一閘閥130設置於下本體111之一側上,用以載入及卸載晶圓10。一排放部件140設置於下本體111之另一側上,用以排放腔室100中之污染物。閘閥130係位於下本體111之一側壁。下室110可經閘閥130連接至另一腔室(圖未示出)。下加熱單元112設置於下本體111之側壁之一部分處,用以加熱腔室100。下加熱單元112設置於下本體111之側壁中。因此,下加熱單元112可用以加熱下本體111,且因下加熱單元112可控制內部溫度,故可穩定地維持下本體111之內部溫度而不會因外界環境條件而使內部溫度發生驟然變化。可使用一電加熱器作為下加熱單元112。該電加熱器包含複數加熱絲112a及一電源供應器112b,其中該複數加熱絲112a係沿下本體111之內部側向表面設置或穿過下本體111之側壁設置,電源供應器112b係用以供應電力至該複數加熱絲112a。然而,下加熱單元112並非僅限於電加熱器。舉例而言,亦可使用一燈加熱器作為下加熱單元112。因下加熱單元112設置於下本體111之側壁上或穿過該側壁設置,故可從加載晶圓10之時起集中地加熱晶圓10之斜面區域。藉此,可更有效地蝕刻晶圓10之斜面區域。特別地,因當晶圓10之斜面區域受到加熱時,金屬層與反應氣體間之反應性增強,故可輕易地移除形成於晶圓10之斜面區域上之非所欲之金屬層。此外,蝕刻反應之副產物不容易再次沉積於晶圓10之斜面區域上,且因此可容易地排放副產物。下加熱單元112可設置於下本體111之頂壁及/或底壁上。較佳使貫穿下本體111之頂壁形成之貫穿開口113所具有之直徑大於晶圓10之直徑,以容許晶圓支架500穿過貫穿開口113向上移動至下本體111外。The lower chamber 110 includes a lower body 111, a lower heating unit 112, and a through opening 113. The lower body 111 has a hollow rectangular box shape. The lower heating unit 112 is disposed in at least one sidewall of the lower body 111. The through opening 113 is formed through one of the top walls of the lower body 111. That is, the lower body 111 is shaped like a rectangular pillar having a rectangular top surface and a bottom surface and four side walls. However, the lower body 111 is not limited to a rectangular pillar shape. Alternatively, the lower body 111 may be shaped like a cylinder or a polyhedron, and each surface of the lower body 111 may have a polygonal shape. The wafer holder 500 for supporting the wafer 10 is vertically moved in an inner space of the lower body 111. A gate valve 130 is disposed on one side of the lower body 111 for loading and unloading the wafer 10. A discharge member 140 is disposed on the other side of the lower body 111 for discharging contaminants in the chamber 100. The gate valve 130 is located on one side wall of the lower body 111. The lower chamber 110 can be connected to another chamber via a gate valve 130 (not shown). The lower heating unit 112 is disposed at a portion of the side wall of the lower body 111 for heating the chamber 100. The lower heating unit 112 is disposed in a sidewall of the lower body 111. Therefore, the lower heating unit 112 can be used to heat the lower body 111, and since the lower heating unit 112 can control the internal temperature, the internal temperature of the lower body 111 can be stably maintained without a sudden change in the internal temperature due to external environmental conditions. An electric heater can be used as the lower heating unit 112. The electric heater includes a plurality of heating wires 112a and a power supply 112b, wherein the plurality of heating wires 112a are disposed along an inner lateral surface of the lower body 111 or through a sidewall of the lower body 111, and the power supply 112b is used Power is supplied to the plurality of heating wires 112a. However, the lower heating unit 112 is not limited to the electric heater. For example, a lamp heater can also be used as the lower heating unit 112. Since the lower heating unit 112 is disposed on or through the sidewall of the lower body 111, the bevel region of the wafer 10 can be collectively heated from the time of loading the wafer 10. Thereby, the bevel area of the wafer 10 can be etched more efficiently. In particular, since the reactivity between the metal layer and the reaction gas is enhanced when the bevel region of the wafer 10 is heated, the undesired metal layer formed on the slope region of the wafer 10 can be easily removed. In addition, by-products of the etching reaction are not easily deposited again on the bevel area of the wafer 10, and thus by-products can be easily discharged. The lower heating unit 112 may be disposed on the top wall and/or the bottom wall of the lower body 111. Preferably, the through opening 113 formed through the top wall of the lower body 111 has a diameter larger than the diameter of the wafer 10 to allow the wafer holder 500 to move upward through the through opening 113 to the outside of the lower body 111.

上室120包含一上本體121、上加熱單元122、以及一內凹單元123。上本體121具有一矩形盒形狀,且上加熱單元122設置於上本體121上。內凹單元123形成於上本體121中。上本體121亦可具有其他形狀。上本體121可具有類似於下室110之下本體111之形狀。上本體121可被成型為覆蓋下本體111之貫穿開口113。亦即,上本體121之底面與下本體111之頂面緊密接觸。形成於上本體121中之內凹單元123係與下本體111之貫穿開口113相連通。為此,內凹單元123具有位於上本體121之底壁之一開口,並形成為朝上本體121之一頂壁凹陷。凹槽123之一直徑可大於貫穿開口113之直徑。於本實施例中,可利用晶圓支架500傳送晶圓10,藉以將晶圓10設置於內凹單元123中。因此,藉由集中產生電漿於內凹單元123內,可自晶圓10之斜面區域移除非所欲之層或微粒。上加熱單元122設置於內凹單元123之周緣之一部分處。舉例而言,上加熱單元122設置於上本體121之一頂壁之一部分中。類似於下本體111之下加熱單元112,上加熱單元122用以加熱晶圓10,以促進晶圓10之斜面區域中之電漿反應。較佳使下加熱單元112及上加熱單元122之加熱溫度約為80℃。根據另一實施例,加熱溫度可介於約30℃至約350℃之間。在圖式中,複數加熱絲均勻地設置於上本體121之頂壁上而形成上加熱單元122。另一選擇為,該等加熱絲可主要設置於對應於晶圓斜面區域之一區域中。上加熱單元122可自與下加熱單元112之電源供應器不同之一電源供應器(圖未示出)受電。藉此,腔室100之上部區域及下部區域可保持處於不同之溫度。另一選擇為,上加熱單元122與下加熱單元112可自同一電源供應器受電。The upper chamber 120 includes an upper body 121, an upper heating unit 122, and a concave unit 123. The upper body 121 has a rectangular box shape, and the upper heating unit 122 is disposed on the upper body 121. The concave unit 123 is formed in the upper body 121. The upper body 121 can also have other shapes. The upper body 121 may have a shape similar to the body 111 below the lower chamber 110. The upper body 121 may be shaped to cover the through opening 113 of the lower body 111. That is, the bottom surface of the upper body 121 is in close contact with the top surface of the lower body 111. The concave unit 123 formed in the upper body 121 communicates with the through opening 113 of the lower body 111. To this end, the recessed unit 123 has an opening in the bottom wall of the upper body 121 and is formed to be recessed toward the top wall of one of the upper bodies 121. One of the grooves 123 may have a diameter larger than the diameter of the through opening 113. In the present embodiment, the wafer 10 can be transferred by the wafer holder 500, so that the wafer 10 is disposed in the concave unit 123. Thus, by collectively generating plasma into the recessed unit 123, undesired layers or particles can be removed from the beveled area of the wafer 10. The upper heating unit 122 is disposed at a portion of the circumference of the concave unit 123. For example, the upper heating unit 122 is disposed in a portion of one of the top walls of the upper body 121. Similar to the heating unit 112 below the lower body 111, the upper heating unit 122 is used to heat the wafer 10 to promote the plasma reaction in the bevel region of the wafer 10. Preferably, the heating temperature of the lower heating unit 112 and the upper heating unit 122 is about 80 °C. According to another embodiment, the heating temperature may be between about 30 °C and about 350 °C. In the drawing, a plurality of heating wires are uniformly disposed on the top wall of the upper body 121 to form an upper heating unit 122. Alternatively, the heater wires may be disposed primarily in a region corresponding to a bevel region of the wafer. The upper heating unit 122 can be powered from a power supply (not shown) different from the power supply of the lower heating unit 112. Thereby, the upper and lower regions of the chamber 100 can be maintained at different temperatures. Alternatively, the upper heating unit 122 and the lower heating unit 112 can be powered from the same power supply.

儘管圖中未顯示,然腔室100更包含一門單元(圖未示出)作為上室120之上本體121與下室110之下本體111間之開/合裝置。藉由分別形成腔室100之上、下本體並將上、本體組裝形成腔室100,可更易於實施腔室100之維護。Although not shown in the drawings, the chamber 100 further includes a door unit (not shown) as an opening/closing device between the upper body 120 and the lower portion 110 of the upper chamber 110. Maintenance of the chamber 100 can be more easily performed by separately forming the upper and lower bodies of the chamber 100 and assembling the upper body to form the chamber 100.

屏蔽部件200具有一環形形狀,自下室110之頂壁穿過內凹單元123之內部延伸至上室120之頂壁。屏蔽部件200沿貫穿開口113之周緣設置,進而將包含上室110及下室120之腔室100劃分成分隔隔間(D)與反應隔間(A)。於反應隔間(A)中,設置有晶圓10,並產生電漿以蝕刻晶圓10之斜面區域。分隔隔間(D)容納電漿產生器400之一部分。反應隔間(A)與分隔隔間(D)可藉由屏蔽部件200相互隔離。舉例而言,分隔隔間(D)可保持處於大氣壓力,而反應隔間(A)中則可形成真空。The shield member 200 has an annular shape extending from the top wall of the lower chamber 110 through the interior of the recessed unit 123 to the top wall of the upper chamber 120. The shield member 200 is disposed along the periphery of the through opening 113, thereby dividing the chamber 100 including the upper chamber 110 and the lower chamber 120 into a compartment (D) and a reaction compartment (A). In the reaction compartment (A), a wafer 10 is disposed and a plasma is generated to etch the beveled area of the wafer 10. The compartment (D) houses a portion of the plasma generator 400. The reaction compartment (A) and the compartment (D) can be isolated from each other by the shield member 200. For example, the compartment (D) can be kept at atmospheric pressure, while the reaction compartment (A) can form a vacuum.

反應隔間(A)包含由上室120之頂壁與屏蔽部件200所形成之一空間以及下室110之一內部空間。分隔隔間(D)則包含由屏蔽部件200、上室120之頂壁及側壁、以及下室110之頂壁所環繞之一空間。屏蔽部件200可由能夠傳遞高頻能量之材料形成以於其中產生電漿。舉例而言,屏蔽部件200可由一絕緣材料形成,例如由氧化鋁(Al2 O3 )形成。於本實施例中,於利用晶圓支架500將晶圓10提升至屏蔽部件200之內部區域後,可藉由於屏蔽部件200之內部區域(即於屏蔽部件200與晶圓支架500間之一空間)中產生電漿而蝕刻晶圓10之斜面區域。The reaction compartment (A) includes a space formed by the top wall of the upper chamber 120 and the shield member 200, and an inner space of the lower chamber 110. The compartment (D) includes a space surrounded by the shield member 200, the top and side walls of the upper chamber 120, and the top wall of the lower chamber 110. The shield member 200 may be formed of a material capable of transmitting high frequency energy to generate plasma therein. For example, the shield member 200 may be formed of an insulating material, such as alumina (Al 2 O 3 ). In the present embodiment, after the wafer 10 is lifted to the inner region of the shield member 200 by using the wafer holder 500, the inner region of the shield member 200 (ie, a space between the shield member 200 and the wafer holder 500) may be utilized. The plasma is generated to etch the beveled area of the wafer 10.

屏蔽部件200包含一環形本體210、一位於本體210之一上部之延伸部220、以及一位於本體210之一下部之下延伸部230。上延伸部220耦合至上室120之頂壁,下延伸部230則耦合至下室110之頂壁。本體210具有與晶圓10之形狀相對應之環形形狀,俾使屏蔽部件200與晶圓10之間距可均勻。因此,電漿可均勻地提供至晶圓10之斜面區域。本體210可具有一圓環形狀。The shield member 200 includes an annular body 210, an extension 220 located at an upper portion of the body 210, and an extension portion 230 located below a lower portion of the body 210. The upper extension 220 is coupled to the top wall of the upper chamber 120 and the lower extension 230 is coupled to the top wall of the lower chamber 110. The body 210 has an annular shape corresponding to the shape of the wafer 10 so that the distance between the shield member 200 and the wafer 10 can be uniform. Therefore, the plasma can be uniformly supplied to the bevel area of the wafer 10. The body 210 can have a circular ring shape.

下延伸部230形成於本體210之下部,自本體210向外延伸,上延伸部220則形成於本體210之上部,自本體210向內延伸。另一選擇為,下延伸部230可自本體210之下部向內延伸,上延伸部220則可自本體210之上部向外延伸。下延伸部230及上延伸部220分別與下室110及上室120緊密接觸,以使反應隔間(A)及分隔隔間(D)可保持處於不同壓力。亦即,上延伸部220及下延伸部230係用作密封構件,用以對反應隔間(A)進行氣密性密封。The lower extension portion 230 is formed at a lower portion of the body 210 and extends outward from the body 210. The upper extension portion 220 is formed on the upper portion of the body 210 and extends inward from the body 210. Alternatively, the lower extension 230 can extend inwardly from the lower portion of the body 210, and the upper extension 220 can extend outwardly from the upper portion of the body 210. The lower extension portion 230 and the upper extension portion 220 are in close contact with the lower chamber 110 and the upper chamber 120, respectively, so that the reaction compartment (A) and the separation compartment (D) can be maintained at different pressures. That is, the upper extension portion 220 and the lower extension portion 230 serve as a sealing member for hermetically sealing the reaction compartment (A).

屏蔽部件200可藉由下延伸部230固定至下室110,或者藉由上延伸部220固定至上室120。可於屏蔽部件200與下室110之間以及屏蔽部件200與上室120之間額外設置例如O形圈等密封構件(圖未示出),以可靠地密封反應隔間(A)。於圖式中,屏蔽部件200係設置於下室110及上室120之平坦表面上。然而,屏蔽部件200亦可設置於下室110及上室120之凹陷表面上。於此中情形中,反應隔間(A)可得到更可靠密封。於本實施例中,屏蔽部件200、下室110、以及上室120被描述為單獨之部件。然而,於另一實施例中,屏蔽部件100、下室110、以及上室120可形成為一體。The shield member 200 may be fixed to the lower chamber 110 by the lower extension 230 or to the upper chamber 120 by the upper extension 220. A sealing member (not shown) such as an O-ring may be additionally provided between the shield member 200 and the lower chamber 110 and between the shield member 200 and the upper chamber 120 to reliably seal the reaction compartment (A). In the drawings, the shield member 200 is disposed on the flat surfaces of the lower chamber 110 and the upper chamber 120. However, the shield member 200 may also be disposed on the recessed surfaces of the lower chamber 110 and the upper chamber 120. In this case, the reaction compartment (A) provides a more reliable seal. In the present embodiment, the shield member 200, the lower chamber 110, and the upper chamber 120 are described as separate components. However, in another embodiment, the shield member 100, the lower chamber 110, and the upper chamber 120 may be formed in one piece.

遮罩部件300用以防止在設置於晶圓支架500上之晶圓10之非蝕刻區域(即中央區域)中產生電漿,以使晶圓10之非蝕刻區域不被蝕刻。為此,遮罩部件300具有類似於晶圓10之形狀。舉例而言,遮罩部件300具有一圓板形狀。較佳使遮罩部件300所具有之尺寸小於晶圓10之尺寸。於此種情形中,可選擇性地暴露晶圓10之斜面區域。舉例而言,暴露於遮罩部件300外之晶圓10之斜面區域可為約0.1毫米至約5毫米寬。藉此,可暴露出未形成有層或半導體圖案之晶圓斜面區域。亦即,若晶圓10之被暴露斜面區域之寬度小於約0.1毫米,則晶圓10之被暴露斜面區域會太小而無法藉由電漿蝕刻自晶圓10之斜面區域移除非所欲之層或微粒。而若晶圓10之被暴露斜面區域大於約5毫米,則可暴露出形成於晶圓10之非蝕刻區域(即中央區域)之層或圖案。於另一實施例中,端視製程條件而定,遮罩部件300可具有等於或大於晶圓10之尺寸。此外,可自遮罩部件300之一內部區域噴射惰性氣體,以防止電漿狀態之蝕刻氣體滲透入設置於遮罩部件300內之晶圓10之中央區域。The mask member 300 serves to prevent plasma from being generated in the non-etched region (ie, the central region) of the wafer 10 disposed on the wafer holder 500 so that the non-etched regions of the wafer 10 are not etched. To this end, the mask member 300 has a shape similar to the wafer 10. For example, the mask member 300 has a circular plate shape. Preferably, the mask member 300 has a size smaller than the size of the wafer 10. In this case, the beveled area of the wafer 10 can be selectively exposed. For example, the beveled area of the wafer 10 exposed outside of the masking component 300 can be from about 0.1 mm to about 5 mm wide. Thereby, the wafer bevel area where no layer or semiconductor pattern is formed may be exposed. That is, if the exposed bevel region of the wafer 10 has a width of less than about 0.1 mm, the exposed bevel region of the wafer 10 will be too small to be removed from the bevel region of the wafer 10 by plasma etching. Layer or particle. If the exposed bevel area of the wafer 10 is greater than about 5 mm, a layer or pattern formed in the non-etched region (ie, the central region) of the wafer 10 may be exposed. In another embodiment, depending on the process conditions, the mask component 300 can have a size equal to or greater than the wafer 10. Further, an inert gas may be ejected from an inner region of one of the mask members 300 to prevent the etching gas in the plasma state from penetrating into the central region of the wafer 10 disposed in the mask member 300.

遮罩部件300設置於屏蔽部件200內之反應隔間中。此外,遮罩部件300設置於上室120之內凹單元123之一底面上,即上室120之頂壁之一底面上。於單獨形成遮罩部件300後,可利用一耦合構件將遮罩部件300附裝至內凹單元123之底面上。另一選擇為,遮罩部件300及上室120可形成為一體。The mask member 300 is disposed in the reaction compartment within the shield member 200. Further, the mask member 300 is disposed on one of the bottom surfaces of the concave unit 123 of the upper chamber 120, that is, one of the bottom surfaces of the top wall of the upper chamber 120. After the mask member 300 is separately formed, the mask member 300 may be attached to the bottom surface of the recess unit 123 by a coupling member. Alternatively, the mask member 300 and the upper chamber 120 may be formed integrally.

一上電極310可設置於遮罩部件300之一外側部分上。一接地電壓施加至上電極310。另一選擇為,上電極310可設置於遮罩部件300內。可並不形成上電極310,而是由遮罩部件300用作一上電極。於此種情形中,可形成一絕緣層於遮罩部件300之一預定部分上。上電極310用以達成對晶圓支架500施加之一偏壓(bias voltage)之耦合,以提高晶圓10之斜面區域之電漿密度及蝕刻速率。An upper electrode 310 may be disposed on an outer portion of the mask member 300. A ground voltage is applied to the upper electrode 310. Alternatively, the upper electrode 310 may be disposed within the mask member 300. The upper electrode 310 may not be formed, but the mask member 300 may be used as an upper electrode. In this case, an insulating layer may be formed on a predetermined portion of the mask member 300. The upper electrode 310 is used to achieve a bias voltage coupling to the wafer holder 500 to increase the plasma density and etch rate of the bevel region of the wafer 10.

電漿產生器400包含一天線部件410及一電漿電源供應器420。天線部件410設置於由屏蔽部件200、上室120及下室110所環繞之分隔隔間(D)中。天線部件410包含至少一線圈,該至少一線圈圍繞屏蔽部件200纏繞N次。此外,該線圈可被繞製成垂直及/或水平地交疊、堆積或交叉。當晶圓10與天線部件410間隔開約2公分至約10公分時,可於晶圓10之斜面區域有效地產生電漿。若晶圓10與天線部件410間隔不足約2公分,則電漿可能會施加至晶圓10之中央區域,進而可不利地蝕刻晶圓10之中央區域。而若晶圓10與天線部件410間隔超過約10公分,則將難以於晶圓10之斜面區域獲得足夠之電漿密度。The plasma generator 400 includes an antenna component 410 and a plasma power supply 420. The antenna member 410 is disposed in a partition compartment (D) surrounded by the shield member 200, the upper chamber 120, and the lower chamber 110. The antenna component 410 includes at least one coil wound around the shield member 200 N times. In addition, the coils can be wound to overlap, stack or cross vertically and/or horizontally. When the wafer 10 is spaced apart from the antenna member 410 by about 2 cm to about 10 cm, plasma can be efficiently generated in the bevel region of the wafer 10. If the wafer 10 is spaced less than about 2 cm from the antenna component 410, plasma may be applied to the central region of the wafer 10, which may adversely etch the central region of the wafer 10. If the wafer 10 is spaced apart from the antenna member 410 by more than about 10 cm, it will be difficult to obtain a sufficient plasma density in the bevel region of the wafer 10.

電漿電源供應器420供應電源(例如射頻(RF)電源)至天線部件410。舉例而言,電漿電源供應器420可供應高頻電源至天線部件410。電漿電源供應器420可設置於腔室100外。亦即,可僅將電漿產生器400之天線部件410設置於腔室100之分隔隔間(D)中,電漿產生器400之其他組件則可設置於腔室100外。於本實施例中,因天線部件410緊靠反應隔間(A)設置於分隔隔間(D)中,故電漿可集中地產生於反應隔間(A)之緊靠天線部件410之一區域中。亦即,電漿可以一圓環形狀產生於環形屏蔽部件200內之反應隔間(A)中。天線部件410可與腔室100形成一體,以簡化電漿蝕刻設備並減小電漿蝕刻設備之尺寸。由電漿電源供應器420供應至天線部件410之電源可介於約100瓦至約3.0千瓦範圍內。由電漿電源供應器420供應至天線部件410之電源之頻率可介於約2百萬赫茲至約13.56百萬赫茲範圍內。The plasma power supply 420 supplies a power source, such as a radio frequency (RF) power source, to the antenna component 410. For example, the plasma power supply 420 can supply a high frequency power source to the antenna component 410. The plasma power supply 420 can be disposed outside of the chamber 100. That is, only the antenna member 410 of the plasma generator 400 may be disposed in the compartment (D) of the chamber 100, and other components of the plasma generator 400 may be disposed outside the chamber 100. In the present embodiment, since the antenna member 410 is disposed in the partition compartment (D) in close proximity to the reaction compartment (A), the plasma can be collectively generated in the reaction compartment (A) in close proximity to the antenna component 410. In the area. That is, the plasma may be generated in a ring shape in the reaction compartment (A) in the annular shield member 200. Antenna component 410 can be integral with chamber 100 to simplify the plasma etching apparatus and reduce the size of the plasma etching apparatus. The power source supplied by the plasma power supply 420 to the antenna component 410 can range from about 100 watts to about 3.0 kilowatts. The frequency of the power supplied by the plasma power supply 420 to the antenna component 410 can range from about 2 megahertz to about 13.56 megahertz.

當供應電源至天線部件410時,屏蔽部件200內之反應隔間(A)中便產生電漿。亦即,供應至天線部件410之電源於屏蔽部件200內產生高密度電漿。因遮罩部件300設置於屏蔽部件200內,故電漿之產生集中於屏蔽部件200與遮罩部件300間之一區域以及屏蔽部件200與升起之晶圓支架500間之一區域。When power is supplied to the antenna member 410, plasma is generated in the reaction compartment (A) in the shield member 200. That is, the power supplied to the antenna member 410 generates high-density plasma in the shield member 200. Since the mask member 300 is disposed in the shield member 200, the generation of plasma is concentrated in a region between the shield member 200 and the mask member 300 and a region between the shield member 200 and the raised wafer holder 500.

如上所述,於本實施例中,天線部件410設置成當晶圓支架500被升起時包圍晶圓支架500上之晶圓10,且接地電極(即上電極310及一下電極510)設置於天線部件410之上側及下側。因此,高密度電漿可均勻地產生並集中於晶圓10之斜面區域中,進而可更有效地蝕刻晶圓10之斜面區域。As described above, in the present embodiment, the antenna member 410 is disposed to surround the wafer 10 on the wafer holder 500 when the wafer holder 500 is raised, and the ground electrodes (ie, the upper electrode 310 and the lower electrode 510) are disposed on The upper side and the lower side of the antenna member 410. Therefore, the high-density plasma can be uniformly generated and concentrated in the bevel area of the wafer 10, thereby more effectively etching the bevel area of the wafer 10.

電漿產生器400包含一容性耦合電漿(capacitively coupled plasma;CCP)產生器、一混合型電漿產生器、一電子迴旋共振式(electron cyclotron resonance;ECR)電漿產生器、或一表面波電漿(surface wave plasma;SWP)產生器。The plasma generator 400 includes a capacitively coupled plasma (CCP) generator, a hybrid plasma generator, an electron cyclotron resonance (ECR) plasma generator, or a surface. Surface wave plasma (SWP) generator.

一連接孔(圖未示出)形成於上室120處,以連接電漿電源供應器420與天線部件410。一電源線可自電漿電源供應器420穿過該連接孔連接至設置於上室120內之反應隔間中之天線部件410。一阻抗匹配單元(圖未示出)可更設置於電漿電源供應器420與天線部件410之間。一冷卻單元(圖未示出)可設置於天線部件410之一側,以防止設置於腔室100內之加熱單元112及122損壞天線部件410。A connection hole (not shown) is formed at the upper chamber 120 to connect the plasma power supply 420 and the antenna member 410. A power cord can be connected from the plasma power supply 420 through the connection hole to the antenna component 410 disposed in the reaction compartment in the upper chamber 120. An impedance matching unit (not shown) may be further disposed between the plasma power supply 420 and the antenna member 410. A cooling unit (not shown) may be disposed on one side of the antenna member 410 to prevent the heating units 112 and 122 disposed in the chamber 100 from damaging the antenna member 410.

法拉第屏蔽600設置於屏蔽部件200之一外表面上,用於將屏蔽部件200內所產生之電漿集中於晶圓10之斜面區域中。法拉第屏蔽600可設置於屏蔽部件200與天線部件410之間。法拉第屏蔽600能防止因法拉第效應(Faraday Effect)而使電漿集中於天線部件410之線圈,俾使電漿可均勻地形成於腔室100內。此外,法拉第屏蔽600能防止因濺射現象而使蝕刻副產物及聚合物主要沉積於鄰近天線部件410之屏蔽部件200之內表面上,俾使蝕刻副產物及聚合物可均勻地沉積於腔室100中,並進而降低副產物及聚合物之沉積層之積聚速率。藉此,可延長電漿蝕刻設備之壽命,並減少因污染物積聚於腔室內表面而造成之微粒產生。The Faraday shield 600 is disposed on an outer surface of the shield member 200 for concentrating the plasma generated in the shield member 200 in the bevel region of the wafer 10. The Faraday shield 600 may be disposed between the shield member 200 and the antenna member 410. The Faraday shield 600 prevents the plasma from being concentrated on the coil of the antenna member 410 due to the Faraday effect, so that the plasma can be uniformly formed in the chamber 100. In addition, the Faraday shield 600 can prevent the etching by-products and the polymer from being mainly deposited on the inner surface of the shield member 200 adjacent to the antenna member 410 due to the sputtering phenomenon, so that the etching by-products and the polymer can be uniformly deposited in the chamber. 100, and in turn reduces the rate of accumulation of by-products and deposited layers of the polymer. Thereby, the life of the plasma etching equipment can be prolonged, and the generation of particles caused by the accumulation of pollutants on the inner surface of the chamber can be reduced.

法拉第屏蔽600可包含一環形本體以及形成於該本體中之複數垂直狹縫(圖未示出)。可藉由調整該等狹縫之寬度及間距,控制屏蔽部件200內電漿之均勻度。法拉第屏蔽600係連接至電漿蝕刻設備之一接地點,以當在屏蔽部件200內產生電漿時,可使電漿與天線部件410之線圈間非所欲之電壓之出現最小化,並可使電漿均勻地分佈於屏蔽部件200之整個內部。The Faraday shield 600 can include an annular body and a plurality of vertical slits (not shown) formed in the body. The uniformity of the plasma in the shield member 200 can be controlled by adjusting the width and spacing of the slits. The Faraday shield 600 is connected to one of the grounding points of the plasma etching apparatus to minimize the occurrence of undesired voltage between the plasma and the coil of the antenna component 410 when plasma is generated within the shield member 200, and The plasma is evenly distributed throughout the entire interior of the shield member 200.

一絕緣構件(圖未示出)可設置於法拉第屏蔽600與天線部件410之間。法拉第屏蔽600可與天線部件410之線圈間隔開一預定距離並設置於用以產生電漿之屏蔽部件200外。An insulating member (not shown) may be disposed between the Faraday shield 600 and the antenna member 410. The Faraday shield 600 can be spaced apart from the coil of the antenna member 410 by a predetermined distance and disposed outside of the shield member 200 for generating plasma.

晶圓支架500設置於腔室100之反應隔間(A)中,用以支撐晶圓10。晶圓支架500用以將載入下室110中之晶圓10移動至設置有遮罩部件300及屏蔽部件200之上室120之內凹單元123,或者將晶圓10自上室120之內凹單元123向下移動至下室100。The wafer holder 500 is disposed in the reaction compartment (A) of the chamber 100 for supporting the wafer 10. The wafer holder 500 is used to move the wafer 10 loaded in the lower chamber 110 to the concave unit 123 provided with the mask member 300 and the chamber 120 above the shielding member 200, or to place the wafer 10 from the upper chamber 120. The concave unit 123 moves downward to the lower chamber 100.

晶圓支架500包含:一晶圓支架卡盤520,用以支撐晶圓10;一驅動單元540,用以垂直地移動晶圓支架卡盤520;以及一偏壓電源供應器550,用以供應偏壓電源至晶圓支架卡盤520。晶圓支架500更包含一提升銷(圖未示出),且晶圓支架卡盤520包含一貫穿孔,以使提升銷於其中垂直移動。The wafer holder 500 includes: a wafer holder chuck 520 for supporting the wafer 10; a driving unit 540 for vertically moving the wafer holder chuck 520; and a bias power supply 550 for supplying The power is biased to the wafer holder chuck 520. Wafer holder 500 further includes a lift pin (not shown), and wafer holder chuck 520 includes a consistent perforation to allow the lift pin to move vertically therein.

晶圓支架卡盤520具有與晶圓10之形狀相對應之一板形狀,並具有小於晶圓10之一尺寸。因此,當晶圓10放置於晶圓支架卡盤520上時,晶圓10之一背面斜面區域可暴露於電漿。一晶圓加熱單元530設置於晶圓支架卡盤520內,用以加熱晶圓10。晶圓加熱單元530包含設置於晶圓支架卡盤520內之一加熱絲531、以及用以供應電源至加熱絲531之一電源供應器532。晶圓加熱單元530之加熱絲可密集地設置於晶圓支架卡盤520之一邊緣區域中。於此種情形中,可有效地加熱放置於晶圓支架卡盤520上之晶圓10之斜面區域,進而可增強晶圓10之斜面區域10與電漿之反應性。晶圓加熱單元530之加熱溫度可介於約150℃至約550℃之間。於本實施例中,晶圓加熱單元530可將晶圓支架卡盤520加熱至約350℃。The wafer holder chuck 520 has a plate shape corresponding to the shape of the wafer 10 and has a size smaller than one of the wafers 10. Thus, when the wafer 10 is placed on the wafer carrier chuck 520, one of the back bevel regions of the wafer 10 can be exposed to the plasma. A wafer heating unit 530 is disposed in the wafer holder chuck 520 for heating the wafer 10. The wafer heating unit 530 includes a heating wire 531 disposed in the wafer holder chuck 520, and a power supply 532 for supplying power to the heating wire 531. The heater wires of the wafer heating unit 530 may be densely disposed in an edge region of the wafer holder chuck 520. In this case, the beveled area of the wafer 10 placed on the wafer holder chuck 520 can be effectively heated, thereby enhancing the reactivity of the beveled area 10 of the wafer 10 with the plasma. The heating temperature of the wafer heating unit 530 can be between about 150 ° C and about 550 ° C. In the present embodiment, the wafer heating unit 530 can heat the wafer holder chuck 520 to about 350 °C.

由偏壓電源供應器550供應至晶圓支架卡盤520之電源可介於約10瓦至約1000瓦範圍內。由偏壓電源供應器550供應至晶圓支架卡盤520之電源之頻率可介於約2百萬赫茲至約13.56百萬赫茲範圍內。偏壓電源供應器550供應偏壓電源至晶圓支架卡盤520,以提供偏壓電源至放置於晶圓支架卡盤520上之晶圓10。該偏壓電源使電漿移動至晶圓10暴露於遮罩部件300及晶圓支架卡盤520外之斜面區域。The power supplied by the bias power supply 550 to the wafer carrier chuck 520 can range from about 10 watts to about 1000 watts. The frequency of the power supplied by the bias power supply 550 to the wafer carrier chuck 520 can range from about 2 megahertz to about 13.56 megahertz. The bias power supply 550 supplies a bias supply to the wafer carrier chuck 520 to provide a bias supply to the wafer 10 placed on the wafer carrier chuck 520. The bias power source moves the plasma to a beveled area of the wafer 10 that is exposed to the mask member 300 and the wafer holder chuck 520.

下電極510可設置於晶圓支架卡盤520之一端部。下電極510被接地。下電極510係用以達成供應至晶圓支架500之偏壓電源之耦合,以提高晶圓10之斜面區域之電漿密度及蝕刻速率。The lower electrode 510 may be disposed at one end of the wafer holder chuck 520. The lower electrode 510 is grounded. The lower electrode 510 is used to achieve coupling of a bias power supply to the wafer holder 500 to increase the plasma density and etch rate of the bevel region of the wafer 10.

因偏壓電源被供應至晶圓支架卡盤520,一絕緣層511設置於晶圓支架卡盤520與下電極510之間。絕緣層511可圍繞晶圓支架卡盤520設置。於此種情形中,晶圓支架500之尺寸取決於晶圓支架卡盤520及絕緣層511之尺寸。因此,當晶圓10放置於晶圓支架500上時,晶圓10可自絕緣層511之一邊緣突出約0.1毫米至約5毫米。然而,當絕緣層511僅設置於晶圓支架卡盤520與下電極510之間時,即當絕緣層511不與晶圓10相接觸時,放置於晶圓支架500上之晶圓10可自晶圓支架卡盤520之一邊緣突出約0.1毫米至約5毫米。於另一實施例中,可不形成下電極510,因而可亦省卻絕緣層511。Since the bias power is supplied to the wafer holder chuck 520, an insulating layer 511 is disposed between the wafer holder chuck 520 and the lower electrode 510. The insulating layer 511 can be disposed around the wafer holder chuck 520. In this case, the size of the wafer holder 500 depends on the size of the wafer holder chuck 520 and the insulating layer 511. Therefore, when the wafer 10 is placed on the wafer holder 500, the wafer 10 may protrude from the edge of one of the insulating layers 511 by about 0.1 mm to about 5 mm. However, when the insulating layer 511 is disposed only between the wafer holder chuck 520 and the lower electrode 510, that is, when the insulating layer 511 is not in contact with the wafer 10, the wafer 10 placed on the wafer holder 500 may be self-made. One of the edges of the wafer holder chuck 520 protrudes from about 0.1 mm to about 5 mm. In another embodiment, the lower electrode 510 may not be formed, and thus the insulating layer 511 may be omitted.

驅動單元540包含一驅動軸541及一驅動構件542。驅動軸541延伸至腔室100內,用以垂直地移動晶圓支架卡盤520。驅動構件542用以致動驅動軸541。The driving unit 540 includes a driving shaft 541 and a driving member 542. The drive shaft 541 extends into the chamber 100 for vertically moving the wafer holder chuck 520. The drive member 542 is used to actuate the drive shaft 541.

蝕刻氣體供應單元700供應蝕刻氣體至一電漿產生區域,即屏蔽部件200、遮罩部件300及晶圓支架500間之一區域。蝕刻氣體供應單元700包含:一氣體噴射器(gas injector)710,用以噴射製程氣體至腔室100之反應隔間(A)中;一氣體管道720,用以供應製程氣體至噴射器710;一氣體罐730,用以供應製程氣體至氣體管道720;以及一閥門740,用以容許及切斷製程氣體對腔室100之供應。噴射器710可包含圍繞遮罩部件300設置於上室120中之複數噴嘴。藉此,製程氣體可圍繞遮罩部件300均勻地供應至腔室100。如上文所述,因腔室100中設置有下加熱單元112及上加熱單元122,故可於供應製程氣體至腔室100之前,利用下加熱單元112及上加熱單元122加熱製程氣體。The etching gas supply unit 700 supplies the etching gas to a plasma generating region, that is, a region between the shield member 200, the mask member 300, and the wafer holder 500. The etching gas supply unit 700 includes: a gas injector 710 for injecting process gas into the reaction compartment (A) of the chamber 100; a gas conduit 720 for supplying process gas to the injector 710; A gas tank 730 for supplying process gas to the gas line 720; and a valve 740 for allowing and shutting off the supply of the process gas to the chamber 100. The ejector 710 can include a plurality of nozzles disposed in the upper chamber 120 about the shroud component 300. Thereby, the process gas can be uniformly supplied to the chamber 100 around the mask member 300. As described above, since the lower heating unit 112 and the upper heating unit 122 are disposed in the chamber 100, the process gas can be heated by the lower heating unit 112 and the upper heating unit 122 before the process gas is supplied to the chamber 100.

於另一實施例中,蝕刻氣體供應單元700可穿過屏蔽部件200連接至腔室100之電漿產生區域。亦即,噴射器710之噴嘴可均勻地形成於屏蔽部件200中,且氣體管道720可穿過上室120連接至噴嘴,以穿過屏蔽部件200供應製程氣體至電漿產生區域。In another embodiment, the etching gas supply unit 700 may be connected to the plasma generating region of the chamber 100 through the shield member 200. That is, the nozzle of the ejector 710 may be uniformly formed in the shield member 200, and the gas conduit 720 may be connected to the nozzle through the upper chamber 120 to supply the process gas to the plasma generation region through the shield member 200.

現在將根據本發明之一實例性實施例,參照第2圖來闡述一種利用上述電漿蝕刻設備蝕刻一晶圓之方法。A method of etching a wafer using the plasma etching apparatus described above will now be described with reference to FIG. 2 in accordance with an exemplary embodiment of the present invention.

於步驟S110中,開啟設置於腔室100之側壁上之閘閥130,並將晶圓10引入腔室100中,即反應隔間(A)中。一金屬層已藉由某一先前製程而形成於晶圓10上,以用於在晶圓10上形成半導體裝置,且因而該金屬層已形成於晶圓10之斜面區域上。In step S110, the gate valve 130 disposed on the sidewall of the chamber 100 is opened, and the wafer 10 is introduced into the chamber 100, that is, in the reaction compartment (A). A metal layer has been formed on the wafer 10 by a prior process for forming a semiconductor device on the wafer 10, and thus the metal layer has been formed on the bevel region of the wafer 10.

於步驟S120中,將所引入之晶圓10放置於晶圓支架500上。此處,在引入晶圓10之前或過程中,可利用設置於腔室100及晶圓支架500上之下加熱單元112及上加熱單元122將腔室100加熱至一預定溫度。加熱之目的係加熱晶圓10之斜面區域,以提高晶圓10之斜面區域之蝕刻反應性。腔室100之加熱溫度可因腔室100之材料而異。一般而言,加熱溫度可係為100℃或以下,以防止腔室100發生熱變形。此後,關閉閘閥130,並將腔室100之反應隔間(A)之壓力調節至一所需準位。反應隔間(A)之壓力可係為1×10-3托或以下。接著,將晶圓支架500向上移動至上室120之內凹單元123、靠近遮罩部件300。此處,晶圓支架500與設置於內凹單元123中之遮罩部件300之間距被調整至約0.1毫米至約10毫米。於此範圍內,可防止在遮罩部件300與晶圓支架500間之一區域中產生電漿。此處,晶圓10、晶圓支架500及遮罩部件300係形成為一圓形形狀,且晶圓10、晶圓支架500及遮罩部件300之中心對齊。因此,晶圓10之斜面區域可暴露於緊密相間之晶圓支架500與遮罩部件300外。藉由減小遮罩部件300與晶圓10之間距,可降低在設置於遮罩部件300下面的晶圓10之一區域中產生電漿之可能性。In step S120, the introduced wafer 10 is placed on the wafer holder 500. Here, before or during the introduction of the wafer 10, the heating unit 112 and the upper heating unit 122 disposed under the chamber 100 and the wafer holder 500 may be used to heat the chamber 100 to a predetermined temperature. The purpose of the heating is to heat the beveled area of the wafer 10 to increase the etch reactivity of the beveled areas of the wafer 10. The heating temperature of the chamber 100 may vary depending on the material of the chamber 100. In general, the heating temperature may be 100 ° C or less to prevent thermal deformation of the chamber 100. Thereafter, the gate valve 130 is closed and the pressure of the reaction compartment (A) of the chamber 100 is adjusted to a desired level. The pressure of the reaction compartment (A) may be 1 x 10-3 Torr or less. Next, the wafer holder 500 is moved up to the concave unit 123 of the upper chamber 120, adjacent to the mask member 300. Here, the distance between the wafer holder 500 and the mask member 300 disposed in the concave unit 123 is adjusted to be about 0.1 mm to about 10 mm. Within this range, it is possible to prevent plasma from being generated in a region between the mask member 300 and the wafer holder 500. Here, the wafer 10, the wafer holder 500, and the mask member 300 are formed in a circular shape, and the centers of the wafer 10, the wafer holder 500, and the mask member 300 are aligned. Therefore, the beveled area of the wafer 10 can be exposed to the outside of the closely spaced wafer holder 500 and the mask member 300. By reducing the distance between the mask member 300 and the wafer 10, the possibility of generating plasma in one of the regions of the wafer 10 disposed under the mask member 300 can be reduced.

於步驟S130中,由氣體供應單元700供應包含例如氯(Cl)之蝕刻氣體至反應隔間(A),並利用電漿產生器400將供應至反應隔間(A)之蝕刻氣體激發至電漿狀態,藉此產生電漿狀態之蝕刻氣體。亦即,施加高頻電源至設置於分隔隔間(D)中之天線部件410,並施加接地電源至設置於遮罩部件300之一側之上電極310及設置於晶圓支架500之一側之下電極510,藉此於其間之一區域中,即於屏蔽部件200內之一區域中產生電漿。此處,舉例而言,供應2百萬赫茲、1.5千瓦之高頻電源至天線部件410,以於晶圓10之斜面區域產生電漿。此時,製程壓力可保持處於約5毫托至約500毫托之範圍內。電漿狀態之蝕刻氣體沿遮罩部件300之周緣均勻地噴射,且設置於屏蔽部件200內表面上之法拉第屏蔽600可使電漿狀態之製程氣體集中至斜面區域。此時,施加一偏壓至圍繞遮罩部件300設置之上電極310以及圍繞晶圓支架500設置之下電極510,以移除晶圓10之斜面區域上非所欲之層及微粒。舉例而言,供應13.56百萬赫茲、500瓦之偏壓電源至晶圓支架500,以蝕刻掉暴露於電漿之晶圓10之斜面區域上非所欲之層及微粒。於本實施例中,可利用設置於腔室100之內表面上或側壁中以及晶圓支架500內之加熱單元,加熱晶圓10。因此,甚至當有一金屬層沉積於晶圓10之斜面區域上時,亦可在加熱該金屬層後,利用電漿自晶圓10之斜面區域蝕刻掉該金屬層。若需要,可於進行蝕刻製程前將晶圓10自室溫加熱至約350℃之加熱溫度。該加熱溫度可因沉積於晶圓10斜面區域上之材料而異。舉例而言,當晶圓10之斜面區域上沉積有銅(Cu)時,可將晶圓10加熱至約250℃至約350℃之溫度。當晶圓10之斜面區域上沉積有鋁(Al)時,可將晶圓10加熱至約40℃至約80℃之溫度。當晶圓10之斜面區域上沉積有鎢(W)時,可將晶圓10加熱至約30℃至約50℃之溫度。在自晶圓10之斜面區域蝕刻掉一材料層時,可使晶圓10之加熱溫度保持恒定。於其中自晶圓10之斜面區域依序蝕刻掉複數材料層之情形中,可使晶圓10在對應於一當前所蝕刻材料層之溫度範圍內保持恒定,然後將晶圓10加熱或冷卻至對應於下一材料層之一溫度範圍並在蝕刻掉該下一材料層之同時在該溫度範圍內保持恒定。製程氣體包含惰性氣體及反應氣體。惰性氣體可係為一18族元素,例如氬(Ar)及氦(14),或者一不與腔室100之內表面或晶圓10發生化學反應之氣體,例如氮氣(N2 )。反應氣體可係為氧(O2 )基氣體或一17族元素基氣體,例如氯(Cl)基氣體及氟(F)基氣體。根據欲自晶圓10之斜面區域移除之材料而定,亦可利用其他氣體作為反應氣體。氟(F)基氣體之實例包括CF4 、CHF、SF6 、C2 F6 、NF3 、F2 、F2 N2 及C4 F8 。氯(Cl)基氣體之實例包括BCl3 及Cl2 。當自晶圓10之斜面區域移除銅(Cu)時,可使用Cl2 或BCl3 作為反應氣體,並可使用氬氣(Ar)作為惰性氣體。當自晶圓10之斜面區域移除鋁(Al)時,可使用Cl2 、BCl3 、或O2 作為反應氣體,並可使用氬氣(Ar)作為惰性氣體。當自晶圓10之斜面區域移除鎢(W)時,可使用SF6或NF3 作為反應氣體,並可使用氬氣(Ar)作為惰性氣體。當自晶圓10之斜面區域移除銅(Cu)時,反應氣體在約250℃至約350℃之溫度範圍內可更具反應性。當自晶圓10之斜面區域移除鋁(Al)時,反應氣體在約40℃至約80℃之溫度範圍內可更具反應性。當自晶圓10之斜面區域移除鎢(W)時,反應氣體在約30℃至約50℃之溫度範圍內可更具反應性。In step S130, an etching gas containing, for example, chlorine (Cl) is supplied from the gas supply unit 700 to the reaction compartment (A), and the etching gas supplied to the reaction compartment (A) is excited to the electricity by the plasma generator 400. The slurry state, thereby producing an etching gas in a plasma state. That is, a high-frequency power source is applied to the antenna member 410 disposed in the partition (D), and a ground power source is applied to the electrode 310 disposed on one side of the mask member 300 and disposed on one side of the wafer holder 500. The lower electrode 510 thereby generates plasma in a region therebetween, i.e., in a region within the shield member 200. Here, for example, a 2 megahertz, 1.5 kW high frequency power source is supplied to the antenna component 410 to generate plasma in the bevel area of the wafer 10. At this point, the process pressure can be maintained in the range of from about 5 mTorr to about 500 mTorr. The etching gas in the plasma state is uniformly sprayed along the circumference of the mask member 300, and the Faraday shield 600 disposed on the inner surface of the shield member 200 can concentrate the process gas in the plasma state to the slope region. At this time, a bias is applied to the upper electrode 310 disposed around the mask member 300 and the lower electrode 510 is disposed around the wafer holder 500 to remove undesired layers and particles on the bevel region of the wafer 10. For example, a 13.56 megahertz, 500 watt bias supply is supplied to the wafer holder 500 to etch away undesired layers and particles on the beveled area of the wafer 10 exposed to the plasma. In the present embodiment, the wafer 10 can be heated by a heating unit disposed on or in the inner surface of the chamber 100 and in the wafer holder 500. Therefore, even when a metal layer is deposited on the bevel region of the wafer 10, the metal layer can be etched away from the bevel region of the wafer 10 by plasma after heating the metal layer. If desired, the wafer 10 can be heated from room temperature to a heating temperature of about 350 ° C prior to the etching process. This heating temperature may vary depending on the material deposited on the bevel area of the wafer 10. For example, when copper (Cu) is deposited on the beveled area of the wafer 10, the wafer 10 can be heated to a temperature of from about 250 °C to about 350 °C. When aluminum (Al) is deposited on the beveled area of the wafer 10, the wafer 10 can be heated to a temperature of from about 40 ° C to about 80 ° C. When tungsten (W) is deposited on the beveled area of the wafer 10, the wafer 10 can be heated to a temperature of from about 30 °C to about 50 °C. The temperature of the heating of the wafer 10 can be kept constant while etching a layer of material from the beveled area of the wafer 10. In the case where the plurality of material layers are sequentially etched from the bevel area of the wafer 10, the wafer 10 can be kept constant over a temperature range corresponding to a layer of the currently etched material, and then the wafer 10 is heated or cooled to Corresponding to a temperature range of one of the next material layers and remaining constant over this temperature range while etching away the next material layer. The process gas contains an inert gas and a reactive gas. The inert gas may be a group 18 element such as argon (Ar) and helium (14), or a gas that does not chemically react with the inner surface of the chamber 100 or the wafer 10, such as nitrogen (N 2 ). The reaction gas may be an oxygen (O 2 )-based gas or a Group 17 element-based gas such as a chlorine (Cl)-based gas and a fluorine (F)-based gas. Depending on the material to be removed from the beveled area of the wafer 10, other gases may also be utilized as the reactive gas. Examples of the fluorine (F)-based gas include CF 4 , CHF, SF 6 , C 2 F 6 , NF 3 , F 2 , F 2 N 2 , and C 4 F 8 . Examples of the chlorine (Cl)-based gas include BCl 3 and Cl 2 . When copper (Cu) is removed from the bevel area of the wafer 10, Cl 2 or BCl 3 may be used as the reaction gas, and argon (Ar) may be used as the inert gas. When aluminum (Al) is removed from the bevel area of the wafer 10, Cl 2 , BCl 3 , or O 2 may be used as the reaction gas, and argon (Ar) may be used as the inert gas. When tungsten (W) is removed from the bevel area of the wafer 10, SF6 or NF 3 may be used as the reaction gas, and argon (Ar) may be used as the inert gas. When copper (Cu) is removed from the beveled region of wafer 10, the reactive gas is more reactive at temperatures ranging from about 250 °C to about 350 °C. When aluminum (Al) is removed from the bevel area of the wafer 10, the reaction gas is more reactive in a temperature range of from about 40 ° C to about 80 ° C. When tungsten (W) is removed from the beveled region of the wafer 10, the reactive gas is more reactive in a temperature range of from about 30 ° C to about 50 ° C.

於步驟S140中,於蝕刻晶圓10之斜面區域後,終止電漿產生以及蝕刻氣體供應,並自腔室100排放出剩餘氣體及副產物。In step S140, after the bevel region of the wafer 10 is etched, the plasma generation and the etching gas supply are terminated, and the remaining gas and by-products are discharged from the chamber 100.

於步驟S150中,將晶圓支架500向下移動至下室110。此處,可供應額外氣體至腔室100內,並可緩慢地減小供應至天線部件410之高頻電源以維持電漿狀態,直到剩餘氣體完全排放出或者晶圓支架500移動到下方為止,藉此減少缺陷及減少微粒之產生。此後,開啟閘閥130,並將晶圓10載出腔室100。In step S150, the wafer holder 500 is moved down to the lower chamber 110. Here, additional gas may be supplied into the chamber 100, and the high frequency power supplied to the antenna member 410 may be slowly reduced to maintain the plasma state until the remaining gas is completely discharged or the wafer holder 500 is moved to the lower side, This reduces defects and reduces the generation of particles. Thereafter, the gate valve 130 is opened and the wafer 10 is carried out of the chamber 100.

第3圖係為一示意性剖視圖,其例示根據本發明另一實施例之電漿蝕刻設備。3 is a schematic cross-sectional view illustrating a plasma etching apparatus according to another embodiment of the present invention.

參見第3圖,該實施例之電漿蝕刻設備包含:一腔室100;一屏蔽部件200,將腔室100劃分成一反應隔間(A)與一分隔隔間(D);一遮罩部件300,設置於屏蔽部件200內之反應隔間(A)中;一電漿產生器400,設置於屏蔽部件200外之分隔隔間(D)中;一晶圓支架500,設置於遮罩部件300下面;一法拉第屏蔽600,設置於遮罩部件300與電漿產生器400之間;以及一蝕刻氣體供應單元700,用以於一斜面區域蝕刻製程中供應反應氣體。該電漿蝕刻設備更包含一遠端電漿產生器800,用以將一反應氣體之狀態改變至一電漿狀態並於一後處理期間供應該電漿狀態之反應氣體。Referring to FIG. 3, the plasma etching apparatus of this embodiment comprises: a chamber 100; a shielding member 200 dividing the chamber 100 into a reaction compartment (A) and a compartment (D); a mask component 300, disposed in the reaction compartment (A) in the shielding member 200; a plasma generator 400 disposed in the partition compartment (D) outside the shielding component 200; a wafer holder 500 disposed on the mask component Below the 300; a Faraday shield 600 disposed between the mask member 300 and the plasma generator 400; and an etching gas supply unit 700 for supplying a reactive gas in a bevel region etching process. The plasma etching apparatus further includes a remote plasma generator 800 for changing the state of a reactive gas to a plasma state and supplying the reactive gas of the plasma state during a post-treatment.

亦即,相較第1圖之電漿蝕刻設備,該實施例之電漿蝕刻設備更包含遠端電漿產生器800。因此,在以下說明中,將主要詳細闡述遠端電漿產生器800。That is, the plasma etching apparatus of this embodiment further includes the remote plasma generator 800 compared to the plasma etching apparatus of FIG. Therefore, in the following description, the distal plasma generator 800 will be primarily explained in detail.

遠端電漿產生器800係用以將一後處理氣體激發至一電漿狀態並供應該電漿狀態之後處理氣體至一晶圓10之正面。遠端電漿產生器800包含:一後處理氣體罐810,用以儲存該後處理氣體;一電漿產生器820,用以自該後處理氣體罐810接收該後處理氣體並將該後處理氣體激發至一電漿狀態;一電源供應器830,用以供應高頻電源至該電漿產生器820;一氣體供應單元840,用以經一氣體管道720及一噴射器710供應該電漿狀態之後處理氣體至腔室100內;以及一閥門850,用以控制該電漿狀態之後處理氣體之供應。來自電漿產生器820之該電漿狀態之後處理氣體經由氣體供應單元840、氣體管道720及噴射器710供應至腔室100內。在此後處理製程中,晶圓支架500之一晶圓支架卡盤520被向下移動至腔室100之下側。因此,由遠端電漿產生器800所供應之遠端電漿可噴射至晶圓10之正面。藉此,可自晶圓10之正面移除蝕刻殘留物,例如氯氣。該電漿蝕刻設備亦可使用另一能夠以各種方法(例如一種利用微波之方法)在腔室100外產生電漿之遠端電漿系統來取代遠端電漿產生器800。The remote plasma generator 800 is configured to excite a post-treatment gas to a plasma state and supply the plasma state to the front side of a wafer 10. The remote plasma generator 800 includes: a post-treatment gas tank 810 for storing the post-treatment gas; a plasma generator 820 for receiving the post-treatment gas from the post-treatment gas tank 810 and post-processing The gas is excited to a plasma state; a power supply 830 for supplying a high frequency power to the plasma generator 820; a gas supply unit 840 for supplying the plasma via a gas pipe 720 and an injector 710 After the state, the process gas is introduced into the chamber 100; and a valve 850 is used to control the supply of the process gas after the plasma state. The process gas from the plasma generator 820 is then supplied to the chamber 100 via the gas supply unit 840, the gas line 720, and the injector 710. In this post-processing process, one of the wafer holders 500 wafer holder chuck 520 is moved down to the lower side of the chamber 100. Thus, the far end plasma supplied by the remote plasma generator 800 can be injected onto the front side of the wafer 10. Thereby, etching residues, such as chlorine, can be removed from the front side of the wafer 10. The plasma etch apparatus can also replace the remote plasma generator 800 with another remote plasma system that can generate plasma outside of the chamber 100 in a variety of ways, such as a method utilizing microwaves.

儲存於後處理氣體罐810中之後處理氣體包含H2 O、NH3 、H2 O2 、H2 、及N2 之一混合氣體,且H2 O及H2 O2 係以一氣體狀態加以儲存。於其中使用H2 O或H2 O2 作為後處理氣體之情形中,額外提供一蒸發裝置(圖未示出)以蒸發H2 O或H2 O2 。此外,設置一惰性氣體供應裝置(圖未示出),以供應惰性氣體,例如氬氣(Ar)。惰性氣體係與後處理氣體一同供應並被激發至一電漿狀態。After being stored in the post-treatment gas tank 810, the treatment gas contains a mixed gas of H 2 O, NH 3 , H 2 O 2 , H 2 , and N 2 , and H 2 O and H 2 O 2 are applied in a gaseous state. Store. In the case where H 2 O or H 2 O 2 is used as the after-treatment gas, an evaporation device (not shown) is additionally provided to evaporate H 2 O or H 2 O 2 . Further, an inert gas supply means (not shown) is provided to supply an inert gas such as argon (Ar). The inert gas system is supplied together with the aftertreatment gas and is excited to a plasma state.

第4圖係為一流程圖,其闡釋根據本發明另一實施例之一種利用第3圖之電漿蝕刻設備蝕刻一晶圓之方法。相較第2圖之晶圓蝕刻方法,該實施例之晶圓蝕刻方法更包含:於步驟S140中排放蝕刻氣體及反應副產物後,執行一利用遠端電漿之晶圓後處理操作S250以及一反應副產物排放操作S260。亦即,該實施例之晶圓蝕刻方法包含一晶圓引入操作S210、一晶圓加熱及提升操作S220、一斜面區域蝕刻操作S230、一蝕刻氣體及反應副產物排放操作S240、利用遠端電漿之晶圓後處理操作S250、反應副產物排放操作S260、以及一晶圓排放操作S270。於以下對該實施例之說明中,將主要闡述利用遠端電漿之晶圓後處理操作S250以及反應副產物排放操作S260。4 is a flow chart illustrating a method of etching a wafer using the plasma etching apparatus of FIG. 3 in accordance with another embodiment of the present invention. The wafer etching method of the embodiment further includes: after discharging the etching gas and the reaction by-product in step S140, performing a wafer post-processing operation S250 using the remote plasma, and A reaction by-product discharge operation S260. That is, the wafer etching method of this embodiment includes a wafer introducing operation S210, a wafer heating and lifting operation S220, a bevel region etching operation S230, an etching gas and a reaction byproduct discharging operation S240, and utilizing the remote power. The wafer wafer post-processing operation S250, the reaction by-product discharge operation S260, and a wafer discharge operation S270. In the following description of the embodiment, the wafer post-processing operation S250 using the remote plasma and the reaction by-product discharge operation S260 will be mainly explained.

於步驟S250中,為在蝕刻晶圓10之斜面區域後移除殘留於晶圓10正面上之蝕刻氣體組分(例如氯(Cl)),自遠端電漿產生器800供應電漿狀態之後處理氣體至晶圓10之正面。與供應電漿狀態之後處理氣體之同時或在此之前,向下移動晶圓支架500,以將晶圓10定位於腔室100之下側。為供應電漿狀態之後處理氣體,由電源供應器830對電漿產生器820供應預定之功率,並由後處理氣體罐810對電漿產生器820供應後處理氣體。此時,舉例而言,由電源供應器830供應約為2百萬赫茲、1.5千瓦之高頻電源,並使腔室100內部保持處於約5毫托至約500毫托之壓力。將以此種方式製備之電漿狀態之後處理氣體經氣體供應單元840、氣體管道720及噴射器710噴射入腔室100中。將含氫之氣體,例如H2 O、H2 O2 、NH3 、以及H2 與N2 之一混合氣體其中之一,與一惰性氣體相混合,並供應含氫之氣體與惰性氣體之混合氣體作為後處理氣體。此時,可施加偏壓電源至一上電極310及一下電極510,以促進該後處理之進行。以此種方式供應之電漿狀態之含氫之後處理氣體與殘留於晶圓10上之氯(Cl)發生反應,結果產生HCl。HCl在真空及高溫狀態下係為氣相。In step S250, after etching the bevel area of the wafer 10, the etching gas component (for example, chlorine (Cl)) remaining on the front surface of the wafer 10 is removed, and the plasma state is supplied from the remote plasma generator 800. The gas is processed to the front side of the wafer 10. Simultaneously with or prior to the processing of the plasma state after the plasma state, the wafer holder 500 is moved downward to position the wafer 10 on the lower side of the chamber 100. The plasma generator 820 is supplied with a predetermined power by the power supply 830, and the post-process gas is supplied to the plasma generator 820 by the post-treatment gas tank 810 to supply the gas after the plasma state. At this time, for example, a high frequency power source of about 2 megahertz and 1.5 kW is supplied from the power supply 830, and the inside of the chamber 100 is maintained at a pressure of about 5 mTorr to about 500 mTorr. The plasma after the plasma state prepared in this manner is injected into the chamber 100 through the gas supply unit 840, the gas line 720, and the ejector 710. A hydrogen-containing gas, such as H 2 O, H 2 O 2 , NH 3 , and one of a mixed gas of H 2 and N 2 , is mixed with an inert gas, and supplies a hydrogen-containing gas and an inert gas. The mixed gas is used as a post-treatment gas. At this time, a bias power can be applied to an upper electrode 310 and a lower electrode 510 to facilitate the post-processing. The hydrogen contained in the plasma state supplied in this manner is reacted with chlorine (Cl) remaining on the wafer 10 to produce HCl. HCl is in the gas phase under vacuum and high temperature conditions.

於步驟S260中,於後處理操作之後,終止遠端電漿產生器800之電漿產生及後處理氣體供應,並排出殘留於腔室100中之氣體(即HCl氣體)。In step S260, after the post-processing operation, the plasma generation and after-treatment gas supply of the remote plasma generator 800 is terminated, and the gas remaining in the chamber 100 (i.e., HCl gas) is discharged.

於步驟S270中,開啟一閘閥130,並自腔室100排放出經處理之晶圓10。In step S270, a gate valve 130 is opened and the processed wafer 10 is discharged from the chamber 100.

第5圖係為一示意圖,其例示根據本發明另一實施例之一包含電漿蝕刻設備之模組。該模組包含能夠執行斜面區域蝕刻與後處理二種製程之複數電漿蝕刻設備。Figure 5 is a schematic diagram illustrating a module including a plasma etching apparatus in accordance with another embodiment of the present invention. The module includes a plurality of plasma etching equipment capable of performing both etching and post-processing of the bevel area.

參見第5圖,該實施例之模組包含複數晶圓載入機910、傳送裝置920a及920b、緩衝室930、傳送室940、以及設置於傳送室940之側壁上之複數電漿蝕刻設備950a、950b、950c及950d。各該電漿蝕刻設備950a、950b、950c及950d具有與第3圖所示相同之結構並以與第4圖所述相同之方式運作,藉此執行斜面區域蝕刻與後處理二種製程。Referring to FIG. 5, the module of this embodiment includes a plurality of wafer loaders 910, transfer devices 920a and 920b, a buffer chamber 930, a transfer chamber 940, and a plurality of plasma etching devices 950a disposed on the sidewalls of the transfer chamber 940. , 950b, 950c and 950d. Each of the plasma etching apparatuses 950a, 950b, 950c, and 950d has the same structure as that shown in Fig. 3 and operates in the same manner as described in Fig. 4, thereby performing two processes of bevel area etching and post-processing.

傳送裝置920a用以將一晶圓自晶圓載入機910傳送至緩衝室930,設置於緩衝室940中之傳送裝置920b則可將晶圓自緩衝室930依序傳送至電漿蝕刻設備950a、950b、950c及950d。於電漿蝕刻設備950a、950b、950c及950d中,利用電漿蝕刻晶圓之斜面區域並利用遠端電漿移除晶圓上之殘留物質。The transfer device 920a is configured to transfer a wafer from the wafer loader 910 to the buffer chamber 930, and the transfer device 920b disposed in the buffer chamber 940 can sequentially transfer the wafer from the buffer chamber 930 to the plasma etching device 950a. , 950b, 950c and 950d. In the plasma etching apparatus 950a, 950b, 950c, and 950d, the bevel area of the wafer is etched using plasma and the residual material on the wafer is removed using the remote plasma.

如上文所述,該實施例之模組包含複數電漿蝕刻設備,因而不需要一後處理腔室-而習知模組則同時包含一斜面區域蝕刻裝置及一後處理腔室二者。因此,本實施例之模組可有利地節約空間並降低製造成本。此外,因斜面區域蝕刻製程與後處理製程係於一個裝置中順次執行,故可縮短處理時間。As described above, the module of this embodiment includes a plurality of plasma etching apparatus so that a post processing chamber is not required - and the conventional module includes both a beveled area etching apparatus and a post processing chamber. Therefore, the module of the present embodiment can advantageously save space and reduce manufacturing costs. In addition, since the bevel area etching process and the post-processing process are sequentially performed in one device, the processing time can be shortened.

第6至10圖係為用於闡釋根據本發明另一實施例之一種斜面區域蝕刻方法之剖視圖。在第6至10圖,以一種利用一雙重鑲嵌製程(dual damascene process)形成一銅線之方法為例來闡釋一種半導體裝置製造方法,且參考編號20及30分別表示一晶片區域及一斜面區域。6 to 10 are cross-sectional views for explaining a bevel etching method according to another embodiment of the present invention. In the sixth to tenth embodiments, a method of fabricating a copper wire by using a dual damascene process is taken as an example to illustrate a method of fabricating a semiconductor device, and reference numerals 20 and 30 respectively denote a wafer region and a slope region. .

參見第6圖,一第一絕緣層11、一蝕刻終止層(etch stop layer)12、以及一第二絕緣層13依序形成於一晶圓10之一頂面上,該頂面上形成有一預定結構。舉例而言,蝕刻終止層12可利用一氮化矽層形成。第一絕緣層11及第二絕緣層13係由蝕刻速率不同於蝕刻終止層12之材料形成。舉例而言,第一絕緣層11及第二絕緣層13係由一含氧材料例如TEOS(tetra ethyl ortho silicate;四乙基正矽酸鹽)形成。透過利用一通孔遮罩(via hole mask)之一光刻製程,蝕刻第二絕緣層13並暴露出蝕刻終止層12。藉此,將第一絕緣層11、蝕刻終止層12及第二絕緣層13沉積於斜面區域30之正面、側面及背面以及晶片區域20之正面上。Referring to FIG. 6, a first insulating layer 11, an etch stop layer 12, and a second insulating layer 13 are sequentially formed on a top surface of a wafer 10, and a top surface is formed thereon. Scheduled structure. For example, the etch stop layer 12 can be formed using a tantalum nitride layer. The first insulating layer 11 and the second insulating layer 13 are formed of a material having an etching rate different from that of the etch stop layer 12. For example, the first insulating layer 11 and the second insulating layer 13 are formed of an oxygen-containing material such as TEOS (tetraethyl ortho silicate; tetraethyl orthosilicate). The second insulating layer 13 is etched and the etch stop layer 12 is exposed by a photolithography process using a via hole mask. Thereby, the first insulating layer 11, the etch stop layer 12, and the second insulating layer 13 are deposited on the front surface, the side surface, and the back surface of the slope region 30 and the front surface of the wafer region 20.

參見第7圖,透過利用一溝槽遮罩(trench mask)之一光刻製程,蝕刻第二絕緣層13之一預定區域以形成一溝槽14,同時蝕刻第一絕緣層11之一暴露區域以形成一通孔15。藉此,形成包含溝槽14及通孔15之一雙鑲嵌圖案。此處,第一絕緣層11、蝕刻終止層12及第二絕緣層13殘留於斜面區域30之正面、側面及背面上。Referring to FIG. 7, a predetermined region of the second insulating layer 13 is etched by using a lithography process of a trench mask to form a trench 14 while etching an exposed region of the first insulating layer 11. To form a through hole 15. Thereby, a double damascene pattern including the trench 14 and the via 15 is formed. Here, the first insulating layer 11, the etch stop layer 12, and the second insulating layer 13 remain on the front side, the side surface, and the back surface of the slope area 30.

參見第8圖,形成一反擴散層16於晶圓10之整個表面上。反擴散層16係由Ta、TaN、Ti、TiN、W、或WN形成。舉例而言,反擴散層16係透過一電鍍方法形成。反擴散層16在通孔15及溝槽14之底部可較在通孔15及溝槽14之橫向側面處為厚,且在溝槽14及通孔15之上隅角處可存在懸垂部。於此種情形中,與氬濺射同時地產生氮之電漿,以蝕刻溝槽14及通孔15底部之反擴散層16並在溝槽14及通孔15橫向側面上重新沉積反擴散層16。藉由重複此反擴散層16之沉積及氬濺射,可在溝槽14及通孔15之橫向側面及底部上均勻地控制反擴散層16之厚度。此後,在藉由化學蒸氣沉積(chemical vapor deposition;CVD)或物理蒸氣沉積(physical vapor deposition;PVD)方法形成一銅種子層(圖未示出)後,藉由一電鍍方法形成一銅層17。如此一來,反擴散層16及銅層17亦形成於斜面區域30上。Referring to Figure 8, an anti-diffusion layer 16 is formed over the entire surface of the wafer 10. The anti-diffusion layer 16 is formed of Ta, TaN, Ti, TiN, W, or WN. For example, the anti-diffusion layer 16 is formed by an electroplating method. The anti-diffusion layer 16 may be thicker at the bottom of the via 15 and the trench 14 than at the lateral sides of the via 15 and the trench 14, and an overhang may exist at the corner of the trench 14 and the via 15 above. In this case, a plasma of nitrogen is generated simultaneously with argon sputtering to etch the trench 14 and the anti-diffusion layer 16 at the bottom of the via 15 and redeposit the anti-diffusion layer on the lateral sides of the trench 14 and the via 15 16. By repeating the deposition of the anti-diffusion layer 16 and argon sputtering, the thickness of the anti-diffusion layer 16 can be uniformly controlled on the lateral sides and the bottom of the trench 14 and the via hole 15. Thereafter, after forming a copper seed layer (not shown) by chemical vapor deposition (CVD) or physical vapor deposition (PVD), a copper layer 17 is formed by an electroplating method. . As a result, the anti-diffusion layer 16 and the copper layer 17 are also formed on the slope region 30.

參見第9圖,藉由一化學機械拋光(chemical mechanical polishing;CMP)製程將銅層17及反擴散層16平坦化,直到暴露出第二絕緣層13。藉此,於晶片區域20之一預定區域形成銅線。此處,可自斜面區域30局部地移除反擴散層16及銅層17。Referring to Fig. 9, the copper layer 17 and the anti-diffusion layer 16 are planarized by a chemical mechanical polishing (CMP) process until the second insulating layer 13 is exposed. Thereby, a copper wire is formed in a predetermined region of one of the wafer regions 20. Here, the anti-diffusion layer 16 and the copper layer 17 may be partially removed from the bevel region 30.

參見第10圖,移除斜面區域30中殘留之銅層17。可利用一種化學品移除斜面區域30中殘留之銅層17。然後,利用上述斜面區域蝕刻設備其中之一,移除斜面區域30中之反擴散層16及第二絕緣層13。為移除反擴散層16及第二絕緣層13,將CF4、SF6、O2及He氣體引入斜面區域蝕刻設備,並施加預定之偏壓電源及壓力達一預定之處理時間。於執行該斜面區域蝕刻製程之同時,根據沉積於斜面區域30上之各層之厚度,於不會使晶片區域20或晶圓發生變形或受損之安全處理條件範圍內改變處理條件。Referring to Fig. 10, the copper layer 17 remaining in the bevel region 30 is removed. The copper layer 17 remaining in the beveled region 30 can be removed using a chemical. Then, the anti-diffusion layer 16 and the second insulating layer 13 in the bevel region 30 are removed by using one of the above-described bevel region etching devices. To remove the anti-diffusion layer 16 and the second insulating layer 13, CF4, SF6, O2, and He gases are introduced into the bevel region etching apparatus, and a predetermined bias power source and pressure are applied for a predetermined processing time. While performing the bevel region etching process, the processing conditions are changed within a safe processing condition that does not deform or damage the wafer region 20 or the wafer depending on the thickness of each layer deposited on the bevel region 30.

另一選擇為,不執行利用化學品移除殘留於斜面區域30中之銅層17之製程,而是可利用斜面區域蝕刻設備順次移除殘留於晶圓斜面區域30中之銅層17、反擴散層16及第二絕緣層13。為此,可利用包含設置於一腔室中之加熱裝置之斜面區域蝕刻設備。Alternatively, the process of removing the copper layer 17 remaining in the bevel region 30 by the chemical is not performed, but the copper layer 17 remaining in the bevel region 30 of the wafer may be sequentially removed by the bevel region etching device. The diffusion layer 16 and the second insulating layer 13. To this end, the apparatus can be etched using a beveled area comprising a heating device disposed in a chamber.

另一選擇為,如第11圖所示,於移除殘留於晶圓斜面區域30中之銅層17後,可利用斜面區域蝕刻設備移除反擴散層16、第二絕緣層13、蝕刻終止層12及第一絕緣層11,以暴露出晶圓10。為如上文所述暴露出晶圓10之斜面區域30,以與用於移除反擴散層16及第二絕緣層13之處理條件局部地有所不同之處理條件來執行該製程。舉例而言,該製程係藉由如下方式執行:供應CF4、SF6、O2氣體,並接著施加預定偏壓電源及壓力至斜面區域蝕刻設備達一處理時間,該處理時間長於用於移除反擴散層16及第二絕緣層13之處理時間。於此種情形中,在執行該製程時,亦根據沉積於斜面區域30上之各層之厚度,於不會使晶片區域20或晶圓發生變形或受損之安全處理條件範圍內改變處理條件。Alternatively, as shown in FIG. 11, after removing the copper layer 17 remaining in the wafer bevel region 30, the anti-diffusion layer 16, the second insulating layer 13, and the etching termination may be removed by the bevel region etching apparatus. The layer 12 and the first insulating layer 11 are exposed to the wafer 10. To expose the beveled region 30 of the wafer 10 as described above, the process is performed with processing conditions that are locally different from those used to remove the anti-diffusion layer 16 and the second insulating layer 13. For example, the process is performed by supplying CF4, SF6, O2 gas, and then applying a predetermined bias power and pressure to the bevel region etching device for a processing time longer than for removing the anti-diffusion Processing time of layer 16 and second insulating layer 13. In such a case, during the execution of the process, the processing conditions are also changed within the safe processing conditions that do not deform or damage the wafer region 20 or wafer, depending on the thickness of the layers deposited on the bevel region 30.

第12圖係為根據本發明之一實施例,於實施一斜面區域蝕刻製程之前所截取之一晶圓之平面影像;第13圖係為根據本發明之該實施例,於實施斜面區域蝕刻製程以暴露出晶圓之後所截取之晶圓之平面影像;以及第14圖係為根據本發明之該實施例,於蝕刻晶圓斜面區域之一部分之後所截取之晶圓之平面影像。第12至14圖之影像係自晶圓右側截取,且參考編號20、30及40分別表示晶片區域、斜面區域及平台。Figure 12 is a plan view of a wafer taken before a bevel area etching process is performed according to an embodiment of the present invention; and Figure 13 is a plan view of the bevel area etching process according to the embodiment of the present invention. A planar image of the wafer taken after exposing the wafer; and FIG. 14 is a plan view of the wafer intercepted after etching a portion of the bevel region of the wafer in accordance with the embodiment of the present invention. The images of Figures 12 through 14 are taken from the right side of the wafer, and reference numerals 20, 30 and 40 represent the wafer area, the bevel area and the platform, respectively.

為比較在根據本發明該實施例執行斜面區域蝕刻製程之前與之後晶圓之狀態,於晶圓上形成厚度分別約為2000、300及1000之一TEOS層、一氮化矽層及一TEOS層作為第一絕緣層11、蝕刻終止層12及第二絕緣層13。形成厚度約為100之一Ta層作為反擴散層16。接著,形成一銅層並隨之執行一邊緣珠狀物移除(edge bead remove;EBR)製程。於分別以約90sccm、90sccm、20sccm及180sccm之流速供應CF4、SF6、O2及He氣體至斜面區域蝕刻設備、並施加約600瓦之偏壓電源及1.5托之壓力至斜面區域蝕刻設備之同時,利用上述斜面區域蝕刻設備其中之一執行斜面區域蝕刻製程達10秒及20秒。亦即,於相同之處理條件下,該製程被執行10秒以蝕刻掉晶圓斜面區域之一部分,並執行20秒以暴露出晶圓之斜面區域。In order to compare the state of the wafer before and after the bevel region etching process is performed according to the embodiment of the present invention, the thicknesses formed on the wafer are respectively about 2000. 300 And 1000 One of the TEOS layer, the tantalum nitride layer, and the TEOS layer serves as the first insulating layer 11, the etch stop layer 12, and the second insulating layer 13. Forming a thickness of approximately 100 One of the Ta layers serves as the anti-diffusion layer 16. Next, a copper layer is formed and an edge bead remove (EBR) process is performed therewith. Supplying CF4, SF6, O2, and He gas to the bevel area etching apparatus at a flow rate of about 90 sccm, 90 sccm, 20 sccm, and 180 sccm, respectively, and applying a bias power of about 600 watts and a pressure of 1.5 Torr to the bevel area etching apparatus, One of the above-described beveled area etching apparatuses performs a bevel area etching process for 10 seconds and 20 seconds. That is, under the same processing conditions, the process was performed for 10 seconds to etch away a portion of the wafer bevel region and perform for 20 seconds to expose the bevel region of the wafer.

於執行該斜面區域蝕刻製程後,如第12圖所示,在晶片區域20中留下一堆疊結構,且作為藉由EBR製程移除銅層之結果,一EBR線40出現於斜面區域30中。參考編號60表示斜面區域30之一曲面橫側區域。此處,斜面區域30中存在例如銅離子等殘留物。After performing the bevel region etching process, as shown in FIG. 12, a stacked structure is left in the wafer region 20, and as a result of removing the copper layer by the EBR process, an EBR line 40 appears in the bevel region 30. . Reference numeral 60 denotes a curved lateral side region of the bevel region 30. Here, a residue such as copper ions exists in the slope area 30.

於對斜面區域30局部執行斜面區域蝕刻製程後,如第13圖所示,在鄰近曲面橫側區域60之一區域中,即在由參考編號80表示之一區域中暴露出第二絕緣層13,且在晶片區域20與第二絕緣層13之暴露區域80間之一區域70中暴露出反擴散層16。於此種情形中,於曲面橫側區域60中亦暴露出第二絕緣層13。藉由此種局部蝕刻,可徹底移除殘留於反擴散層16上之銅離子。After the bevel region etching process is partially performed on the bevel region 30, as shown in FIG. 13, the second insulating layer 13 is exposed in a region adjacent to the lateral side region 60 of the curved surface, that is, in a region indicated by reference numeral 80. And the anti-diffusion layer 16 is exposed in a region 70 between the wafer region 20 and the exposed region 80 of the second insulating layer 13. In this case, the second insulating layer 13 is also exposed in the lateral side region 60 of the curved surface. By such partial etching, the copper ions remaining on the anti-diffusion layer 16 can be completely removed.

於執行斜面區域蝕刻製程以暴露出晶圓之斜面區域30後,如第14圖所示,在鄰近斜面區域30之曲面橫側區域60之一區域中,即在由參考編號90表示之一區域中暴露出晶圓,且分別在晶片區域20與晶圓暴露區域90間之區域70及80中暴露出反擴散層16及第二絕緣層13。藉由此種斜面區域蝕刻製程,可徹底移除殘留於斜面區域30中之銅離子。After performing the bevel region etching process to expose the bevel region 30 of the wafer, as shown in FIG. 14, in an area adjacent to the curved lateral region 60 of the bevel region 30, that is, in an area indicated by reference numeral 90 The wafer is exposed and the anti-diffusion layer 16 and the second insulating layer 13 are exposed in regions 70 and 80 between the wafer region 20 and the wafer exposed region 90, respectively. By such a bevel region etching process, the copper ions remaining in the bevel region 30 can be completely removed.

於上述實施例中,係闡釋用以於形成銅層及執行EBR製程後移除殘留於斜面區域30上之銅離子之斜面區域蝕刻製程。然而,根據該實施例,除移除銅離子外,亦可移除在半導體製造製程中沉積於斜面區域30上之各種層及微粒。In the above embodiment, a bevel region etching process for forming a copper layer and removing copper ions remaining on the bevel region 30 after performing the EBR process is explained. However, according to this embodiment, in addition to removing copper ions, various layers and particles deposited on the bevel region 30 in the semiconductor fabrication process can also be removed.

於上述實施例中,係以包含一感應耦合電漿(inductively coupled plasma;ICP)源及一加熱單元之一電漿蝕刻設備為例。然而,本發明並不僅限於此。本發明可應用於各種利用電漿蝕刻斜面區域之電漿蝕刻設備。In the above embodiment, a plasma etching apparatus including an inductively coupled plasma (ICP) source and a heating unit is taken as an example. However, the invention is not limited to this. The invention is applicable to a variety of plasma etching apparatus that utilize plasma to etch a ramped region.

此外,本發明可應用於用以蝕刻晶圓之某一區域之電漿蝕刻設備以及用以蝕刻斜面區域之電漿蝕刻設備。Furthermore, the present invention is applicable to plasma etching apparatus for etching a certain area of a wafer and plasma etching apparatus for etching a bevel area.

【工業適用性】[Industrial Applicability]

本發明可用於在半導體裝置製造製程中蝕刻晶圓,例如晶圓之斜面區域,以徹底移除沉積於晶圓斜面區域上之層及微粒。The invention can be used to etch wafers, such as beveled regions of wafers, in a semiconductor device fabrication process to completely remove layers and particles deposited on the bevel regions of the wafer.

10...晶圓10. . . Wafer

11...第一絕緣層11. . . First insulating layer

12...蝕刻終止層12. . . Etch stop layer

13...第二絕緣層13. . . Second insulating layer

14...溝槽14. . . Trench

15...通孔15. . . Through hole

16...反擴散層16. . . Anti-diffusion layer

17...銅層17. . . Copper layer

20...晶片區域20. . . Wafer area

30...晶圓斜面區域30. . . Wafer bevel area

40...平台/EBR線40. . . Platform/EBR line

60...曲面橫側區域60. . . Lateral side of the surface

70...區域70. . . region

80...區域80. . . region

90...晶圓暴露區域90. . . Wafer exposed area

100...腔室100. . . Chamber

110...下室110. . . Lower room

111...下本體111. . . Lower body

112...下加熱單元112. . . Lower heating unit

112a...複數加熱絲112a. . . Multiple heating wire

112b...電源供應器112b. . . Power Supplier

113...貫穿開口113. . . Through opening

120...上室120. . . Upper room

121...上本體121. . . Upper body

122...上室/上加熱單元122. . . Upper/upper heating unit

123...內凹單元123. . . Concave unit

130...閘閥130. . . gate

140...排放部件140. . . Discharge component

200...屏蔽部件200. . . Shielding component

210...環形本體210. . . Ring body

220...上延伸部220. . . Upper extension

230...下延伸部230. . . Lower extension

300...遮罩部件300. . . Mask component

310...上電極310. . . Upper electrode

400...電漿產生器400. . . Plasma generator

410...天線部件410. . . Antenna component

420...電漿電源供應器420. . . Plasma power supply

500...晶圓支架500. . . Wafer holder

510...下電極510. . . Lower electrode

511...絕緣層511. . . Insulation

520...晶圓支架卡盤520. . . Wafer holder chuck

530...晶圓加熱單元530. . . Wafer heating unit

531...加熱絲531. . . Heating wire

532...電源供應器532. . . Power Supplier

540...驅動單元540. . . Drive unit

541...驅動軸541. . . Drive shaft

542...驅動構件542. . . Drive member

550...偏壓電源供應器550. . . Bias power supply

600...法拉第屏蔽600. . . Faraday shield

700...蝕刻氣體供應單元700. . . Etching gas supply unit

710...噴射器710. . . Ejector

720...氣體管道720. . . Gas pipeline

730...氣體罐730. . . Gas tank

740...閥門740. . . valve

800...遠端電漿產生器800. . . Remote plasma generator

810...後處理氣體罐810. . . Post-treatment gas tank

820...電漿產生器820. . . Plasma generator

830...電源供應器830. . . Power Supplier

840...氣體供應單元840. . . Gas supply unit

850...閥門850. . . valve

910...晶圓載入機910. . . Wafer loader

920a...傳送裝置920a. . . Conveyor

920b...傳送裝置920b. . . Conveyor

930...緩衝室930. . . Buffer chamber

940...傳送室940. . . Transfer room

950a...電漿蝕刻設備950a. . . Plasma etching equipment

950b...電漿蝕刻設備950b. . . Plasma etching equipment

950c...電漿蝕刻設備950c. . . Plasma etching equipment

950d...電漿蝕刻設備950d. . . Plasma etching equipment

A...反應隔間A. . . Reaction compartment

D...分隔隔間D. . . Separate compartment

第1圖係為一示意性剖視圖,其例示根據本發明之一實施例之電漿蝕刻設備;1 is a schematic cross-sectional view illustrating a plasma etching apparatus according to an embodiment of the present invention;

第2圖係為一流程圖,其闡釋根據本發明一實施例之一種利用第1圖之電漿蝕刻設備蝕刻一晶圓之方法;2 is a flow chart illustrating a method of etching a wafer using the plasma etching apparatus of FIG. 1 according to an embodiment of the invention;

第3圖係為一示意性剖視圖,其例示根據本發明另一實施例之電漿蝕刻設備;3 is a schematic cross-sectional view illustrating a plasma etching apparatus according to another embodiment of the present invention;

第4圖係為一流程圖,其闡釋根據本發明另一實施例之一種利用第3圖之電漿蝕刻設備蝕刻一晶圓之方法;4 is a flow chart illustrating a method of etching a wafer using the plasma etching apparatus of FIG. 3 according to another embodiment of the present invention;

第5圖係為一示意圖,其例示根據本發明另一實施例之一包含電漿蝕刻設備之模組;Figure 5 is a schematic view showing a module including a plasma etching apparatus according to another embodiment of the present invention;

第6至10圖係為用於闡釋根據本發明一實施例之一種斜面區域蝕刻方法之剖視圖;6 to 10 are cross-sectional views for explaining a bevel region etching method according to an embodiment of the present invention;

第11圖係為用於闡釋根據本發明又一實施例之一種斜面區域蝕刻方法之剖視圖;Figure 11 is a cross-sectional view for explaining a bevel region etching method according to still another embodiment of the present invention;

第12圖係為根據本發明之一實施例,於實施一斜面區域蝕刻製程之前所截取之一晶圓之平面影像;Figure 12 is a plan view of a wafer taken prior to performing a beveled area etching process in accordance with an embodiment of the present invention;

第13圖係為根據本發明之該實施例,於實施斜面區域蝕刻製程以暴露出晶圓之後所截取之晶圓之平面影像;以及Figure 13 is a plan view of a wafer intercepted after performing a bevel area etching process to expose a wafer in accordance with the embodiment of the present invention;

第14圖係為根據本發明之該實施例,於蝕刻晶圓斜面區域之一部分之後所截取之晶圓之平面影像。Figure 14 is a plan view of a wafer taken after etching a portion of the bevel area of the wafer in accordance with this embodiment of the present invention.

10...晶圓10. . . Wafer

100...腔室100. . . Chamber

110...下室110. . . Lower room

111...下本體111. . . Lower body

112...下加熱單元112. . . Lower heating unit

112a...複數加熱絲112a. . . Multiple heating wire

112b...電源供應器112b. . . Power Supplier

113...貫穿開口113. . . Through opening

120...上室120. . . Upper room

121...上本體121. . . Upper body

122...上室/上加熱單元122. . . Upper/upper heating unit

123...內凹單元123. . . Concave unit

130...閘閥130. . . gate

140...排放部件140. . . Discharge component

200...屏蔽部件200. . . Shielding component

210...環形本體210. . . Ring body

220...上延伸部220. . . Upper extension

230...下延伸部230. . . Lower extension

300...遮罩部件300. . . Mask component

310...上電極310. . . Upper electrode

400...電漿產生器400. . . Plasma generator

410...天線部件410. . . Antenna component

420...電漿電源供應器420. . . Plasma power supply

500...晶圓支架500. . . Wafer holder

510...下電極510. . . Lower electrode

511...絕緣層511. . . Insulation

520...晶圓支架卡盤520. . . Wafer holder chuck

530...晶圓加熱單元530. . . Wafer heating unit

531...加熱絲531. . . Heating wire

532...電源供應器532. . . Power Supplier

540...驅動單元540. . . Drive unit

541...驅動軸541. . . Drive shaft

542...驅動構件542. . . Drive member

550...偏壓電源供應器550. . . Bias power supply

600...法拉第屏蔽600. . . Faraday shield

700...蝕刻氣體供應單元700. . . Etching gas supply unit

710...噴射器710. . . Ejector

720...氣體管道720. . . Gas pipeline

730...氣體罐730. . . Gas tank

A...反應隔間A. . . Reaction compartment

D...分隔隔間D. . . Separate compartment

Claims (23)

一種電漿蝕刻設備,包含:一腔室,具有一電漿反應隔間,被構造成閉合的;一屏蔽部件,用以將該腔室之一內部劃分成一反應隔間與一分隔隔間;一遮罩部件,設置於該屏蔽部件內之該反應隔間中,並用以暴露一晶圓之一斜面區域且屏蔽該晶圓之一中央區域;一晶圓支架,設置於該腔室內並用以支撐該晶圓之該中央區域,俾使該晶圓之該斜面區域被暴露,且用以垂直地移動該晶圓;一蝕刻氣體供應單元,用以供應一蝕刻氣體至該腔室內之該屏蔽部件及該遮罩部件之間;一電漿產生單元,設置於該分隔隔間內,並用以產生該蝕刻氣體之電漿至該腔室;以及一加熱單元,設置於該腔室之一壁上,用以加熱該電漿反應隔間及該晶圓其中之一或加熱該電漿反應隔間與該晶圓至活化一電漿反應之一溫度。 A plasma etching apparatus comprising: a chamber having a plasma reaction compartment configured to be closed; a shielding member for dividing an interior of the chamber into a reaction compartment and a compartment; a masking member disposed in the reaction compartment in the shielding component for exposing a beveled area of a wafer and shielding a central region of the wafer; a wafer holder disposed in the chamber and configured to Supporting the central region of the wafer such that the bevel region of the wafer is exposed and used to vertically move the wafer; an etching gas supply unit for supplying an etching gas to the shielding in the chamber Between the component and the mask component; a plasma generating unit disposed in the compartment and configured to generate a plasma of the etching gas to the chamber; and a heating unit disposed on a wall of the chamber And a temperature for heating the plasma reaction compartment and one of the wafers or heating the plasma reaction compartment to react with the wafer to activate a plasma. 如請求項1所述之電漿蝕刻設備,其中該加熱單元係設置於該反應隔間之一給定壁或一側面上。 The plasma etching apparatus of claim 1, wherein the heating unit is disposed on a given wall or a side of one of the reaction compartments. 如請求項1所述之電漿蝕刻設備,更包含一晶圓支架加熱單元,設置於該晶圓支架中,用以加熱該晶圓支架。 The plasma etching apparatus of claim 1, further comprising a wafer holder heating unit disposed in the wafer holder for heating the wafer holder. 如請求項2或3所述之電漿蝕刻設備,其中該加熱單元包含:一加熱絲;以及一電源供應器,用於供應電源至該加熱絲。 The plasma etching apparatus of claim 2 or 3, wherein the heating unit comprises: a heating wire; and a power supply for supplying a power source to the heating wire. 如請求項1所述之電漿蝕刻設備,其中活化該電漿反應之該溫度之範圍係自室溫至約350℃。 The plasma etching apparatus of claim 1, wherein the temperature at which the plasma reaction is activated ranges from room temperature to about 350 °C. 如請求項1所述之電漿蝕刻設備,其中該晶圓之該斜面區域包含形成一包含一金屬層之薄層。 The plasma etching apparatus of claim 1, wherein the beveled region of the wafer comprises a thin layer comprising a metal layer. 如請求項6所述之電漿蝕刻設備,其中於產生該電漿之前,由該加熱單元加熱該晶圓。 The plasma etching apparatus of claim 6, wherein the wafer is heated by the heating unit before the plasma is generated. 如請求項7所述之電漿蝕刻設備,其中該金屬層係為一銅層、一鋁層、及一鎢層其中之一。 The plasma etching apparatus of claim 7, wherein the metal layer is one of a copper layer, an aluminum layer, and a tungsten layer. 如請求項8所述之電漿蝕刻設備,其中若該金屬層係為該銅層,則該晶圓係被加熱至自約250℃至約350℃之溫度範圍,若該金屬層係為該鋁層,則該晶圓係被加熱至自約40℃至約80℃之溫度範圍,且若該金屬層係為該鎢層,則該晶圓係被加熱至自約30℃至約50℃之溫度範圍。 The plasma etching apparatus of claim 8, wherein if the metal layer is the copper layer, the wafer is heated to a temperature ranging from about 250 ° C to about 350 ° C, if the metal layer is the In the aluminum layer, the wafer is heated to a temperature ranging from about 40 ° C to about 80 ° C, and if the metal layer is the tungsten layer, the wafer is heated to from about 30 ° C to about 50 ° C. Temperature range. 如請求項1所述之電漿蝕刻設備,更包含一遠端電漿產生單元,用以將一後處理氣體激發至一電漿狀態並供應該電漿狀態之後處理氣體至該腔室內。 The plasma etching apparatus of claim 1, further comprising a remote plasma generating unit for exciting a post-treatment gas to a plasma state and supplying the plasma state to the chamber after the plasma state is supplied. 如請求項10所述之電漿蝕刻設備,其中該遠端電漿產生單元包含:一後處理氣體罐,用以儲存該後處理氣體;一電漿產生器,用以將該後處理氣體激發至該電漿狀態;以及一電源供應器,用以供應高頻電源至該遠端電漿產生單元之該電漿產生器。 The plasma etching apparatus of claim 10, wherein the remote plasma generating unit comprises: a post-processing gas tank for storing the post-processing gas; and a plasma generator for exciting the post-processing gas Up to the plasma state; and a power supply for supplying high frequency power to the plasma generator of the remote plasma generating unit. 如請求項11所述之電漿蝕刻設備,其中該遠端電漿產生單元更包含一蒸發器,用以蒸發一液態之後處理材料。 The plasma etching apparatus of claim 11, wherein the remote plasma generating unit further comprises an evaporator for evaporating a liquid to process the material. 一種用以蝕刻一晶圓之方法,該方法包含:放置一晶圓之一中央區域於一腔室中之一晶圓支架上,以暴露該晶圓之一斜面區域;向上移動該晶圓支架以與一遮罩部件維持一所需距離,藉此利用該遮罩部件及該晶圓支架屏蔽該晶圓之該中央區域且暴露該晶圓之該斜面區域;供應一蝕刻氣體至該腔室中之該晶圓之該斜面區域;以及藉由於該腔室中產生電漿,蝕刻該晶圓之該斜面區域,其中於產生該電漿之前,加熱該晶圓。 A method for etching a wafer, the method comprising: placing a central region of a wafer on one of the wafer holders in a chamber to expose a sloped area of the wafer; moving the wafer holder upward Maintaining a desired distance from a mask member, thereby shielding the central region of the wafer with the mask member and the wafer holder and exposing the slope region of the wafer; supplying an etching gas to the chamber The bevel region of the wafer; and etching the bevel region of the wafer by generating plasma in the chamber, wherein the wafer is heated prior to generating the plasma. 如請求項13所述之方法,其中該晶圓被加熱至自室溫至約350℃之溫度範圍。 The method of claim 13, wherein the wafer is heated to a temperature ranging from room temperature to about 350 °C. 如請求項14所述之方法,其中藉由執行一加熱該晶圓支架之製程、一加熱該腔室之內部之製程其中之一或同時執行該二製程,以加熱該晶圓。 The method of claim 14, wherein the wafer is heated by performing a process of heating the wafer holder, heating one of the processes of the interior of the chamber, or simultaneously performing the two processes. 如請求項13所述之方法,其中一金屬層及一絕緣層係堆疊於該斜面區域上。 The method of claim 13, wherein a metal layer and an insulating layer are stacked on the slope area. 如請求項16所述之方法,更包含:自該斜面區域移除該金屬層;以及利用電漿、透過一局部蝕刻製程自該斜面區域移除該絕緣層之一部分,以移除留存於該斜面區域中之金屬離子或微 粒。 The method of claim 16, further comprising: removing the metal layer from the bevel region; and removing a portion of the insulating layer from the bevel region by using a plasma, through a partial etching process, to remove the remaining Metal ions or micro in the bevel area grain. 如請求項17所述之方法,其中藉由使用CF4 、SF6 、O2 、及He氣體所產生之電漿,移除該絕緣層。The method of claim 17, wherein the insulating layer is removed by using a plasma generated by CF 4 , SF 6 , O 2 , and He gas. 如請求項17所述之方法,其中該金屬層係為一銅層、一鋁層、及一鎢層其中之一。 The method of claim 17, wherein the metal layer is one of a copper layer, an aluminum layer, and a tungsten layer. 如請求項19所述之方法,其中利用Cl2 及BCl3 作為一反應氣體及利用Ar作為一惰性氣體蝕刻該銅層,利用Cl2 、BCl3 、及O2 作為一反應氣體及利用Ar作為一惰性氣體蝕刻該鋁層,並利用SF6 或NF3 作為一反應氣體及利用Ar作為一惰性氣體蝕刻該鎢層。The method of claim 19, wherein the copper layer is etched using Cl 2 and BCl 3 as a reactive gas and Ar is used as an inert gas, and Cl 2 , BCl 3 , and O 2 are used as a reaction gas and Ar is used as a reaction gas. An aluminum layer is etched by an inert gas, and the tungsten layer is etched using SF 6 or NF 3 as a reactive gas and Ar as an inert gas. 如請求項13所述之方法,其中於蝕刻該晶圓之該預定區域之後,該方法更包含:於該腔室中利用一電漿狀態之後處理氣體自該晶圓之一整個頂面移除殘留物;以及於移除該等殘留物之後,排放一剩餘氣體。 The method of claim 13, wherein after etching the predetermined region of the wafer, the method further comprises: removing the process gas from the entire top surface of the wafer after utilizing a plasma state in the chamber Residue; and after removing the residues, a residual gas is discharged. 如請求項21所述之方法,其中利用一遠端電漿製程產生該電漿狀態之後處理氣體。 The method of claim 21, wherein the processing of the gas after the plasma state is generated using a remote plasma process. 如請求項22所述之方法,其中藉由混合一惰性氣體與H2 O、H2 O2 、NH3 其中之一或一H2 與N2 之混合氣體,來製備該後處理氣體。The method of claim 22, wherein the post-treatment gas is prepared by mixing an inert gas with one of H 2 O, H 2 O 2 , NH 3 or a mixed gas of H 2 and N 2 .
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