TWI469532B - Analog to digital converter - Google Patents

Description

Digital analog converter

The present invention relates to a digital analog converter, and more particularly to a digital analog converter that can find an analog value corresponding to a partial value range of a digit value via interpolation.

In today's fast-changing technology era, liquid crystal displays have been widely used in electronic display products, such as televisions, computer screens, notebook computers, mobile phones or personal digital assistants. The data driver of the liquid crystal display includes an analog digital converter for providing a pixel voltage to the liquid crystal display panel according to a Gray Level value, and scanning the pixel voltage to the liquid crystal with a scan driver (Scan Driver). The pixels of the display panel are displayed to display the image to be displayed.

Since the pixel voltage and its corresponding gray scale value are non-linear (Non-Linear) relationship, the conventional digital analog converter converts the gray scale value to the pixel voltage via a Gamma Voltage resistor string, and then inputs the liquid crystal. Display panel. However, as the display quality requirements for liquid crystal displays continue to increase, the number of bits of grayscale values and the number of levels of the Gamma voltage resistor strings increase dramatically. As a result, the digital analog converter needs to occupy a large circuit area circuit, resulting in an increase in cost. Traditionally, each digital code is subjected to interpolation to reduce the design of the digital analog converter, and also has the disadvantages of high pixel voltage error and poor display quality of the liquid crystal display.

The present invention relates to a digital analog converter and a method thereof, which can effectively improve the disadvantages of large circuit area, high cost and high pixel error caused by interpolation of all digital codes in the conventional technology. The utility model has the advantages of small area, low cost, low pixel voltage error and good display quality of the liquid crystal display to which the application is applied.

According to the present invention, a digital analog converter is provided that generates a corresponding plurality of voltages in response to a plurality of values of a grayscale value, wherein the grayscale value comprises k bits and k is a natural number greater than one. The digital analog converter includes a decoding device and an operational amplifier. The decoding device includes first to fourth decoding circuits and logic operation circuits. The first decoding circuit provides first to third output voltages of the same level when the w most significant bits (MSBs) of the grayscale values are equal to the same logic value. The second decoding circuit provides the first intermediate voltage in response to the x MSBs adjacent to the w MSBs in the grayscale value when the w MSBs are not equal to the same logical value. The logic operation circuit generates the first to third logic control signals according to the y MSBs adjacent to the x MSBs among the x MSBs and the grayscale values. The third decoding circuit provides a second intermediate voltage in response to the x MSBs and the first to third logic control signals when the w MSBs are not equal to the same logic value. The fourth decoding circuit selectively controls the first to third output voltages as the first and the third according to the z MSBs adjacent to the y MSBs among the y MSBs and the grayscale values when the w MSBs are not equal to the same logic value One of the two intermediate voltages. The operational amplifier generates a pixel voltage based on the first to third output voltages. When w MSBs are not equal to the same logic value, the level of the pixel voltage is between the first and second intermediate voltages. w, x, y, and z are satisfied: The natural number.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

Please refer to FIG. 1 and FIG. 2, FIG. 1 is a block diagram of a digital analog converter according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a data driver of a digital analog converter to which the present invention is applied. The digital analog converter 20 is applied to the data driver 10 to process the gray scale values according to the hardware in the data drive 10 (such as the data register 11, the linear latch 13 and the level shifter 14). Level) GS, converted to the corresponding pixel voltage PV. Thereafter, the pixel voltage PV is output to the liquid crystal display panel (not shown) via the output buffer 15.

The digital analog converter 20 responds to a plurality of values of a gray level GS, and controls the output signal PV to correspond to a plurality of voltage levels, wherein the gray level value GS includes, for example, k bits DTk-1, DT2, ..., DT0, where k is a natural number greater than one. The digital analog converter 20 includes a decoding device 21 and an operational amplifier 22.

The operational amplifier 22 is configured to generate a pixel voltage PV according to the output voltages O1, O2, and O3, wherein the level of the pixel voltage PV is between the output voltages O1 to O3. For example, the operational amplifier 22 of the present embodiment generates a pixel voltage PV via Nearest Neighbor Interpolation, and the level of the pixel voltage PV passes through the output voltages O1 to O3, respectively. 2. The weights of 1/4 and 1/4 are added together.

The decoding device 21 provides the output voltage O1 in response to the grayscale value GS to O3. In one example, decoding device 21 divides the range of values of grayscale values GS into first and second sets of values. When the grayscale value GS is equal to the first set of values, the decoding device 21 provides the output voltages O1 to O3 having substantially the same level, whereby the digital analog converter 20 does not have the operational efficiency of the interpolation method.

When the grayscale value GS is equal to the second set of values, the decoding device 21 causes some or all of the output voltages O1 to O3 to correspond to different levels, whereby the digital analog converter 20 can correspondingly be based on the output voltages O1 to O3. The pixel voltage PV is generated by interpolation.

In this way, the digital analog converter 20 can elastically select a linear range and a relatively non-linear range of values in the gamma curve between the gray scale value GS and the pixel voltage PV, respectively, by interpolation. And the traditional resistor voltage method to obtain the corresponding pixel voltage. Accordingly, the digital analog converter 20 of the present embodiment can effectively improve the disadvantages of the large area, high cost, and large pixel voltage error of the digital analog converter in the conventional technology compared with the conventional digital analog converter.

Please refer to FIG. 3, which shows the gamma curve between the gray scale value GS and the pixel voltage PV in this embodiment. In one example of operation, k is equal to 7, in other words, the grayscale value GS includes 8 bits DT0, DT1, ..., DT7, and corresponds to a range of values including 2 ⁸ (= 256) values. In this example, the gamma curve is more linear when the grayscale value GS is between 32 and 224, and is less nonlinear when the grayscale value is less than 32 and greater than 224. Accordingly, the first set of values of the grayscale value GS of the present embodiment includes, for example, the values 0 to 31 and the values 224 to 255, and the second set of values of the grayscale value GS includes, for example, the values 32 to 223.

Next, the decoding operation of the decoding device 21 will be further described by way of example. In the following paragraphs, k bits DTk-1 to DTk0 in the grayscale value GS are divided into 4 groups according to their order, each of which includes w Most Significant Bits (MSBs) DTk -1 to DTk-w, x highest-order bits DTk-w-1 to DTk-wx, y highest-order bits DTk-wx-1 to DTk-wxy, and z highest-order bits DTk-wxy-1 To DTk-wxyz, where w, x, y, and z satisfy the condition: The natural number. The different sub-decoding units in the decoding device 21 respectively implement the aforementioned decoding operation with reference to the aforementioned four groups of bits.

Referring to FIGS. 4A to 4C, a detailed circuit diagram of the decoding device 21 of FIG. 1 is shown. For example, the decoding device 21 includes decoding circuits 21a, 21b, 21c, 21d and a logic operation circuit 21e.

Decoding circuit 21a

Please refer to Figure 4A. The decoding circuit 21a provides substantially the same level of output when the w most significant bits (MSB) DTk-1, DTk-2, ..., DTk-w are equal to the same logic value in the grayscale value GS. Voltages O1, O2 and O3. In other words, when the grayscale value GS corresponds to its maximum 2 ^Kw value and the smallest 2 ^kw value, the decoding device 21 supplies the output voltages O1 to O3 corresponding to the same level.

In the case where k and w are equal to 8 and 3, respectively, when w (= 3) MSB DTk-1 to DTk-w (ie, bit DT7 to DT5) of the gray scale value GS correspond to a logical value of 0, , indicating that the grayscale value GS corresponds to its smallest value of 32 (= 2 ^kw ) (ie, the value (00000000) ₂ to (00001111) ₂ ). The decoding circuit 21a outputs the intermediate voltage D as the output voltages O1 to O3 in response to the 32 values of the minimum grayscale value GS. The intermediate voltage D is provided by a sub-decoding circuit (not shown), which provides 32 voltage levels L0, L1, L2, ..., L31 of the lowest output signal PV in response to the minimum gray level value GS32.

When the three MSBs DT7 to DT5 of the grayscale value GS correspond to the logical value 1, it means that the grayscale value GS corresponds to its maximum 32 values (11110000) ₂ to (11111111) ₂ ). The decoding circuit 21a outputs the intermediate voltage E as the output voltages O1 to O3 in response to the 32 values of the grayscale value GS. The intermediate voltage E is provided by a sub-decoding circuit (not shown), which provides 32 voltage levels L224, L225, L226, ..., L255 with the highest output signal PV respectively in response to the maximum gray level value GS32.

According to the operation of the logic circuit 21a, the decoding device 21 can have the calibration output voltages O1 to O3 corresponding to the same level when the grayscale value GS corresponds to the first group of values, so that the digital analog converter 20 Correspondingly, there is no arithmetic effect of the interpolation method.

For example, the decoding circuit 21a includes sub-decoding units 21a1, 21a2, and 21a3 including transistors controlled by the inverted signals DN7 to DN5 of the MSBs DT7 to DT5 and their MSBs. Thus, the sub-decoding units 21a1 to 21a3 respectively provide the intermediate voltages D or E as the output voltages O1 to O3 when the MSBs DT7 to DT5 are both equal to the value 0 or the value 1.

Decoding circuit 21b

Please refer to Figure 4B. Decoding circuit 21b to w MSB DTk-1 to When DTk-w is not equal to the same logical value, it responds to x MSBs DTk-w-1, DTk-w-2, ..., DTk-wx adjacent to w MSBs in the grayscale value GS (ie, second only to The intermediate voltage A is provided for x MSBs of w MSBs.

In the case where k, w, and x are equal to 8, 3, and 2, respectively, w (= 3) MSBs DT7 to DT5 (ie, DTk-1 to DTk-w) of the grayscale value GS are not equal to the same logical value. The decoding circuit 21b provides an intermediate voltage in response to x (= 2) MSBs DTk-w-1 to DTk-wx (ie, bit DT4 to DT3) adjacent to MSB DT7 to DT5 in the grayscale value GS. A. The decoding circuit 21b includes 2 ^w (=8) sub-decoding units 21b1, 21b2, ..., 21b8 for 3 MSBs DT7 to DT5 in response to the fact that w MSBs DTk-1 to DTk-w may correspond to a plurality of different value combinations. Different numerical combinations provide decoding operations. Since the operations of the sub-decoding units 21b1 to 21b8 are substantially close, next, the operation of the sub-decoding unit 21b1 is taken as an example to further explain the operation of all the sub-decoding units 21b1 to 21b8.

The sub-decoding unit 21b1 is configured to provide the intermediate voltage A when the MSBs DT7 to DT5 correspond to the values 0, 0, and 1, respectively. When the bit DT4 and DT3 correspond to the values 00, 01, 10, and 11, respectively, the sub-decoding unit 21b1 correspondingly supplies the voltage levels L36, L44, L52, and L60 as the intermediate voltage A. For example, the True Table of the intermediate voltage A can be as shown in Figures 5A and 5B.

Logic operation circuit 21e

Please refer to Figure 4C. The logical operation circuit 21e is based on x MSBs DTk-w-1 to DTk-wx and y MSBs DTk-wx-1, DTk- adjacent to x MSBs DTk-w-1 to DTk-wx in the grayscale value GS. Wx-2,..., DTk-w-x-y generates logic control signals DTC, DTD and DTB.

In the example where k, w, x, and y are equal to 8, 3, 2, and 1, respectively, the logical operation circuit 21e is based on x (= 2) MSBs DTk-w-1 to DTk-wx (that is, bit DT4 to The MSB DT3 and the y MSBs DTk-wx-1 to DTk-wxy (that is, the bit DT2) in DT3) perform logical operations. For example, the control signals DTC, DTD, and DTB satisfy the following equations: DTC=DT2 NOR DT3

DTD=DT2 AND DT3

For example, the truth table of the control signals DTC, DTD, and DTB can be as shown in FIGS. 5A and 5B.

Decoding circuit 21c

Please refer to Figure 4B. The decoding circuit 21c provides the intermediate voltage B in response to the x MSBs DTk-1-w-1 to DTk-wx and the logic control signals DTC, DTD and DTB when the w MSBs DTk-1 to DTk-w are not equal to the same logic value. .

In the example where k, w, and x are equal to 8, 3, and 2, respectively, w (= 3) MSB DTk-1 to DTk-w (ie, bit DT7 to DT5) of the gray scale value GS are not equal to the same. For the logic value, the decoding circuit 21c responds to the x (= 2) MSBs DTk-w-1 to DTk-wx (ie, the bits DT4 to DT3) adjacent to the MSB DT7 to DT5 in the grayscale value GS and controls The signals DTC, DTD and DTB are used to provide the intermediate voltage B. The decoding circuit 21b includes 2 ^w (=8) sub-decoding units 21c1, 21c2, ..., 21c8 for 3 MSBs DT7 to DT5 in response to the fact that w MSBs DTk-1 to DTk-w may correspond to a plurality of different value combinations. Different numerical combinations provide decoding operations. Since the operations of the sub-decoding units 21c1 to 21c8 are substantially close, next, the operation of the sub-decoding unit 21c1 is taken as an example to further explain the operation of all the sub-decoding units 21c1 to 21c8.

The sub-decoding unit 21c1 is configured to provide an intermediate voltage B when the bit signals DT7 to DT5 correspond to the values 0, 0, and 1, respectively. Wherein, if the bit DT4 is equal to the value 0, the sub-decoding unit 21c1 correspondingly supplies the voltage levels L32, L40 and L48 as the intermediate voltage B when the control signals DTC, DTB and DTD correspond to the values 001, 010 and 100, respectively: If the bit DT4 is equal to the value 1, the sub-decoding unit 21c1 correspondingly supplies the voltage levels L48, L56 and L52 as the intermediate voltage B when the control signals DTC, DTB and DTD correspond to the values 001, 010 and 100, respectively. For example, the truth table of the intermediate voltage B can be as shown in FIGS. 5A and 5B.

Decoding circuit 21d

Please refer to Figure 4A. The decoding circuit 21d is based on y MSBs DTk-wx-1 to DTk-wxy in the grayscale value GS and y MSBs in the grayscale value GS when w MSBs DTk-1-DTk-w are not equal to the same logical value. DTk-wx-1 to DTk-wxy adjacent z MSBs DTk-wxy-1, ..., DTk-wxyz, selectively control the output voltage O1 as one of the intermediate voltages A and B, selectively control the output voltage O2 is one of the intermediate voltages A and B, and selectively controls the output voltage o3 to be one of the intermediate voltages A and B.

An example where k, w, x, y, and z are equal to 8, 3, 2, 1, and 2, respectively. In other words, when the MSBs DT7 to DT5 correspond to different values, the decoding circuit 21d is based on y (=1) MSB DTk-wx-1 to DTk-wxy (that is, bit DT2) and the bit in the grayscale value GS. The z(=2) MSBs DTk-wxy-1 to DTk-wxyz (ie, bit DT1 and DT0) adjacent to the DT2 are selectively controlled to output voltages O1, O2, and O3 as intermediate voltages A and B. One.

The decoding circuit 21d includes, for example, sub-decoding units 21d1, 21d2, and 21d3 for determining output voltages O1, O2, and O3, respectively. When the bit DT1 and DT2 correspond to the value 10 or 01, the sub-decoding unit 21d1 supplies the intermediate voltage A as the output voltage O1; when the bit DT1 and DT2 correspond to the value 00 or 11, the sub-decoding unit 21d1 supplies the intermediate voltage B. As the output voltage O1. When the bit DT2 and DT0 correspond to the value 10 or 01, the sub-decoding unit 21d2 supplies the intermediate voltage A as the output voltage O2; when the bits DT2 and DT0 correspond to the values 00 and 11, the sub-decoding unit 212d2 provides the intermediate voltage B. As the output voltage O2. When the bit DT2 corresponds to the value 1, the sub-decoding unit 21d3 supplies the intermediate voltage A as the output voltage O3; when the bit DT2 corresponds to the value 0, the sub-decoding unit 212d3 supplies the intermediate voltage B as the output voltage O3. For example, the truth table of the output voltages O1 to O3 can be as shown in FIGS. 5A and 5B.

Through the operations of the foregoing logic circuit 21e and the decoding circuits 21a to 21d, the decoding device 21 can correspondingly implement the truth table shown in FIGS. 5A and 5B. In this way, the operational amplifier 22 can correspondingly perform an interpolation operation according to the output voltages O1 to O3, and correspondingly find that the gray level value GS is equal to one of the values 32 to 223, the level corresponding to the pixel voltage PV is L32 to L223.

In this embodiment, the case where the number of bits k of the gray scale value GS is equal to 8, and w, x, y, and z are equal to 3, 2, 1, and 2, respectively, is taken as an example. However, this embodiment The decoding device 31 is not limited to this. In other examples, the grayscale value GS may also include more or fewer bits, and other adjustments may be made to w, x, y, and z. For example, by adjusting the values w and k, the size of the numerical space of the first set of values (including 2 ^kw elements) can be determined.

The digital analog converter of the embodiment is configured to elastically group the numerical value range of the gray scale value by setting a decoding unit that can perform a specific logical operation, and obtain different gray scales by using substantially different operation methods. The value value group corresponds to the pixel voltage. Accordingly, the digital analog converter of the embodiment can effectively solve the disadvantages of large area and high cost of the conventional digital analog converter, and correspondingly has the advantages of small area and low cost.

In addition, the digital analog converter of the present embodiment can improve the pixel in the conventional technology, which is easy to be nonlinear due to the corresponding non-linearity of the gamma curve, for the conventional technique of digital analog conversion for all digital code via the interpolation method. The voltage error is high and the picture quality of the liquid crystal display to which it is applied is poor, and correspondingly, the pixel voltage error is low and the display quality of the liquid crystal display to which it is applied is better.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. Those having ordinary skill in the art to which the present invention pertains can be made in various ways without departing from the spirit and scope of the invention. Change and retouch. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧Data Drive

11‧‧‧data register

13‧‧‧Linear latch

14‧‧‧ position shifter

15‧‧‧Output buffer

20‧‧‧Digital Analog Converter

21‧‧‧Decoding device

22‧‧‧Operational Amplifier

21e‧‧‧Logical Circuit

21a, 21b, 21c, 21d‧‧‧ logic circuits

21a1, 21a2, 21a3, 21d1, 21d2, 21d3, 21b1 to 21b8, 21c1 to 21c8‧‧‧ sub-decoding unit

FIG. 1 is a block diagram of a digital analog converter according to an embodiment of the present invention.

Figure 2 is a block diagram showing the data driver of the digital analog converter to which the present invention is applied.

FIG. 3 is a diagram showing the gamma curve between the gray scale value GS and the pixel voltage PV in the embodiment.

4A to 4C are diagrams showing detailed circuits of the decoding device 21 of Fig. 1.

5A and 5B are diagrams showing the truth table of the decoding device 21 of Fig. 1.

20‧‧‧Digital Analog Converter

21‧‧‧Decoding device

22‧‧‧Operational Amplifier

Claims (9)

A digital analog converter that generates a corresponding plurality of voltages in response to a plurality of values of a gray scale value, wherein the gray scale value includes k bits, and k is a natural number greater than 1, the digital analog converter includes: a decoding The device includes: a first decoding circuit, configured to provide a first output voltage substantially equal to the same when the w most significant bits (MSBs) of the grayscale value are equal to the same logic value a second output voltage and a third output voltage, wherein the second decoding circuit is configured to respond to the x of the gray level values adjacent to the w MSBs when the w MSBs are not equal to the same logic value The MSB provides a first intermediate voltage, and a logic operation circuit is configured to generate a first logic control signal and a second logic control according to the x MSBs and the y MSBs adjacent to the x MSBs in the grayscale value. a third logic control signal; a third decoding circuit, configured to provide a second response to the x MSBs and the first to third logic control signals when the w MSBs are not equal to the same logic value Intermediate voltage; and a fourth decoding circuit for the w When the MSB is not equal to the same logical value, the first output voltage is selectively controlled as the first and the second intermediate voltage according to the y MSBs and the z MSBs adjacent to the y MSBs of the grayscale values. One of selectively controlling the second output voltage to be one of the first and second intermediate voltages, and selectively controlling the third output voltage to be one of the first and second intermediate voltages; An operational amplifier, generating a pixel voltage according to the first to the third output voltage; wherein, when the w MSBs are not equal to the same logic value, the pixel voltage level is between the first and the Between the second intermediate voltages; wherein w, x, y, and z satisfy the condition: w+x+y+z The natural number of k. The digital analog converter of claim 1, wherein the logic operation circuit further comprises: a first operation unit, configured to: w+x MSBs and the y MSBs according to one of the x MSBs The inverse or gate (NOR) operation result and the AND operation result of the w+x+1 MSBs adjacent to the x MSBs respectively generate the first and second logic control signals; The second operation unit is configured to generate the third logic control signal according to the result of the AND operation of the inverted signals of the first and second logic control signals. The digital analog converter of claim 1, wherein the first decoding circuit further comprises: a first sub-decoding unit, configured to provide the plurality of voltages when the w MSBs are all logic 0 The lowest level voltage is used as the first voltage, and when the w MSBs are both logic 1, the voltage with the highest level of the plurality of voltages is provided as the first voltage. For example, the digital analog converter described in claim 1 of the patent scope, The first decoding circuit further includes: a second sub-decoding unit, configured to provide, when the w MSBs are all logic 0, a voltage of a plurality of levels in the voltages as the second voltage, and When the w MSBs are both logic 1, the voltage with the highest level among the voltages is provided as the second voltage. The digital analog converter of claim 1, wherein the first decoding circuit further comprises: a third sub-decoding unit, configured to provide the plurality of voltages when the w MSBs are all logic 0 The lowest level voltage is used as the third voltage, and when the w MSBs are all logic 1, the voltage with the highest level among the voltages is provided as the third voltage. The digital analog converter of claim 1, wherein the fourth decoding circuit further comprises: a first sub decoding unit, configured to correspond to one of the y MSBs, w+x+y MSBs When the logic value is 1, the first intermediate voltage is provided as the first output voltage, and when the first w+x+y MSBs correspond to the logic value 0, the second intermediate voltage is provided as the first output. Voltage. The digital analog converter of claim 1, wherein the fourth decoding circuit further comprises: a second sub decoding unit, configured to w+x+y MSBs of the one of the y MSBs The first intermediate voltage is provided when one of the z MSBs corresponds to a different logical value (Last Significant Bit, LSB) For the second output voltage, and when the first w+x+y MSBs and the LSBs correspond to the same logic value, the second intermediate voltage is provided as the second output voltage. The digital analog converter of claim 1, wherein the fourth decoding circuit further comprises: a third sub decoding unit, configured to w+x+y MSBs of the one of the y MSBs and Providing the first intermediate voltage as the third output voltage when the w+x+y+1 MSBs adjacent to the one of the y MSBs correspond to different logic values, and the When the +x+y MSBs and the w+x+y+1 MSBs correspond to the same logic value, the second intermediate voltage is provided as the third output voltage. The digital analog converter of claim 1, wherein the operational amplifier has three positive terminal inputs for receiving the first, second, and third output voltages, respectively, according to the operational amplifier The first to the third voltage performs interpolation to obtain the pixel voltage.