JP5864179B2 - Image display panel driver - Google Patents

Description

  The present invention relates to an image display panel driver that sequentially supplies a luminance potential to an image display panel.

  In general, the image display panel driver includes an operational amplifier, and the operational amplifier generates a luminance potential based on the gradation potential supplied from the decoder, and supplies the luminance potential to the image display panel. Conventionally, an image display panel driver using a differential division type operational amplifier is known (for example, Patent Documents 1 and 2). When a differential division type amplifier is used, since the size of the decoder can be reduced, there is an advantage that a highly accurate luminance potential can be output without increasing the chip size.

JP 2005-130332 A JP 2009-88716 A

  However, the conventional image display panel driver using the differential division type amplifier has the following problems. Due to the characteristics of the so-called gamma curve, when the potential difference to be differentially divided becomes large, the balance of the current flowing through the differential stage is lost, and the accuracy of the luminance potential to be supplied to the image display panel is deteriorated. is there.

  In addition, with the miniaturization of the display device, there has been a demand for further reducing the size of the image display panel driver.

  The present invention has been made in view of the problems as described above, and provides an image display panel driver capable of reducing deterioration in accuracy of the luminance potential to be supplied to the image display panel and reducing the size. With the goal.

An image display panel driver according to the present invention is an image display panel driver that sequentially supplies a luminance potential to an image display panel in accordance with sequentially supplied image data, and generates a plurality of gradation potentials. And a decoder that sequentially selects the plurality of gradation potentials based on the image data, and a drive that generates the luminance potential based on the selected gradation potential and sequentially supplies the luminance potential to the image display panel And an extraction unit that extracts at least one digit bit of the plurality of digits constituting the image data as a control bit, and the driving unit includes a constant current source in which each operating current terminal is connected A differential input transistor pair that is connected in common and has the gradation potential input to the control terminal of one of the transistors, and each operating current terminal is the rest of the differential input transistor pair A current mirror transistor pair connected to an operating current terminal; and two variable resistors connected between a remaining operating current terminal of the current mirror transistor pair and a power supply potential, and at least one of the two variable resistors. Is a variable resistance pair consisting of at least two resistors connected in parallel to each other, an output driver that generates and outputs the luminance potential based on the current value of the control terminal of the other transistor of the differential input transistor pair, and A control unit that disconnects at least one of the at least two resistors according to a bit value of a control bit and changes a resistance value of the variable resistor pair, and controls the height of the luminance potential It is characterized by adjusting according to the bit.

  According to the image display panel driver of the present invention, it is possible to reduce deterioration in accuracy of the luminance potential to be supplied to the image display panel and to reduce the size.

1 is a block diagram illustrating a configuration of an image display panel driver that is a first embodiment of the present invention; FIG. FIG. 2 is a circuit diagram illustrating an example of a configuration of a gradation potential generation unit in FIG. 1. It is a circuit diagram which shows an example of a structure of the control part of FIG. 1, and an offset cancellation block. It is a flowchart which shows the luminance potential control processing flow by an image display panel driver. It is a circuit diagram which shows an example of a structure of the control part and offset cancellation block in a 2nd Example. It is a table which shows a correspondence with a control bit and ON / OFF of a switch.

  Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

<First embodiment>
FIG. 1 shows the configuration of an image display panel driver 100 that is an embodiment of the present invention.

  The gradation potential generator 1 generates a plurality of gradation potentials by dividing the voltage.

  FIG. 2 shows an example of the configuration of the gradation potential generation unit 1. The gradation potential generation unit 1 includes resistors R1 to Rn-1 (n is an integer of 2 or more) connected in series between the highest GMA potential GMA_U and the lowest GMA potential GMA_L. For example, in the case of 256 gradations, n = 128 can be set. In this case, 128 gradation potentials obtained by dividing the resistances R1 to Rn-1 are generated. With this configuration, the gradation potential generation unit 1 corresponds to, for example, even-numbered gradations 0, 2,..., 256 out of 256 gradations including gradations 0, 1,. Individual grayscale potentials are generated.

  The data latch 2 temporarily holds image data sequentially supplied from an image data supply unit (not shown). For example, image data indicating one gradation of 256 gradations is supplied from the image data supply unit. In the case of 256 gradations, the image data consists of 8-bit binary numbers.

  The extraction unit 3 extracts at least one digit bit among a plurality of digits constituting the image data held in the data latch 2 as a control bit. For example, the control bit is the lowest bit among the bits constituting the image data.

  The decoder 4 selects one gradation potential from the plurality of gradation potentials generated by the gradation potential generation unit 1 based on the image data held in the data latch 2 and supplies the selected gradation potential to the drive unit 5. To do. Specifically, when the image data indicates an even-numbered gradation, the decoder 4 selects a gradation potential corresponding to the even-numbered gradation. For example, when the image data indicates the “0” th gradation, the gradation potential corresponding to the “0” th gradation is selected. In addition, when the image data indicates an odd-numbered gradation, the decoder 4 selects a gradation potential corresponding to an even-numbered gradation that is smaller than the odd-numbered gradation by a unit gradation. To do. For example, if one piece of image data represents the “1” gradation, the gradation potential corresponding to the “0” gradation that is smaller by one gradation is selected. A level shifter (not shown) may be provided between the data latch 2 and the decoder 4. The level shifter amplifies the voltage indicating the image data held in the data latch 2 and supplies the amplified voltage to the decoder 4.

  The drive unit 5 generates a luminance potential based on the gradation potential supplied from the decoder 4 and supplies it to the image display panel 16.

  The differential stage bias transistor 6 is an NMOS (Negative channel Metal Oxide Semiconductor) transistor for differential stage bias. The source of the differential stage bias transistor 6 is connected to the ground potential Gnd, and the drain is connected to the source of each of the differential stage transistors 7 and 8. The differential stage bias transistor 6 is turned on when a bias voltage VB1 is applied to its gate. The differential stage bias transistor 6 operates as a constant current source that generates a constant current according to the bias potential VB1.

  The differential stage transistor 7 is an NMOS transistor that forms a differential input transistor pair together with the differential stage transistor 8. The source of the differential stage transistor 7 is connected to the drain of the differential stage bias transistor 6, and the drain is connected to the drain of the current mirror transistor 9. One gradation potential is supplied from the decoder 4 to the gate of the differential stage transistor 7. The differential stage transistor 8 is also an NMOS transistor, its source is commonly connected to the drain of the differential stage bias transistor 6, its drain is connected to the drain of the current mirror transistor 10, and its gate is the drain of the output stage transistor 11 and the output stage. The drain of the transistor 12 is connected.

  The current mirror transistor 9 is a PMOS (Positive channel Metal Oxide Semiconductor) transistor that forms a current mirror in pairs with the current mirror transistor 10. The drain of the current mirror transistor 9 is connected to the drain of the differential stage transistor 7, the source is connected to the first variable resistor 14, and the gate is connected to the gate of the current mirror transistor 10. The current mirror transistor 10 is also a PMOS transistor, its drain is connected to the drain of the differential stage transistor 8, its source is connected to the second variable resistor 15, and its gate is connected to its own drain and the gate of the current mirror transistor 9. ing.

  The output stage transistor 11 is an NMOS transistor that forms an output stage together with the output stage transistor 12. The source of the output stage transistor 11 is connected to the ground potential Gnd, and the drain is connected to the gate of the differential stage transistor 8 and the drain of the output stage transistor 12. The output stage transistor 11 is turned on when the bias voltage VB2 is applied to its gate. The output stage transistor 12 is a PMOS transistor, its drain is connected to the drain of the output stage transistor 11, its source is connected to the power supply potential VDD, and its gate is connected to the drain of the differential stage transistor 7 and the drain of the current mirror transistor 9. Has been. The drain potential of the output stage transistor 12 is supplied to the image display panel 16 as a luminance potential. Hereinafter, the source terminal and the drain terminal of each transistor are also referred to as an operating current terminal, and the gate terminal is also referred to as a control terminal.

  The offset cancel block 13 is provided between the current mirror transistors 9 and 10 and the power supply potential VDD. The offset cancel block 13 includes a first variable resistor 14 and a second variable resistor 15 paired therewith. The first variable resistor 14 is provided between the power supply potential VDD and the source of the current mirror transistor 9. The second variable resistor 15 is provided between the power supply potential VDD and the source of the current mirror transistor 10. As described above, the driving unit 5 includes a differential configuration including the differential stage transistors 7 and 8, the current mirror transistors 9 and 10, and the offset cancel block 13.

  The control unit 30 changes the resistance value of the first variable resistor 14 and / or the second variable resistor 15 of the offset cancel block 13 according to the control bit extracted by the extraction unit 3. Details of the control unit 30 will be described later (FIG. 3).

  The image display panel 16 is a panel such as a liquid crystal having a plurality of display lines. Although only one driving unit 5 is shown in FIG. 1, in reality, a similar driving unit is provided for each display line.

  FIG. 3 shows an example of the configuration of the control unit 30 and the offset cancel block 13.

  The first variable resistor 14 includes PMOS transistors 21 and 22 connected in parallel to each other. The drains of the transistors 21 and 22 are connected to the source of the current mirror transistor 9 (FIG. 1), and each source is connected to the power supply potential. The gate of the transistor 21 is connected to the switch S1, and the gate of the transistor 22 is connected to the switch S2. The second variable resistor 15 is composed of a PMOS transistor, and a ground potential Gnd is always supplied to the gate of the second variable resistor 15 and is in an on state.

  For example, the resistance value between the source and drain of the transistor 22 and the resistance value of the second variable resistor 15 are the same, and the resistance value between the source and drain of the transistor 21 is larger than the resistance value of the second variable resistor 15 or It can be a small value.

  The control unit 30 controls the resistance value of the offset cancel block 14 based on the control bit extracted by the extraction unit 3. Specifically, the control unit 30 controls the resistance value of the offset cancel block 14 by controlling the resistance value of at least one of the transistors 21 and 22 by turning on or off the switches S1 and S2. With this control, the value of the current flowing through the differential stage transistors 7 and 8 can be adjusted.

  For example, when the value of the control bit is “0”, the control unit 30 connects the switch S1 to the ground potential Gnd to turn on the transistor 21 and connects the switch S2 to the power supply potential VDD to turn on the transistor 22. Turn off. For example, when the value of the control bit is “1”, the control unit 30 connects the switch S1 to the power supply potential VDD to turn off the transistor 21 and connects the switch S2 to the ground potential Gnd to connect the transistor 22. Is turned off.

  Hereinafter, the luminance potential control processing by the image display panel driver 100 will be described with reference to FIG. As a premise, the gradation potential generator 1 has 128 gradations corresponding to even-numbered gradations 0, 2,..., Of the 256 gradations composed of gradations 0, 1,. A gradation potential is generated. Further, the image data supply unit (not shown) outputs one of even-numbered gradations 0, 2,..., 254 of 256 gradations including gradations 0, 1,. Supply to the data latch 2.

  First, the data latch 2 holds one image data supplied from an image data supply unit (not shown) (step S11). The image data is, for example, a binary bit string “00000000” indicating the gradation “0”.

  Next, the extracting unit 3 extracts the least significant bit of the plurality of digits constituting the image data held in the data latch 2 as a control bit (step S12). When the image data is a bit string “00000000” indicating the gradation “0”, the control bit is “0”.

  Next, the decoder 4 selects one gradation potential from the plurality of gradation potentials generated by the gradation potential generation unit 1 based on the image data held in the data latch 2, and drives the driving unit. 5 (step S13). For example, when the image data indicates gradation “0”, the decoder 4 selects a gradation potential indicating gradation “0” and supplies it to the drive unit 5 (step S13). Since the gradation “0” is an even number, the decoder 4 selects the gradation potential indicating the gradation “0”.

  Next, the control unit 30 controls the resistance value of the offset cancel block 13 based on the control bit extracted by the extraction unit 3 (step S14).

  For example, when the control bit is “0”, the control unit 30 sets the resistance value of the first variable resistor 14 and the resistance value of the second variable resistor 15 to be the same. As a result, a luminance potential having the same gradation as the gradation indicated by the gradation potential supplied from the decoder 4 to the drive unit 5 is generated (step S15). For example, when the gradation potential corresponding to the gradation “0” is supplied to the drive unit 5, the luminance potential having the height indicating the gradation “0” is also supplied to the image display panel 16 (step S15).

  Hereinafter, a case where the data latch 2 receives supply of image data indicating the gradation “3” from an image data supply unit (not shown) in step S11 will be described.

  First, the data latch 2 holds image data supplied from an image data supply unit (not shown) (step S11). The image data is composed of a binary bit string “00000011” indicating the gradation “3”.

  Next, the extraction unit 3 extracts the least significant bit “1” of the plurality of digits constituting the image data held in the data latch 2 as a control bit, and supplies this to the control unit 30. (Step S12).

  Next, the decoder 4 selects the gradation “based on the image data indicating the gradation“ 3 ”held in the data latch 2 from the plurality of gradation potentials generated by the gradation potential generator 1. A gradation potential indicating 2 ″ is selected and supplied to the drive unit 5 (step S13). Since the gradation “3” is an odd number, the decoder 4 selects the gradation “2” which is one gradation smaller than the gradation “3”.

  Next, the control unit 30 controls the resistance value of the offset cancel block 13 based on the control bit “1” extracted by the extraction unit 3 (step S14). Since the control bit is “1”, the resistance value of the first variable resistor 14 is made larger than the resistance value of the second variable resistor 15 by a predetermined value. By this process, the current value flowing through the differential stage transistors 7 and 8 is adjusted, and the gradation “1” larger than the gradation “2” indicated by the gradation potential supplied from the decoder 4 to the driving unit 5 is obtained. A luminance potential having a height indicating 3 ″ is generated (step S15). As a result, a luminance potential having a height indicating the same gradation “3” as the gradation “3” indicated by the image data supplied to the data latch 2 is supplied to the image display panel 16 (step S15).

  Note that how much the resistance value of the first variable resistor 14 is made larger than the resistance value of the second variable resistor 15 is, for example, a preliminary simulation evaluation on the relationship between the resistance value and the height of the luminance potential, or in a prototype device. Predetermined based on measurement of luminance potential or the like.

  The above example is an example in which the image data supplied from the image data supply unit (not shown) is “0” or “3”. However, the image data may be data indicating other gradations. The image display panel driver 100 performs the same processing. In this way, the offset cancel block 13 controls its own resistance value according to whether the control bit extracted by the extraction unit 3 is “0” or “1”, and the current flowing through the differential stage is controlled. By controlling, a luminance potential of 256 gradations can be supplied to the image display panel 16.

  As described above, in the image display panel driver 100 according to the present embodiment, for example, when the total number of gradations indicated by the image data is 256 gradations, the gradation potential generation unit 1 is a half of 256 gradations, 128. Individual grayscale potentials are generated. With this configuration, the size of the gradation potential generation unit 1 can be reduced. The decoder 4 selects one of the 128 gradation potentials based on the image data held in the data latch 2. With this configuration, the size of the decoder can be reduced as compared with the case where one of all 256 gradation potentials is selected. The offset cancel block 13 controls its own resistance value based on the least significant bit among the bits constituting the image data supplied from the image data supply unit (not shown). With this configuration, the total number of gradation potentials generated by the gradation potential generation unit 1 is 128 gradations, which is half of the total number of gradations 256 indicated by the image data. Can be supplied to the image display panel 16. Further, by setting the resistance values of the first variable resistor 14 and the second variable resistor 15 constituting the offset cancel block 13 to appropriate values in advance, an effect of canceling an offset caused by so-called gamma curve characteristics. Can also be played.

  As described above, according to the image display panel driver 100 of the present embodiment, the size can be reduced and a luminance potential of 256 gradations can be supplied to the image display panel 16. Further, according to the image display panel driver 100 of the present embodiment, it is possible to reduce deterioration in accuracy of the luminance potential to be supplied to the image display panel 16 by offset cancellation.

<Second embodiment>
FIG. 5 shows an example of the configuration of the control unit 30 and the offset cancel block 13 in the present embodiment. Hereinafter, differences from the first embodiment will be mainly described.

  The first variable resistor 14 includes PMOS transistors 21 to 24 connected in parallel to each other. The drains of the transistors 21 to 24 are connected to the source of the current mirror transistor 9 (FIG. 1), and each source is connected to the power supply potential. The gate of the transistor 21 is connected to the switch S1, and the gate of the transistor 22 is connected to the switch S2. The gate of the transistor 23 is connected to the switch S3, and the gate of the transistor 24 is connected to the switch S4. The second variable resistor 15 is formed of a transistor, and the ground potential Gnd is always supplied to the gate of the second variable resistor 15 and is in an on state.

  The extraction unit 3 extracts at least two digits of a plurality of digits constituting the image data held in the data latch 2 as control bits. For example, the control bits are composed of the least significant bit and the most significant bit among the bits constituting the image data. Hereinafter, the bit corresponding to the least significant bit of the control bits is referred to as the least significant control bit, and the bit corresponding to the most significant bit is referred to as the most significant control bit.

  The control unit 30 controls connection of the switches S1 to S4 based on the value of the control bit supplied from the extraction unit 3. Since the control bit consists of 2 bits, four kinds of control are possible. That is, if the resistance values between the source and drain of the transistors 21 to 24 (FIG. 5) are different from each other, four resistance values can be selected.

  FIG. 6 shows the correspondence between control bits and switch on / off. In accordance with such correspondence, the control unit 30 turns on only the switch S1 for the even-numbered gradation among the 0-127 gradations, and turns on only the switch S2 for the odd-numbered gradation among the 0-127 gradations. Only the switch S3 is turned on for the even gradations of ˜255 gradations, and only the switch S4 is turned on for the odd gradations of the 128 to 255 gradations. With this operation, at least one of the transistors 21 to 24 can be selected and disconnected.

  As described above, in the image display panel driver 100 of this embodiment, the resistance value of the offset cancel block 13 is changed to change one gradation according to whether the gradation indicated by the image data is an even number or an odd number. In addition, the resistance value of the offset cancel block 13 can be changed according to the gradation range to which the gradation indicated by the image data belongs. Therefore, it is possible to effectively cancel offsets having different sizes for each gradation range.

  Note that the resistance values between the source and drain of each of the transistors 21 to 24 are preliminarily determined based on, for example, a prior simulation evaluation of the relationship between the resistance value and the height of the luminance potential, measurement of the luminance potential in a prototype device, or the like. decide.

  In the first and second embodiments, the resistance value of the first variable resistor 14 is changed and the resistance value of the second variable resistor 15 is fixed. However, the configuration of the present invention is not limited to this. Absent. For example, the resistance value of the first variable resistor 14 may be fixed and the resistance value of the second variable resistor 15 may be changed, or the resistance values of the first variable resistor 14 and the second variable resistor 15 may be changed. Also good.

  In the second embodiment, the first variable resistor 14 is composed of four transistors 21 to 24 connected in parallel, and the control unit 30 includes four switches S1 to S4. Not limited. For example, the number of parallel transistors configuring the first variable resistor 14 and the number of switches included in the control unit 30 can be further increased. Furthermore, the number of control bits extracted by the extraction unit 3 can be increased according to the number of these transistors and switches. With this configuration, the resistance value of the offset cancel block 13 can be finely adjusted, and the offset can be canceled more effectively. It is also conceivable to select two or more parallel transistors at the same time to finely adjust the resistance value.

  Further, the control unit 30 may have a look-up table that indicates the correspondence between gradations and offset values, and may change the resistance value of the offset cancel block 13 for each gradation based on the correspondence.

  In the above embodiment, the case where the differential input transistor pair (7 and 8) is an N differential amplifier composed of an NMOS transistor has been described, but the case where the transistor pair is a P differential amplifier composed of a PMOS transistor. However, similar control is possible.

DESCRIPTION OF SYMBOLS 1 Gradation potential production | generation part 2 Data latch 3 Extraction part 4 Decoder 5 Drive part 6 Differential stage bias transistor 7, 8 Differential stage transistor 9, 10 Current mirror transistor 11, 12 Output stage transistor 13 Offset cancellation block 14 1st variable Resistor 15 Second variable resistor 16 Image display panels 21 to 24 Transistor 30 Control unit 100 Image display panel driver

Claims (3)

An image display panel driver that sequentially supplies a luminance potential to an image display panel according to sequentially supplied image data,
A gradation potential generation section for generating a plurality of gradation potentials;
A decoder for sequentially selecting the plurality of gradation potentials based on the image data;
A driving unit that generates the luminance potential based on the selected gradation potential and sequentially supplies the luminance potential to the image display panel;
An extraction unit that extracts at least one digit bit of a plurality of digits constituting the image data as a control bit,
The drive unit is
A differential input transistor pair in which each operation current terminal is commonly connected to a constant current source and the gradation potential is input to a control terminal of one transistor;
A current mirror transistor pair, each operating current terminal connected to the remaining operating current terminal of the differential input transistor pair;
It is composed of two variable resistors connected between the remaining operating current terminal of the current mirror transistor pair and a power supply potential, and at least one of the two variable resistors is a variable composed of at least two resistors connected in parallel to each other. A resistance pair,
An output driver that generates and outputs the luminance potential based on the current value of the control terminal of the other transistor of the differential input transistor pair;
A control unit that disconnects at least one of the at least two resistors according to a bit value of the control bit and changes a resistance value of the variable resistor pair;
And adjusting the height of the luminance potential in accordance with the control bit. The decoder selects a gradation potential indicating the gradation when the gradation indicated by the image data is an even gradation, and applies when the gradation indicated by the image data is an odd gradation. 2. The image display panel driver according to claim 1, wherein a gradation potential indicating a gradation smaller than a gradation by a unit gradation is selected . 3. The image display panel driver according to claim 2 , wherein the total number of gradation potentials is half of the total number of gradations indicated by the image data .

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