CN101303834A - Digital-to-analog converter and method thereof - Google Patents
Digital-to-analog converter and method thereof Download PDFInfo
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- CN101303834A CN101303834A CNA2007101017508A CN200710101750A CN101303834A CN 101303834 A CN101303834 A CN 101303834A CN A2007101017508 A CNA2007101017508 A CN A2007101017508A CN 200710101750 A CN200710101750 A CN 200710101750A CN 101303834 A CN101303834 A CN 101303834A
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Abstract
The invention relates to a digital simulation converter which generates corresponding voltage by responding to gray grade values, comprising a decoding device and an operational amplifier. The decoding device comprises a first decoding unit and a second decoding unit. By responding to the first group values of the gray grade values, the first decoding unit regards a first group voltage as a first voltage and a second voltage. By responding to the maximum value and the minimum value of the second group values of the gray grade values, the second decoding unit respectively regards a first boundary voltage as the first and the second voltages, and a second boundary voltage as the first and the second voltages. By responding to the interval values of the second group values, the second decoding unit regards the first and the second boundary voltages as the first and the second voltages. The operational amplifier can generate pixel voltage according to the first and the second voltages, the level of which lies between the first and the second voltages.
Description
Technical field
The present invention relates to a kind of digital simulation (Digital To Analog, D/A) converter, and particularly relate to and a kind ofly find out digital analog converter with the part numerical range corresponding simulating numerical value of digital numerical value by interpolation method (Interpolation).
Background technology
In the epoch now that development in science and technology is maked rapid progress, LCD has been widely used in electronics and has shown on the product, as TV, computer screen, mobile computer, mobile phone or personal digital assistant etc.The data driver of LCD (Data Driver) comprises analog digital (Digital To Analog, D/A) converter, in order to provide pixel voltages to display panels according to GTG value (GrayLevel), the scanner driver (ScanDriver) of arranging in pairs or groups in addition is scanned up to pixel voltages in each picture element of display panels, wants the image that shows to demonstrate.
Owing to be that non-linear (Non-Linear) concerns between the pixel voltages GTG value corresponding with it, the conventional digital analog converter is that to change the GTG value be pixel voltages by praising agate voltage (Gamma Voltage) resistance string, imports display panels afterwards.Yet along with the display quality to LCD requires constantly to promote, the jumbo thereupon increase of progression of the bit of GTG value (Bit) quantity and good agate voltage resistance string.So will make digital analog converter need take jumbo circuit area circuit, and cause its cost to improve thereupon.And adopt each numerical code all to carry out the mode of interpolation (Interpolation) traditionally, and reduce the design of digital analog converter, it is higher also to have the pixel voltages error, and the relatively poor shortcoming of liquid crystal display displays picture quality.
Summary of the invention
The present invention relates to a kind of digital simulation (Digital To Analog, D/A) converter and method thereof, it can improve effectively, and circuit area is big in the conventional art, cost is higher and whole numerical code interpolation (Interpolation) causes the higher shortcoming of pixel voltages error, and has in fact that area is less, cost is lower, the pixel voltages error is lower and the display frame quality of the LCD of its application advantage preferably.
The present invention proposes a kind of digital analog converter, produces corresponding voltage in order to the numerical value in response to GTG value (GrayLevel), and it comprises decoding device and operational amplifier (Operational Amplifier).Decoding device comprises first decoding unit and second decoding unit.First decoding unit is responded first group of numerical value of GTG value, with first group of voltage of correspondence as first voltage and second voltage.Second decoding unit in order to the greatest measure in second group of numerical value responding the GTG value with first boundary voltage as first and second voltage, respond in second group of numerical value minimum value with second boundary voltage as first and second voltage and respond interval numerical value in second group of numerical value with first and second boundary voltage respectively as first and second voltage.Operational amplifier produces pixel voltages according to first and second voltage, and its standard is between first and second voltage.
Propose a kind of digital-to-analogue conversion method according to another object of the present invention, be applied in the source electrode driver (Source Driver), in order to respond a plurality of numerical value of GTG value, to produce corresponding a plurality of voltages.Analog-digital conversion method comprises the following steps.At first, respond first group of numerical value of GTG value, be used as first voltage and second voltage with first group of voltage of correspondence.Then, respond the greatest measure of second group of numerical value of GTG value, with first boundary voltage as first and second voltage.Then, respond the minimum value of second group of numerical value, with second boundary voltage as first and second voltage.Then, respond the intermediate value of second group of numerical value, respectively with first and second boundary voltage as first and second voltage.Afterwards, carry out interpolation method to obtain output voltage according to first and second voltage, its standard is between first and second voltage.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 shows the calcspar of the digital analog converter of one embodiment of the present invention.
Fig. 2 shows the calcspar of the data driver of using digital analog converter of the present invention.
Fig. 3 shows the good Maqu line between GTG value GS and pixel voltages PV in the present embodiment.
Fig. 4 shows the logical operation table of comparisons of decoding device 21 among Fig. 1.
Fig. 5 shows the circuit diagram of logic Unit 211 of present embodiment first decoding unit.
Fig. 6 shows the circuit diagram of the logical block 212 of present embodiment first decoding unit.
Fig. 7 shows the circuit diagram of the logical block 213 of present embodiment first decoding unit.
Fig. 8 shows the circuit diagram of logical block 214 of second decoding unit of present embodiment.
Fig. 9 shows the circuit diagram of logical block 2151 of second decoding unit of present embodiment.
Figure 10 shows the circuit diagram of logical block 216 of second decoding unit of present embodiment.
Figure 11 shows the circuit diagram of logical block 217 of second decoding unit of present embodiment.
Embodiment
Please refer to Fig. 1 and Fig. 2, Fig. 1 shows the calcspar of the digital analog converter of one embodiment of the present invention, and Fig. 2 shows the calcspar of the data driver of using digital analog converter of the present invention.Digital simulation (Digital To Analog, D/A) converter 20 is applied in the data driver 10, pass through part hardware in the data driver 10 in order to conversion, as GTG value (Gray Level) GS after data working storage 11, linear latch device 13 and level shifter 14 processing is corresponding pixel voltages PV, exports pixel voltages PV to the display panels (not shown) by output buffer 15 afterwards.
Digital analog converter 20 comprises decoding device 21 and operational amplifier (OperationalAmplifier) 22.Decoding device 21 receives first group of voltage, first and second boundary voltage and GTG value GS.Comprise that with GTG value GS the numerical data DT0～DT7 of 8 bits (Bit) is that example explains in the present embodiment.Decoding device 21 comprises first decoding unit and second decoding unit, and first decoding unit is in order to first group of numerical value in response to GTG value GS, with first group of voltage of correspondence as voltage O1 and O2.
Second decoding unit is in order to respond the minimum value in second group of numerical value of GTG value GS, with first boundary voltage of correspondence as voltage O1 and O2, and in response to the greatest measure in second group of numerical value of GTG value GS, with second boundary voltage of correspondence as voltage O1 and O2; Second decoding unit is also responded interval numerical value in second group of numerical value, respectively with first and second boundary voltage as voltage O1 and O2.
So, the digital analog converter 20 of present embodiment can be divided into first group and second group of numerical value with the numerical range of GTG value GS.When GTG value GS equaled first group of numerical value, voltage O1 and O2 were for equal in fact, and this moment, digital analog converter 20 did not have the computing effect of interpolation method in fact.When GTG value GS equaled second group of numerical value, voltage O1 and O2 equaled first and second corresponding boundary voltage respectively, and so, this moment, the digital analog converter 20 of present embodiment can be carried out interpolation method to produce pixel voltages PV.So, digital analog converter 20 can flexibly be chosen in the good Maqu line (Gamma Curve) between GTG value GS and pixel voltages PV linear (Linear) and more nonlinear numerical range, try to achieve corresponding pixel voltages in the mode of interpolation method computing and traditional resistor dividing potential drop respectively, can improve the shortcoming that the digital analog converter area is big in the conventional art, cost is higher and the pixel voltages error is bigger effectively simultaneously.
Please refer to Fig. 3, it shows the good Maqu line between GTG value GS and pixel voltages PV in the present embodiment.Good Maqu line is comparatively linear between 32～224 o'clock at GTG value GS, and reaches comparatively non-linear greater than 224 o'clock less than 32 in the GTG value.So, first group of numerical value of the GTG value GS of present embodiment comprises 0～31 and 224～255, and first group of corresponding voltage comprises voltage L0～L31 and L224～L255.And the GTG value GS of present embodiment for example comprise 96 groups of second group of numerical value 32～34,34～36,36～38 ... 222～224, intermediate value wherein is above-mentioned interval numerical value, and first and second corresponding boundary voltage comprise respectively voltage L32 and L34, L34 and L36, L36 and L38 ... L222 and L224.
So, when GTG value GS equaled 0～31 and 224～255, voltage L0～L31 that first decoding unit can be corresponding and L224～L255 were used as voltage O1 and O2 output; When GTG value GS equal 32～34,34～36,36～38 ... when maximum in 222～224 or minimum value, second decoding unit can provide corresponding boundary voltage L32 or L34, L34 or L36, L36 or L38 ... one of them is used as voltage O1 and O2 L222 or L224; When the GTG value equal 33,35,37 ... 223 o'clock, second demoder can provide corresponding boundary voltage L32 and L34, L34 and L36, L36 and L38 ... L222 and L224 come respectively as voltage O1 and O2.
Decoding device 21 for example receive Bit data DT0～DT7, DN0～DN7, voltage L0～L31, L32, L34, L36, L38 ... L222 and L224～L255, wherein Bit data DN0～DN7 is respectively the reverse signal of Bit data DT0～DT7.Next, for example the circuit of first and second decoding unit in the decoding device 21 being implemented framework explains.
Please refer to Fig. 4～Fig. 7, Fig. 4 shows the logical operation table of comparisons of decoding device 21 among Fig. 1, Fig. 5 shows the circuit diagram of logic Unit 211 of present embodiment first decoding unit, Fig. 6 shows the circuit diagram of the logical block 212 of present embodiment first decoding unit, and Fig. 7 shows the circuit diagram of the logical block 213 of present embodiment first decoding unit.
First decoding unit comprises logical block 211,212 and 213, logical block 211 and 212 receives voltage L0～L31 and voltage L224～L255 respectively, it is respectively in order to coming in response to Bit data DT0～DT4 and DN0～DN4 with voltage L0～L31 as voltage D, and with voltage L244～L255 as voltage E.For example when GTG value GS equaled 31, picture element data DT4～DT0 was equal to 1, and this moment, logical block 211 was used as voltage D with voltage L31; When GTG value GS equaled 255, picture element data DT4～DT0 was equal to 1, and this moment, logical block 212 was used as voltage E with voltage L255.
Please refer to Fig. 8～Figure 11, Fig. 8 shows the circuit diagram of logical block 214 of second decoding unit of present embodiment, Fig. 9 shows the circuit diagram of logical block 2151 of second decoding unit of present embodiment, Figure 10 shows the circuit diagram of logical block 216 of second decoding unit of present embodiment, and Figure 11 shows the circuit diagram of logical block 217 of second decoding unit of present embodiment.Second decoding unit comprises logical block 214,215n, 216 and 217, and n is a natural number.
Each logical block 215n is for example in order to receiving 15 groups of boundary voltages, and in order to select two boundary voltages to come respectively as voltage A and voltage B in response to Bit data DT2～DT7, DN2～DN7, controlling signal DTD and DND, its logical operation as shown in Figure 4.For example when GTG value GS equaled 33, Bit data DT2～DT7 equaled 0,0,0,1,0 and 0 respectively, and Bit data DN2～DN7 equals 1,1,1,0,1 and 1 respectively, and controlling signal DTD and DND equal 0 and 1 respectively.This moment, logical block 2151 provided boundary voltage L32 and L34 to come respectively as voltage A and B.
Though present embodiment is that example explains with the logical block 2141 that logical block 215 receives boundary voltage L32 and L34, L34 and L36, L36 and L38...L60 and L62 only, however receive other boundary voltage L64 and L66, L66 and L68 ... the operation of the logical block 215n of L222 and L224 can be analogized according to the narration of the logical block 2151 of present embodiment and obtained.
Logical block 214 is according to Bit data DT0～DT2 actuating logic computing DTD=DT2+DT1*DT0, and with generation controlling signal DTD, and according to controlling signal DTD generation controlling signal DND, wherein controlling signal DND and DTD are for reverse each other.Logical block 216 in order to select in response to Bit data DT3～DT7 and DN3～DN7 boundary voltage L40, L48, L56 ... one of them is used as voltage C L224.
Yet when GTG value GS equals part between 33～233 odd number numerical value, the logical block 2151 of present embodiment can't select suitable boundary voltage to be used as voltage A and B, for example when GTG value GS equals 39, voltage A and B equal boundary voltage L36 and L38 respectively, and operational amplifier 22 can't produce the pixel voltages PV corresponding with GTG value GS 39 according to boundary voltage L36 and L38.This moment, the logical block 217 of present embodiment was to come respectively as voltage O1 and O2 with voltage C and B, and voltage C equals boundary voltage L40.So, operational amplifier 22 can produce the pixel voltages PV corresponding with GTG value GS 39 according to boundary voltage L38 and L40.When GTG value GS equal 47,55,63 ... 223 o'clock, logical block 215n also will produce close in fact problem.This moment, logical block 217 also can be used as voltage O1 and O2 by corresponding voltage B and C, avoided the pixel voltages PV that calculates to produce wrong problem.
Though present embodiment only comprises that with GTG value GS 8 bits are that example explains, yet, the digital analog converter of present embodiment is not limited to the GTG value that comprises 8 bits is carried out digital-to-analogue conversion, and also can to comprise 8 more than the bit or 8 GTG values below the bit carry out digital-to-analogue conversion.And the group technology of the numerical value of first group of GTG value GS and second group also is not limited to the group technology of present embodiment and also can divides into groups by alternate manner in the present embodiment.
The digital analog converter of present embodiment, it is the logical block that to carry out the certain logic computing by being provided with, reach flexibly the numerical range of GTG value is divided into groups, and obtain and the corresponding pixel voltages of different GTG value numerical value grouping with the operational method that is different in essence respectively.The digital analog converter of present embodiment can solve the shortcoming that the digital analog converter area is big in the conventional art, cost is high effectively, and has the less and lower-cost advantage of area in fact.In addition, the digital analog converter of present embodiment also can improve tradition effectively by whole numerical code interpolations are carried out in the technology of digital-to-analogue conversion, higher because of the comparatively non-linear pixel voltages error that produces of the good Maqu line of correspondence easily, and use the second-rate shortcoming of display frame of the LCD of this technology, and it is low to have the pixel voltages error in fact, and uses the display frame quality advantage preferably of its LCD.
In sum, though the present invention with the preferred embodiment disclosure as above, yet it is not in order to limit the present invention.The technical staff in the technical field of the invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking the claims person of defining.
The main element symbol description
10: data driver
11: the data buffer
13: the linear latch device
14: level shifter
15: output buffer
20: digital analog converter
21: decoding device
22: operational amplifier
GS: GTG value
PV: pixel voltages
211,212,213,214,215n, 216,217: logical block
L0～L31, L224～L255: voltage
L32 and L34, L34 and L36 ... L222 and L224: boundary voltage
DT0～DT7, DN0～DN7: Bit data
DTD, DND: controlling signal
O1, O2, A, B, C, D, E: voltage
Claims (12)
1. digital analog converter, in order to respond a plurality of numerical value of GTG value, to produce corresponding a plurality of voltages, described digital analog converter comprises:
Decoding device comprises:
First decoding unit is responded first group of numerical value of described GTG value, is used as first voltage and second voltage with first group of voltage of correspondence; And
Second decoding unit, in order to greatest measure at least one second group of numerical value of responding described GTG value with first boundary voltage as described first with described second voltage, respond in described at least one second group of numerical value minimum value with second boundary voltage as described first with described second voltage and respond in described at least one second group of numerical value at least one interval numerical value with described first and described second boundary voltage respectively as described first and described second voltage; And
Operational amplifier, according to described first and described second voltage produce pixel voltages, the position of described pixel voltages accurate between described first and described second voltage between.
2. digital analog converter according to claim 1, wherein said first group of numerical value comprise the numerical value of m numerical value minimum in the described numerical value of described GTG value, correspond to m voltage that the position is accurate minimum in described first group of voltage, and m is the natural number greater than 1.
3. digital analog converter according to claim 2, wherein said GTG value has k bit, and k is a natural number, and described first decoding unit comprises:
First logical block, be used for i Most Significant Bit (Most Significant Bit) when being logical zero in described GTG value, provide described m the accurate minimum voltage in position to be used as described first and described second voltage, i is for less than k and be relevant to the natural number of m.
4. digital analog converter according to claim 1, wherein said first group of numerical value comprises the numerical value of m numerical value maximum of described GTG value, corresponds to m the voltage that the position is accurate the highest of described first group of voltage.
5. digital analog converter according to claim 4, wherein said first decoding unit comprises:
Second logical block is used for being at 1 o'clock at i Most Significant Bit of described GTG value, and described m position the highest accurate voltage is provided, as described first and described second voltage.
6. digital analog converter according to claim 1, wherein said first group of numerical value comprises the numerical value of described m numerical value maximum and m numerical value minimum, corresponds to described m the voltage that the position is accurate high and minimum respectively.
7. digital analog converter according to claim 6, wherein said first decoding unit comprise described first and described second logical block.
8. according to the described digital analog converter of claim 1, wherein said second decoding unit comprises:
The 3rd logical block, be used for when first bit and second bit are logical one, or the 3rd bit for logical one time output controlling signal, described first, described second and described the 3rd bit be first, second and third Least significant bit (Least Significant Bit) of described GTG value in regular turn.
9. digital analog converter according to claim 8, wherein said second decoding unit comprises:
The 4th logical block, in order to provide in response to j Most Significant Bit of described GTG value and described controlling signal described first and described second boundary voltage one of them as first medium voltage, j is the natural number less than k-1; And
The 5th logical block, in order to j+1 Most Significant Bit in response to described GTG value provide described first and wherein another of described second boundary voltage as second medium voltage.
10. digital analog converter according to claim 9, wherein said second decoding unit also comprises:
The 6th logical block is 1 o'clock at described first bit, or described second bit is 0 o'clock, provides described second medium voltage as described first voltage; Do not provide described first medium voltage as described first voltage at described first bit for 1 o'clock for logical zero and described second bit; And
The 7th logical block, described first and described second bit provide described second medium voltage as described first voltage during for logical zero, and when described first bit is logical one, or described second bit provides described the 3rd medium voltage as described second voltage during for logical one.
11. digital analog converter according to claim 1, wherein said operational amplifier has two anode input ends, receiving described first and described second voltage respectively, described operational amplifier be according to described first and described second voltage carry out interpolation method to obtain described pixel voltages.
12. a digital-to-analogue conversion method is applied in the source electrode driver, produces corresponding a plurality of voltages in order to a plurality of numerical value in response to the GTG value, described analog-digital conversion method comprises:
Respond first group of numerical value of described GTG value, be used as first voltage and second voltage with first group of voltage of correspondence;
Respond the greatest measure of at least one second group of numerical value of described GTG value, with first boundary voltage as described first and described second voltage;
Respond the minimum value of described at least one second group of numerical value, with second boundary voltage as described first and described second voltage;
Respond the intermediate value of described at least one second group of numerical value, respectively with described first and described second boundary voltage as described first and described second voltage; And
According to described first and described second voltage carry out interpolation method obtaining pixel voltages, the position of described pixel voltages accurate between described first and described second voltage between.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102930844A (en) * | 2012-11-12 | 2013-02-13 | 京东方科技集团股份有限公司 | Display device and adjusting method of data voltage |
| CN103516368A (en) * | 2012-06-29 | 2014-01-15 | 瑞鼎科技股份有限公司 | Digital-to-analog converter |
| CN107665689A (en) * | 2017-10-27 | 2018-02-06 | 深圳市华星光电技术有限公司 | Gamma chip, timing controller and liquid crystal display device |
| CN110047439A (en) * | 2018-01-17 | 2019-07-23 | 联咏科技股份有限公司 | Source electrode driver and its operating method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2333408A (en) * | 1998-01-17 | 1999-07-21 | Sharp Kk | Non-linear digital-to-analog converter |
| US6326913B1 (en) * | 2000-04-27 | 2001-12-04 | Century Semiconductor, Inc. | Interpolating digital to analog converter and TFT-LCD source driver using the same |
| KR100517734B1 (en) * | 2003-12-12 | 2005-09-29 | 삼성전자주식회사 | Apparatus and Method for Converting Digital Data to Gamma Corrected Analog Signal, Source Driver Integrated Circuits and Flat Panel Display using the same |
| CN100521547C (en) * | 2004-07-30 | 2009-07-29 | 瀚宇彩晶股份有限公司 | D/A converter and D/A converting method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103516368A (en) * | 2012-06-29 | 2014-01-15 | 瑞鼎科技股份有限公司 | Digital-to-analog converter |
| CN103516368B (en) * | 2012-06-29 | 2016-12-21 | 瑞鼎科技股份有限公司 | Digital-to-analog converter |
| CN102930844A (en) * | 2012-11-12 | 2013-02-13 | 京东方科技集团股份有限公司 | Display device and adjusting method of data voltage |
| CN107665689A (en) * | 2017-10-27 | 2018-02-06 | 深圳市华星光电技术有限公司 | Gamma chip, timing controller and liquid crystal display device |
| CN107665689B (en) * | 2017-10-27 | 2020-06-05 | 深圳市华星光电技术有限公司 | Gamma chip, time sequence control chip and liquid crystal display device |
| CN110047439A (en) * | 2018-01-17 | 2019-07-23 | 联咏科技股份有限公司 | Source electrode driver and its operating method |
| US10755655B2 (en) | 2018-01-17 | 2020-08-25 | Novatek Microelectronics Corp. | Source driver and operation method for improving display quality |
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