TWI466237B - Method of fabricating memory - Google Patents

Description

Memory manufacturing method

The present invention relates to a method of manufacturing a memory.

Non-volatile memory is widely used in personal computers and electronic devices because it has the characteristics of storing, reading, and erasing data many times, and the stored data does not disappear after power-off. As the size of non-volatile memory is gradually reduced, in order to overcome the limitation of the resolution of the light source in the lithography process, a double patterning process has been developed to increase the integration of components.

However, in order to simultaneously define the conductor pattern of the active area and the peripheral area, usually at least three masks are used. For example, the first mask is used to define the minimum line width and spacing of the mask layer (L/S). The second mask is used to cut the unnecessary mask pattern, and the third mask is used to form the conductor pattern of the active area and the peripheral area, wherein the conductor patterns of the active area and the peripheral area are formed of the same conductor material. In general, in order to increase the operating speed of the component, the conductor pattern of the peripheral region is preferably formed of a low resistance conductor material as compared to the conductor pattern of the active region. Therefore, after the above-described process using the three masks, the contact window and the contact plug and the like are usually formed with a low-resistance conductor material in the peripheral region to be electrically connected to the conductor pattern of the peripheral region. However, this increases the manufacturing steps and costs of the memory components.

The invention provides a method of manufacturing a memory to improve the performance of a peripheral zone.

The present invention provides a method of manufacturing a memory. A substrate is provided, the substrate including an active region and a peripheral region. A first conductor layer is formed on the substrate. Forming a mask pattern on the first conductor layer, the mask pattern comprising a first linear pattern in the active region and a U-shaped pattern in the peripheral region, the U-shaped pattern having a second linear pattern, a third linear pattern, and a fourth linear pattern The second linear pattern and the third linear pattern are connected to both ends of the fourth linear pattern, such that the second linear pattern, the third linear pattern, and the fourth linear pattern form a first opening, and the end of the first linear pattern and the U shape The positions other than the ends of the second linear pattern of the pattern are connected. The mask pattern is trimmed to reduce the line widths of the first line pattern, the second line pattern, the third line pattern, and the fourth line pattern. An insulating pattern is formed on the sidewalls of the mask pattern by self-alignment, and the insulating pattern fills the first opening. The mask pattern is removed such that the insulating pattern has a trench exposing a portion of the first conductor layer, the contour of the trench corresponding to the contour of the mask pattern. A portion of the insulating pattern is removed such that the insulating pattern has a second opening, and the second opening is in communication with the trench. The first conductor layer is patterned by using the insulating pattern as a mask to form the first conductor pattern and the second conductor pattern in the active region and the peripheral region, respectively. Remove the insulation pattern. A dielectric layer is formed on the substrate, and the dielectric layer is between the first conductor pattern and the second conductor pattern. A third conductor pattern electrically connected to the second conductor pattern is formed on the dielectric layer.

The above described features and advantages of the present invention will be more apparent from the following description.

1A-11A are schematic top views showing a method of fabricating a memory according to an embodiment of the present invention, and FIG. 1B to FIG. 11B. Further, it is a schematic cross-sectional view taken along lines I-I' and II-II' of Figs. 1A to 11A. In particular, the mask layer including a plurality of mask patterns is generally used for the memory fabrication. Therefore, in order to clearly indicate the line width and the pitch of the mask pattern, FIG. 1B to FIG. 11B are I-I'. The line is illustrated along the cross-sectional view of the three mask patterns as an example.

Referring to FIG. 1A and FIG. 1B simultaneously, first, a substrate 100 is provided. The substrate 100 includes an active region 102 and a peripheral region 104. The substrate 100 is, for example, a semiconductor substrate such as an N-type or P-type germanium substrate, a tri-five semiconductor substrate, or the like. In this embodiment, the barrier layer 110 is further formed on the substrate 100. The material of the barrier layer 110 is, for example, a dielectric material.

Next, a first conductor layer 120 is formed on the substrate 100. The material of the first conductor layer 120 is, for example, a metal material having a lower price but a larger resistance. In the present embodiment, the material of the first conductor layer 120 is, for example, tungsten. The method of forming the first conductor layer 120 is, for example, a chemical vapor deposition method.

Then, a mask pattern 130 is formed on the first conductor layer 120 by using a first mask (not shown). The mask pattern 130 includes a first line pattern 132 located in the active region 102 and a U-shape located in the peripheral region 104. Pattern 134. The U-shaped pattern 134 has a second linear pattern 134a, a third linear pattern 134b, and a fourth linear pattern 134c, wherein the second linear pattern 134a and the third linear pattern 134b are connected to both ends of the fourth linear pattern 134c to make the second line shape The pattern 134a, the third line pattern 134b, and the fourth line pattern 134c form a first opening 136. As shown in FIG. 1A, the second linear pattern 134a and the third linear pattern 134b are connected to both ends of the longer side wall of the fourth linear pattern 134c. The end of the first linear pattern 132 and the ㄩ-shaped diagram The position of the second linear pattern 134a of the case 134 is connected at a position other than the end. In the present embodiment, the end of the first linear pattern 132 is, for example, connected to the intermediate portion of the second linear pattern 134a.

In the present embodiment, the mask pattern 130 has, for example, a wrench shape. The material of the mask pattern 130 is, for example, a photoresist material, an insulating material, a semiconductor material, or other suitable material, wherein the semiconductor material includes a material such as carbon, polysilicon or the like. In the present embodiment, the first line width L1 and the pitch S1 (L1/S1) of the first linear pattern 132 located in the active region 102 are, for example, between 80 nm/80 nm and 20 nm/20 nm. The second line width L2 and the pitch S2 (L2/S2) of the second linear pattern 134a, the third linear pattern 134b, and the fourth linear pattern 134c located in the peripheral region 104 are, for example, 40 nm/40 nm to 160 nm/160 nm.

Referring to FIG. 2A and FIG. 2B simultaneously, the masking process 130 is followed by a trimming process TP to reduce the line width L1 of the first linear pattern 132, the second linear pattern 134a, the third linear pattern 134b, and the fourth linear pattern 134c. ', L2', and increasing the pitches S1', S2' of the first linear pattern 132, the second linear pattern 134a, the third linear pattern 134b, and the fourth linear pattern 134c. The trim process TP is, for example, an isotropic etching process. In the present embodiment, after the trimming process TP, the line width L1' and the pitch S1' (L1'/S1') of the first linear pattern 132 located in the active region 102 are, for example, 10 nm / 30 nm to 40 nm / 120 nm. The line width L2' and the pitch S2' (L2'/S2') of the second linear pattern 134a, the third linear pattern 134b, and the fourth linear pattern 134c located in the peripheral region 104 are, for example, 30 nm / 30 nm to 150 nm / 150 nm.

Please refer to FIG. 3A and FIG. 3B simultaneously, and then, in the mask pattern 130 An insulating pattern 140 is formed on the sidewall 130a in self-alignment, and the insulating pattern 140 fills the first opening 136. The material of the insulating pattern 140 and the material of the mask pattern 130 have, for example, a high selective etching ratio. In this embodiment, the material of the insulation pattern 140 may be tantalum oxide, tantalum nitride or other suitable materials. The insulating pattern 140 is formed by, for example, forming a layer of deposited insulating material on the sidewall 130a of the mask pattern 130 and removing a portion of the insulating material layer, such as the first linear pattern 132, the second linear pattern 134a, the third linear pattern 134b, and An insulating pattern 140 as a spacer is formed on the sidewall 130a of the fourth linear pattern 134c. Among them, a method of removing a portion of the insulating material layer is, for example, Reactive Ion Etching (RIE). In the present embodiment, the insulating pattern 140 includes, for example, a first portion 142 surrounding the mask pattern 130, and a second portion 144 filling the first opening 136, wherein the first portion 142 and the second portion 144 The first portion 142 is connected and surrounds the second portion 144. In this embodiment, the first portion 142 includes, for example, a first sub-portion 142a, a second sub-portion 142b, and a third sub-portion 142c, wherein the second sub-portion 142b connects the first sub-portion 142a and the third sub-portion 142c, A sub-portion 142a is coupled to the second portion 144.

Referring to FIGS. 4A and 4B simultaneously, the mask pattern 130 is removed such that the insulating pattern 140 has a trench 146 exposing a portion of the first conductor layer 120, the contour of the trench 146 corresponding to the contour of the mask pattern 130. In the present embodiment, the method of removing the mask pattern 130 is, for example, a dry etching process or a wet etching process. In the present embodiment, the outline of the opening 146 is, for example, a wrench shape.

Please refer to FIG. 5A, FIG. 6A, FIG. 5B and FIG. 6B simultaneously, the removal part The insulating pattern 140 is divided such that the insulating pattern 140 has a second opening 148, and the second opening 148 is in communication with the trench 146. Here, for the sake of clarity, the depiction of the patterned photoresist layer 150 is omitted in FIGS. 5A and 6A. In this embodiment, as shown in FIG. 5A and FIG. 5B, first, the step of removing a portion of the insulating pattern 140 is, for example, forming a photoresist layer (not shown) on the insulating pattern 140, followed by a second mask (not shown). The photoresist layer is exposed to form a patterned photoresist layer 150 having an opening 150a, wherein the opening 150a exposes a portion of the insulating pattern 140. In the present embodiment, the opening 150a is, for example, a second sub-portion 142b exposing the first portion 142 of the insulating pattern 140, wherein the second sub-portion 142b is a portion connecting the first sub-portion 142a and the third sub-portion 142c.

Next, as shown in FIGS. 6A and 6B, the insulating pattern 140 exposed through the opening 150a is removed such that the insulating pattern 140' has a second opening 148, and the second opening 148 is in communication with the trench 146. In the present embodiment, the step of removing the insulating pattern 140 exposed through the opening 150a is, for example, removing the second sub-portion 142b such that the first sub-portion 142a is separated from the third sub-portion 142c, and the sidewall of the second portion 144 is via The second opening 148 is exposed to the outside, that is, the sidewall of the original second portion 144 is surrounded by the first portion 142 and within the first portion 142, but after the second sub-portion 142b is removed, the sidewall of the second portion 144 is passed through the second The opening 148 is exposed. In the present embodiment, the method of removing the second sub-portion 142b is, for example, a reactive ion etching method. After removing the second sub-portion 142b, the insulating pattern 140' includes, for example, a first portion 142 and a second portion 144, wherein the first portion 142 includes, for example, a first sub-portion 142a and a third sub-portion 142c, wherein the first sub-portion 142a Connected to the second portion 144.

Then, the patterned photoresist layer 150 is removed. The method of removing the patterned photoresist layer 150 is, for example, a dry etching process or a wet etching process.

Referring to FIG. 7A and FIG. 7B , the first conductor layer 120 is patterned by using the insulating pattern 140 ′ as a mask to form the first conductor pattern 122 and the second conductor pattern 124 in the active region 102 and the peripheral region 104 respectively. The first conductor pattern 122 has a third line width L3 and a pitch S3 (L3/S3), and the second conductor pattern 124 has a fourth line width L4 and a pitch (not labeled) (L4/S4). In the present embodiment, the third line width L3 of the first conductor pattern 122 is, for example, twice the fourth line width L4 of the second conductor pattern 124. The third line width L3 of the first conductor pattern 122 is substantially between 25 nm and 42 nm. The third line width L3 and the pitch S3 (L3/S3) of the first conductor pattern 122 are, for example, between 10 nm/10 nm and 40 nm/40 nm. The fourth line width L4 and the pitch (L4/S4) of the second conductor pattern 124 are, for example, between 30 nm / 30 nm and 150 nm / 150 nm.

Referring to Figures 8A and 8B simultaneously, the insulating pattern 140' is removed. A dielectric layer 160 is formed on the substrate 100, and the dielectric layer 160 is located between the first conductor pattern 122 and the second conductor pattern 124. In the present embodiment, the method of forming the dielectric layer 160 is, for example, forming a dielectric material layer on the substrate 100, and then performing a planarization process on the dielectric material layer. In the present embodiment, the first conductor pattern 122 and the second conductor pattern 124 include, for example, wires, plugs, or other conductor patterns. Specifically, in another embodiment, the first conductor pattern 122 and the second conductor pattern 124 may also be formed by a damascene process by a reverse tone mask. The field is well known to those of ordinary skill and will not be described here.

Referring to FIG. 9A to FIG. 11A and FIG. 9B to FIG. 11B , a third conductor pattern 170 a electrically connected to the second conductor pattern 124 is formed on the dielectric layer 160 . Here, the illustration of the second conductor layer 170 is omitted in FIGS. 9A and 10A for clarity of the drawing. In this embodiment, first, as shown in FIG. 9A and FIG. 9B, a second conductor layer 170 is formed on the dielectric layer 160, and the second conductor layer 170 covers the dielectric layer 160, the first conductor pattern 122, and the second conductor. Pattern 124. The material of the second conductor layer 170 is, for example, different from the material of the first conductor layer 120. The resistivity of the second conductor layer 170 is, for example, lower than that of the first conductor layer 120. In the present embodiment, the second conductor layer 170 includes, for example, a barrier layer 174, 176 and a conductor layer 172 between the barrier layers 174, 176. The material of the conductor layer 172 is, for example, aluminum, copper or other suitable metal, and the material of the barrier layers 174, 176 is, for example, titanium, titanium nitride or tungsten nitride.

Next, as shown in FIG. 10A and FIG. 10B, a photoresist pattern 180 is formed on the second conductor layer 170 using a third mask (not shown), wherein the photoresist pattern 180 overlaps with the second conductor pattern 124. Referring to FIG. 10A and FIG. 10B simultaneously, in the present embodiment, the formation position of the photoresist pattern 180 is, for example, at least corresponding to the position of the second sub-portion 142b of the first portion 142.

Then, as shown in FIG. 11A and FIG. 11B, the second conductor layer 170 is patterned by using the photoresist pattern 180 as a mask to form a third conductor pattern 170a electrically connected to the second conductor pattern 124. Then, the photoresist pattern 180 is removed. Among them, a method of patterning the second conductor layer 170 is, for example, reactive ion etching (RIE). In the present embodiment, the material of the third conductor pattern 170a is different from the material of the first conductor pattern 122. third The resistivity of the conductor pattern 170a is, for example, lower than that of the first conductor pattern 122. In the present embodiment, the third conductor pattern 170a includes, for example, a patterned barrier layer 174a, 176a and a patterned conductor layer 172a between the patterned barrier layers 174a, 176a. The third conductor pattern 170a may include a pad, a contact or a wire.

In the present embodiment, the insulating pattern 140 is formed by using the mask pattern 130 having a special configuration such as a plate shape, and the insulating pattern 140 of a specific portion is removed as the first and second conductor patterns 122, 124 are formed. The mask layer and the position corresponding to the second conductor pattern 124 form a patterned photoresist layer, and the third region electrically connected to the second conductor pattern 124 can be formed in the peripheral region 104 without additionally increasing the number of masks. Conductor pattern 170a. In detail, first, a mask pattern 130 having a special configuration such as a hand shape is formed by a first mask. Next, the insulating pattern 140 is formed with the mask pattern 130 as a mask. Then, a specific portion of the insulating pattern 140 is removed by the second mask to form an insulating pattern 140' as a hard mask layer. Then, the first conductor layer 120 is patterned by using the insulating pattern 140' as a mask, and the first conductor pattern 122 and the second conductor pattern 124 are formed in the active region 102 and the peripheral region 104, respectively. Then, the patterned photoresist layer 180 is formed by the third photomask at a position corresponding to the second conductor pattern 124, and the patterned photoresist layer 180 is formed on the second conductor pattern 124 of the peripheral region 104. Three conductor pattern 170a. In this way, the third conductor pattern 170a of the peripheral region 104 and the first conductor pattern 122 of the active region 102 can have different materials without increasing the number of masks, thereby improving the performance of the peripheral region 104.

In summary, in one embodiment of the present invention, the mask pattern of a special configuration, the removal of a specific portion of the insulating pattern, and the formation position of the patterned photoresist layer can be achieved without additional masking Under the condition, the third conductor pattern of the peripheral region has a different material from the first conductor pattern of the active region, thereby improving the performance of the peripheral region. For example, the first conductor pattern of the active region and the second conductor pattern having less influence on the memory performance in the peripheral region can be fabricated using a metal (such as tungsten) having a lower cost but a higher resistance value, and the resistance value is A lower metal, such as copper or aluminum, is used to create a third conductor pattern that has a greater impact on memory performance. In this way, the production cost of the memory can be greatly reduced, and the operational performance of the memory can be improved. In addition, since the present invention is achieved by designing a mask pattern having a special configuration and correspondingly configuring a photoresist layer, the method of manufacturing the memory of the present invention can be easily combined with the existing memory system, and This will result in a significant increase in the cost of manufacturing the memory.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

102‧‧‧active area

104‧‧‧The surrounding area

110‧‧‧The barrier layer

120‧‧‧First conductor layer

122‧‧‧First conductor pattern

124‧‧‧Second conductor pattern

130‧‧‧ mask pattern

130a‧‧‧ Sidewall

132‧‧‧First linear pattern

134‧‧‧ㄩ-shaped pattern

134a‧‧‧Second linear pattern

134b‧‧‧third linear pattern

134c‧‧‧fourth linear pattern

136‧‧‧ first opening

140, 140'‧‧‧ insulation pattern

142‧‧‧Part I

142a‧‧‧ first subsection

142b‧‧‧ second subsection

142c‧‧‧ third subsection

144‧‧‧Part II

146‧‧‧ trench

148‧‧‧ second opening

150‧‧‧ patterned photoresist layer

150a‧‧‧ openings

160‧‧‧ dielectric layer

170‧‧‧Second conductor layer

170a‧‧‧3rd conductor pattern

172‧‧‧Conductor layer

172a‧‧‧ patterned conductor layer

174, 176‧‧‧ barrier layer

174a, 176a‧‧‧ patterned barrier

180‧‧‧resist pattern

L1‧‧‧first line width

L2‧‧‧ second line width

L3‧‧‧ third line width

L4‧‧‧4th line width

L1', L2', L3, L4‧‧‧ line width

S1, S1', S2, S2', S3, S4‧‧‧ spacing

TP‧‧‧Finishing process

1A through 11A are schematic top views of a method of fabricating a memory according to an embodiment of the present invention.

1B to 11B are schematic cross-sectional views taken along lines I-I' and II-II' of Figs. 1A to 11A, respectively.

130‧‧‧ mask pattern

132‧‧‧First linear pattern

134‧‧‧ㄩ-shaped pattern

134a‧‧‧Second linear pattern

134b‧‧‧third linear pattern

134c‧‧‧fourth linear pattern

136‧‧‧ first opening

Claims (11)

A method of manufacturing a memory, comprising: providing a substrate, the substrate comprising an active region and a peripheral region; forming a first conductor layer on the substrate; forming a mask pattern on the first conductor layer, the mask The pattern includes a first linear pattern in the active area and a U-shaped pattern in the peripheral area, the U-shaped pattern having a second linear pattern, a third linear pattern, and a fourth linear pattern, wherein the second pattern The linear pattern and the third linear pattern are connected to both ends of the fourth linear pattern such that the second linear pattern, the third linear pattern and the fourth linear pattern form a first opening, and the end of the first linear pattern Connecting to a position other than an end of the second linear pattern of the U-shaped pattern; performing a trimming process on the mask pattern to reduce the first linear pattern, the second linear pattern, the third linear pattern, and the fourth a line width of the line pattern; forming an insulation pattern on the sidewall of the mask pattern by self-alignment, the insulation pattern filling the first opening; removing the mask pattern to make the The pattern has a trench exposing a portion of the first conductor layer, the contour of the trench corresponding to the outline of the mask pattern; the portion of the insulating pattern is removed such that the insulating pattern has a second opening, the second opening The trench is connected; the first conductor layer is patterned by using the insulating pattern as a mask to form a first conductor pattern and a second conductor respectively in the active region and the peripheral region a pattern; removing the insulating pattern; forming a dielectric layer on the substrate, the dielectric layer being between the first conductor pattern and the second conductor pattern; and forming a second conductor on the dielectric layer A third conductor pattern electrically connected to the pattern. The method of manufacturing the memory of claim 1, wherein the insulating pattern comprises a first portion surrounding the mask pattern, the second portion filling the first opening, Wherein the first portion is coupled to the second portion and the first portion surrounds the second portion. The method of manufacturing the memory of claim 2, wherein the first portion includes a first sub-portion, a second sub-portion, and a third sub-portion, wherein the second sub-portion connects the first sub-portion And a third sub-portion, the first sub-portion being coupled to the second portion. The method of manufacturing a memory according to claim 3, wherein the removing the portion of the insulating pattern comprises: removing a portion of the first portion that is not connected to the second portion, the first portion including the separated portion Two portions, wherein the second portion is exposed to the outside via the second opening. The method of manufacturing a memory according to claim 4, wherein the removing the portion of the insulating pattern comprises: removing the second sub-portion in the first portion such that the first sub-portion and the third portion The subsection is separated and the second portion is exposed via the second opening Outside. The method of manufacturing a memory according to claim 2, wherein the method of forming the third conductor pattern comprises: forming a second conductor layer on the dielectric layer, the second conductor layer covering the dielectric layer a first conductor pattern and the second conductor pattern; forming a photoresist pattern on the second conductor layer, wherein the photoresist pattern overlaps the second conductor pattern; and using the photoresist pattern as a mask, the pattern The second conductor layer is formed to form the third conductor pattern. The method of manufacturing a memory according to claim 6, wherein the photoresist pattern is formed at least at a position corresponding to the second portion of the insulating pattern. The method of manufacturing a memory according to claim 1, wherein the material of the first conductor pattern and the second conductor pattern comprises tungsten. The method of manufacturing a memory according to claim 1, wherein the material of the third conductor pattern comprises aluminum. The method of manufacturing a memory according to claim 1, wherein the line width of the first conductor pattern is substantially between 25 nm and 42 nm. The method of manufacturing a memory according to claim 1, wherein a line width of the first conductor pattern is substantially twice a line width of the second conductor pattern.