TWI462455B - Methods, circuits and systems for controlling electrical power to dc loads - Google Patents

Description

Method, circuit and system for controlling power of a DC load [related application]

U.S. Patent Application Serial No. 12/779,179, filed on Jan. 13, 2010, which is hereby incorporated by reference in its entirety herein in

A conventional method of gradually controlling the power to a DC load by connecting a DC power rail to a power-on load using a switching element, which includes various types of pulse trains, such as pulse width modulation (or PWM) And a fixed width pulse (or 〝VF〞) with a varying frequency. Both methods can effectively change the duty cycle of the pulse train, but both have operational disadvantages.

The aspects and embodiments of the present invention are capable of solving the problems described above by providing control pulses having both a fixed frequency and a fixed time period or duration. Such techniques are considered herein or in related applications as 〝FF/FD〞, 〝FFFD〞, 〝FD/FF〞 or 〝FDFF〞 techniques, which are related to fixed frequency fixed duration characteristics of pulses in a pulse train. . The power supplied to the electrical load is varied by varying the number of times, and the pulses are fixed within a set time interval. The FFFD set in accordance with the present invention has significant advantages over the conventional PWM and VF methods, which are described in further detail herein.

Aspects of the present invention are directed to methods of electrically controlling an electrical load using a fixed duration pulse and a fixed frequency.

In an exemplary embodiment, a processing system, a method includes providing a timing signal and determining a desired power level of the electrical load. The method includes generating a control signal that includes a series of control pulses corresponding to a fixed duration and a fixed frequency within the timing signal and corresponding to the desired power level. The control signal can be supplied to an input of a current switch connected to the electrical load to place the switch in one of an on state in each pulse and a off state in each pulse to be in an on state. , causing current to flow from the first potential, through the electrical load, to the second potential.

The method further includes changing the number of pulses over a repeating time period.

The electrical load includes one or more direct current electric motors.

A timing signal is provided, including using a software that utilizes a decrementing or incrementing counter to control the time interval of the control pulse.

The method further includes controlling movement of one or more direct current electric motors.

The method includes generating a control signal comprising using an analog pulse shaping circuit.

The method includes controlling power applied to one or more electric motors.

The method includes controlling power applied to one or more electric light sources.

The method includes controlling the intensity of the optical output of one or more light sources by varying the number of pulses over a repeating time period.

The method includes controlling power applied to one or more heating devices.

The method includes controlling the heat output by varying the number of pulses over a repeating time period.

The method includes controlling power applied to one or more switching power supplies by varying the number of pulses over a repeating time period.

A further aspect of the present invention is directed to a control circuit/device that functions to provide an FFFD power train from which power applied to an electrical load is controlled.

An exemplary embodiment of an FFFD control circuit includes a first power potential and a second power potential and an electrical load. The control circuit can also include a current switch that can be coupled to the electrical load and includes an input to receive a current switching control signal to place the switch in an open state and a closed state. One, comprising a timing loop having a fixed duration of a series of pulses and a fixed frequency within the timing loop to cause a current to flow from the first potential to the second potential during the on state, The load is caused to cause the load to receive power on a timing loop.

The load includes one or more light emitting diodes (LEDs).

The load includes an array of light emitting diodes (LEDs), such as parallel strings of LEDs in series.

This load includes the circuitry of the DC motor.

The DC motor is a brushless DC motor.

This load includes the circuitry of the AC motor.

The FFFD circuit has an initial condition before current flows through the current switch, and during a time period between pulses of the timing cycle, it is longer than a period in which the circuit returns to the initial state after the pulse of the timing cycle .

The number of pulses in the timing cycle will vary from zero to a maximum number, which corresponds to the intensity level of the LED from zero to the maximum intensity.

The load includes a heating element.

The number of pulses in the timing cycle will vary from zero to a maximum number, which corresponds to the thermal output level of the heating element from zero to the maximum heat output.

The circuit can also include a processing device that generates the current switch control signal that is supplied to the current switch and that will time the start and end of each pulse within the timing cycle.

The circuit can also include a second current switch that is coupled to the load.

The circuit can also include a shunt resistor coupled to the first or second current switch and the first or second power potential.

The circuit can also include a shunt diode coupled to the first or second current switch and the first or second power potential.

It will be appreciated that the above embodiments and aspects may be combined or arranged in any actual combination.

Other features of the embodiments of the invention will be apparent from the description, drawings and claims.

Numerous specific details are set forth in the Detailed Description of the Detailed Description of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without the specific details. In other instances, well known structures and techniques are not shown in detail in order to simplify the understanding.

It is to be understood that the foregoing summary of the invention is intended to In addition, with respect to the terms used herein, references to singular forms of elements, unless specifically stated otherwise, are not intended to mean one and only one, and instead one or more. With the word 〝 some mean one or more. The bottom line and/or the italic title and subtitle are used for convenience only, and are not intended to limit the invention, and are not related to the explanation of the description of the invention.

Embodiments of the present invention are directed to control techniques for transmitting or applying power to electrical (including electronic) loads by applying control pulses having a fixed frequency and fixed duration (FFFD). The load is any kind of DC load, although some variations in the circuit are necessary for different applications. This FFFD technology provides more accurate power transfer than prior art (famous PWM and VF technology). This precise power transfer is especially useful for micro-detail operations such as prosthetics, robots, remote control robots on space shuttles, and controlled movement of motorized medical or surgical equipment where subtle touch and precision are important of. Other applications requiring precise motor movement include control of aircraft such as unmanned remotely piloted aircraft, movement of astronomical telescopes, and movement of long range weapons such as naval cannons.

The FFFD technique in accordance with the present invention includes apparatus and/or methods for driving an electrical load (e.g., an electric motor) that is more accurate than pulse width modulation (PWM) or variable frequency (VF) techniques. For example, the PWM changes (1) pulse width and (2) full cycle length for all 2 variable control parameters. The VF changes (1) the pulse length and (2) these pulse frequencies for all two variable control parameters. The use of FFFD technology allows the designer to change (1) the fixed length of the turn-on pulse, (2) the fixed length during the turn-off or recovery, (3) the full time interval of one cycle, and/or (4) the pulse at that time. number. When the electric motor is an electrical load, it is particularly relevant for the precise transfer of the power of each FFFD turn-on pulse, thus allowing for precise motor movement. Thus, the FFFD technique according to the present invention can be advantageously used in place of PWM and/or VF technology.

1A depicts a simplified circuit that schematically illustrates a general technique (system and/or method) 100 of FFFD power control designed in accordance with an exemplary embodiment of the present invention. As shown, the DC load 106 can be connected to and can be powered by current supplied from the positive voltage rail 105 to the negative voltage rail 110. The power switcher 107 can interfere with the flow of this current or let it pass uninterrupted, which is commanded by the control pulse 108. The pattern of pulse train 108 and the effective duty cycle may ultimately determine the effective current through load 106, but as described below, the accuracy, efficiency, and effectiveness of the current depend on the particular pattern of the pulse train. If the power switch 107 is a power field effect transistor (FET) device, then the pulse train 108 (or G pulse) will be applied to the gate of the FET. In other architectures, any type of power switching device, such as a transistor, can be used.

FIG. 1B depicts a simplified circuit 100B that outlines some of the different architectures required for a non-resistive load. Compared to FIG. 1A, FIG. B shows two switching elements 115 and 125. The G pulse train 130 is used for both switches, which can simultaneously isolate the load 120 from both V positive and negative V lines. This may be necessary, for example, when the load 120 is inherently highly inductive, such as having an electric motor. When the inductive load is switched to the off state, the induced current will cause the voltage peak to occur at the negative end of the load 120, so in this case, the shunt diode 140 is necessary to clamp this current to a reasonable voltage. of. Similarly, if the load 120 is necessary for a very precise amount of power, for example, if we expect the switching off condition to be as close as possible to zero, then the shunt resistor 150 will effectively shunt from the leakage current, which will flow through The switching device 115 is in a closed condition.

In the example shown in FIG. 1B, it can be seen that when switching to off, the load 120 is truly in a zero current state, however in FIG. 1A, in the off state, the load 106 can continue to cause leakage current of the switch 107 to flow. through. Obviously, other circuit designs using FFFD technology include only some of these additional components, or even more and different components, which are necessary for variations in unit load and necessary performance for that particular circuit design.

It will be understood that the FFFD technique designed in accordance with the present invention can be used in place of PWM and/or VF techniques. An electrical load that is applied by FFFD technology is essentially any type of component or component that controls the applied power. The power applied to the load can be controlled by varying the number of FFFD pulses over the repeating time period. For example, such loads include, but are not limited to, any of the following: electrical or electric power tools, any kind of electrical lighting (eg, light emitting diode arrays, high density discharge (HID) lighting, etc.), electric heaters and heating elements, fans Motor and air quieters, electric bicycles, motorcycles, speeds, electric golf carts, electronic toys, electric steering, electric boats, electro-hydraulic technology (including their use in lifts, trolleys, manual palletizers), electronics Or electric prostheses, electric toothbrushes, electronic or electric medical equipment (including adjustable beds, wheelchairs, inhalation equipment, artificial heart, dental drill bits), electric pumps, electronic and electric drones, electric mobile devices (including treadmills, ladder climbers) ), electric vehicles (including buses, trains, indoor trams, trolleys, subways), household appliances (including refrigerators), electric gardening tools (including cutting tools, lawn mowers, chain saws, lawn mowers). Exemplary embodiments can be used with brushless DC motors, including those used in linear and rotary actuators or servo motors.

Figure 2 depicts a set of timing diagrams showing the basic concepts of an FFFD method designed in accordance with an exemplary embodiment of the present invention. As shown, a single pulse 201 can turn on a power switch, such as power switch 107 in Figure 1A, for a short time interval equal to the base pulse length. This will supply a set of amounts of power to the load, such as load 106 of Figure 1A. For example, if three times (3X) power is required to be delivered to the load, then three (3) pulses 205 can be locked by a pulse control train, such as pulse train 108 of Figure 1A. These pulses, such as shown by pulse train 108 of Figure 1A, may be formed by the output of a microcomputer or other similar device (e.g., a processor system, such as a CPU or the like) having a logic output. Similarly, if it is claimed that six times (6X) power is required, then six (6) pulses are sent to the power switch, such as power switch 107 of Figure 1A. This pattern can be repeated in the length cycle (or period) Tcycle 211, which can be chosen to be short enough not to cause problems in the load, such as the load 106 of Figure 1A, but long enough to allow the load to be needed The maximum must pulse 108. If the Tcycle (time period period) is too long, the power to the load seems to be uneven, that is, irregular.

Referring continuously to Figure 2, Tcycle 211 is preferably sufficiently long to have a sufficient number of pulses for fine control. For example, if it is desirable to have the load controlled within 1 percentage percent in the power step, then Tcycle 211 will preferably include at least 100 pulse lengths of the periodic pattern 210 length. The decision of the Tcycle is then based on the application, that is, the specific needs of the particular load, such as the load 106 of Figure 1A. If the load is, for example, LED light, the pulses 210 are each a fraction of a microsecond and the Tcycle 211 is a fraction of a millisecond. If the load, such as load 106, is an electric motor of a car, then pulse 201 is, for example, 20 milliseconds, and Tcycle 211 is, for example, 250 milliseconds, depending on design specifications.

3 depicts a set 300 of timing diagrams showing the difference between the FFFD embodiment of the present invention and conventional power control methods of pulse width modulation (PWM) and variable frequency (VF). In PWM, pulse 301 shows the pulse of the minimum time interval. As shown, when three times (3X) power is required, the pulse length 304 will be three times (3X) long. Ideally, the power that pulse 305 will produce is a multiple (X) of pulse 301. As shown later, this is only an ideal situation; this does not happen in real circuits. Pulse stream 310 shows the particular pulse repetition frequency used to supply the power of level 1 in the VF method. In order to supply three times (X) of power, three times (3X) frequency is required to cause pulsed stream 315. Furthermore, in the ideal world, this should supply several times (3X) of power, but in real circuit applications it will appear to have errors.

Figure 4 depicts a collection 400 of timing diagrams that show the shortcomings of PWM technology. Figure 4 shows why PWM is not accurate in real circuits. It is contemplated that pulse 401 is the pulse of the lowest power state of the PWM application. This causes a current flow substantially at 410 to occur. Although ideally, the current should be a square wave function, i.e., the same shape as the control pulse 401, but this real situation has both capacitive and inductive effects. This is true even when the load is completely resistive, the connection circuit must have an effective length of conductor, which must in turn have significant stray capacitance and inductance. Thus, the typical mode of current flow 410 will be distorted due to these non-zero capacitance and inductance values. This rise time is a ring-shaped chopping type that can be easily seen by connecting an oscilloscope probe to a typical circuit. This loop produces an effect on the PWM method. The full current flow resulting from pulse 401 is then represented by the representation 415. Where pulse 420 represents the PWM pulse of level 2 of the PWM example, pulse 420 is as close as possible to twice the length of pulse 401. This result is the current flow shown by diagram 430. Again, in the ideal case, the shape of 430 should be the same shape as control pulse 420, and ideally, the full current flow of 430 would indeed be twice that of current flow 410. In real life circuits, the illustration 430 is a typical representation of true current flow. Due to the ring shape of 410 and 430, the full current flow 435 is not twice as large as 415, but rather some other value (this example is shown in Figure 6).

Figure 5 shows how the FFFD method is more accurate in terms of the power generation increment. In FFFD pulse 501, the instantaneous current flow produced by the load is shown by real life, typical waveform 505. This causes the full current flow shown by curve 510. The FFFD method uses two pulses, which are represented by 520, when twice the amount of power is desired. Because two of these pulses are substantially equal, and each is the same shape and length as 501, the resulting instantaneous current flow 525 is simply two substantially equal modes 525, each of which is substantially identical to 505. Thus, the full current flow 530 generated from the two FFFD pulses 520, which is substantially twice the current flow of 510, is used for a single pulse 501. Even with a real life circuit, with a distinct ring, the two pulses 520 provide twice the power of a pulse 501, as shown.

Figure 6 includes a set 600 of timing diagrams showing the shortcomings of PWM technology. In Figure 6, curve 640 represents the PWM pulse time, which is expected to be 11 times the single time power. In the ideal world, the resulting current packets 1 through 11 produced on the curve 650 will all be equal in time, size and shape, in particular, completely rectangular. However, in real electronic circuits, the physical laws of inductance and capacitance and the governing electron flow velocity cause the true waveform of the resultant current represented by curve 601. In this waveform, we can see that due to the inductive effect of the electron, at 605, the first part of the wave exhibits a rise time. The same inductance will cause current to exceed, as shown at 610, higher than the level encountered in an ideal, full resistance case. The current will then go through a period or a ring, at 615 to 611 of the curve, until finally settled to a stable value, which will be if the PWM pulse is relatively short compared to the maximum full ring time. Never happened. The resultant current envelope for each time interval of the PWM pulses is represented by curve 620. As shown, the time 621 of the first packet will be less than the second packet 622, and each will be different from all others until the ring finally stops, but may not be at the same value as the first pulse. Even when the PWM pulse comes to a pause, the true life cut of the current causes the current represented by 630 to flow. Therefore, the PWM method cannot provide a plurality of single pulses simply by extending the time interval by a complex number. This example only shows the current flow side of the PWM method. When the power response element and the power factor (ie, the instantaneous voltage X instantaneous current) are taken into account, the ideal error is even more distorted. Therefore, control by PWM in an accurate value cannot be obtained.

Figure 7 includes a set 700 of timing waveforms corresponding to an FFFD embodiment of the present invention. Figure 7 shows how the FFFD pulse is not affected by the ring of the real life circuit. For short FFFD pulses, curve 705 is the potential waveform (which is equal to the rise time and ring of 601) when the circuit is switched from off to on, and curve 701 shows the true life current flow through the circuit, above The time distortion is done to complete and the leakage at the trailing edge is turned off. The entire current envelope is represented by 710, which includes all rise time, loop, and turn-off distortion, but is turned off at the end of the basic period of the first pulse. When a plurality of FFFD pulses are supplied to the power switch, the result is a current flow of a plurality of packets, shown as 715. Each 715 current packet is substantially equal to a single package 701. The relaxation time 717 between the FFFD pulses allows the real life circuit to return to the original condition before the first pulse. This means that each pulse 715 has substantially the same initial condition as provided for pulse 705.

Thus, by merely increasing the number of pulses, an integer increment of any power can be generated by the FFFD technique designed in accordance with the present invention. A limiting factor is that the maximum resolution of the power increment must be appropriate for the Tcycle time interval, such as cycle 211 of Figure 2, and when using the FFFD method, these numbers can be selected as part of the design cycle.

The advantage of a fixed duration pulse in FFFD seems to be also applicable to the variable frequency (VF) method, Figures 310, 315, but this is not true and will be explained. Although the turn-on period is the same for all pulses in the VF method, this method has a number of disadvantages. Due to its digital nature, complete generation of all frequencies by a digital computer is not possible. For example, if 1000 Hz can be used as the reference frequency for the lowest required power, and this can be generated every 10 millisecond pulses, then the value for 3 is 3 kHz, or 333.333333 Hz, which cannot be exact The number is obtained. Considering this problem will occur at least for each prime number, and the digital 〝 particle size 〞 will be a larger part of the problem with shorter time intervals because the pulses are more closely together, ie, the performance system is higher. Also consider that in Figure 315, the time between pulses will vary with each change in frequency. This means that the relaxation time (ie, the off time) will vary with the frequency of each different value. As a result, the initial situation is different for each frequency because there will be a different amount of settling time between the pulses. Moreover, for high performance systems, for example, this problem is most prevalent when time changes between pulses are short. By maintaining both this frequency and the pulse-on period, the FFFD technique ensures that the power increment is as close as possible to the theoretical value.

In addition, FFFD technology offers another advantage over VF technology. For example, with FFFD technology, the pulse timing is fixed, which is and can be selected such that there is no radio frequency interference (RFI) at the sensitive frequency. Conversely, due to VF, these frequencies will change and radiate in harmony with many frequencies, which can cause unwanted RFI. This is especially true in applications such as airplanes and hospitals where RFI can cause serious problems. The VF in these cases requires RFI protection, however any RFI will be at a fixed and therefore predictable frequency once the FFFD timing is set. This RFI problem is especially present when the pulses are used to zone the motor because the magnetic field is formed and collapsed by the inherent use of the power of the motor windings.

The FFFD technique designed in accordance with the present invention has significant advantages in other respects. For example, it is used in the drive of an electric motor, U.S. Patent No. 5,442,272, entitled "Electrical Limiting of Electric Motor Startup", which teaches having additional external components to avoid when the DC motor is started from a stop condition. Excessive current flow is necessary. However, by using the FFFD technique, the pulse duration can be selected to produce a pulse power period that does not overdrive the motor windings when the motor is stopped and there is no back EMF. This also avoids excessive current conditions on the mechanical load on the motor that are large enough to stall the motor-pulse duration, and the spacing can be selected such that the winding cannot be allowed to overheat. Due to the PWM, try to compensate the controller of the overloaded motor, which can increase the length of the duty cycle to the one that will damage the relevant motor; FFFD technology can avoid this event.

Most of the electronics can be controlled by computers that use digital circuits. Due to the digital nature of the computer, PWM or VF, the FFFD method is more suitable for computer applications. The computer system operates with a set clock, which means that the operation of the computer instructions (ie, the execution software) only occurs on a specific portion of the computer clock cycle. Basically, the computer clock runs on a plurality of mechanical language instruction sets.

Attention is drawn to Figure 8, which shows a set of waveforms 800 that describe the timing signals of G FFFD pulses generated by a computer or processor designed in accordance with an exemplary embodiment of the present invention.

In FIG. 8, the computer clock signal is displayed by signal 810. In a typical computer chip, the computer-implemented portion of the computer-based instruction (essentially in four parts of the entire computer cycle) occurs substantially every fourth clock cycle (although there are some special types). The state of the computer mechanical instructions will change, but they are still even integer clock cycles). This means that if the computer tries to generate a high, then low, then high state pulse period at the output, then these state changes only occur in the discontinuous time, which is represented by every fourth cycle, This is indicated at 820 in Figure 8, which is looped by the discontinuous time stamp indicated by line 830. Therefore, the fastest pulse is composed of four (4) clock periods, shown at 840.

Referring continuously to Figure 8, at 840 a computer command sets the line high and resets the output to low, which occurs only at 845 at the earliest, or at any time mark 830, but not at any time in between. . For example, in the high period 860 on the graph, it represents three (3) full computer timing cycles of pulses. Pulses between full computer cycles, such as 2.7, are not possible due to the inherent operation of the computer. Similarly, the low or recovered portion of pulses 850, 875 is also an integer value of the number of cycles of the computer. In the example shown, the 850's off or low period is 7 (7) computer cycles long, and in the case of 875, it is nine (9) computer cycles long. Once these two periods, i.e., the high state period 840 or 860 and the low state periods 850, 875 are selected by the user of the FFFD electronic circuit, then the two periods are succinctly copied due to the nature of the computer operation. For this reason, the output port of the computer can only be switched from one state to another state at the discontinuous time 830, and the VF method of controlling the power to the motor or other electrical load becomes completely inaccurate because one A small number of pulses are not possible.

The hardware that produces the G pulse stream or column, such as column 880 of Figure 8, is derived from the selection of the FFFD parameters, which can be obtained in one embodiment by the circuit shown in Figure 9.

As shown, a computer chip labeled as item 930 of the CPU can utilize a computer clock 910, such as a quartz crystal element, to drive the clock frequency 920. As can be seen, 920 can provide a CPU with a clock pulse, such as pulse train 810 of FIG. 8, which is capable of causing I/O (input/output) port 940 to generate G-pulse signal 950, similar to 880 in the figure, when CPU 930 When executing the appropriate software. Of course, the invention is not limited to a particular type of oscillator or clock, and any suitable type can be used with embodiments of the invention.

The software of the CPU, such as the CPU 930, includes or performs the subroutine 1000 shown in FIG. 10 in the exemplary embodiment. In the case of the subroutine 1000, the main software in the CPU calls the subprogram 〝G pulse output signal 〞1000, which starts at 1005, and whenever the G pulse stream is generated, it is at the beginning of each Tcycle, for example Cycle 211 of Figure 2. The user-specified subroutine, for example, at 1010, the number of pulses to be generated N, the length HI of the computer cycle period of the high or open period, the length LO of the low or closed period computer cycle period, and the I/driven by the G pulse stream. Number of O ports S.

The subroutine can confirm that the G pulse stream is in a low state, as described in 1015. It can then set the count of counts to be equal to the number of high periods of instructions issued by 1010, for example equal to HI. If the shortest possible pulse is needed, for example, the count is equal to 1, then in the test of count 1035, the program will be shunted to 1030, which sets the I/O port S high and then at 1060, in the next very close Computer cycle, then reset it to low. If, instead, at instruction 1035, the specified count is greater than one, then I/O port S is set to high, 1040, and by causing instruction 1055 to be shunted to itself via 1050, the computer cycle counts every time. Reduce the number of computers by one cycle. Each loop will consume a computer cycle by itself and will reduce the count until the next cycle when the count is equal to 1, when the program continues to command 1060, it is set to low by setting the SI/O port. And to end the high state. The counted count is then set to the number of computer cycles in which the G pulse should be in a low state (eg, LO). The loop in shunt loop 1070 returns to its own 1080, which reduces the count by one every time it loops until the value reaches zero. When the counter has calculated the period of the number of LOs, the program will continue to 1085. If the number of G pulses during the Tcycle period is one, then a decrement of zero will cause the program to leave the subroutine 1190 until the next Tcycle begins, such as Tcycle 211 of Figure 2, which again calls the subroutine. If the number of pulses is greater than 1, then the decrement N will result in a non-zero value, and the subroutine shunt 1075 will return to 1025, where the next high pulse will be generated. When the number of G pulses for this Tcycle is completed, the N count will be zero and the subroutine will leave from 1085 to 1090.

The result of this subroutine is a G pulse stream, such as 880 of Figure 8, where HI = 1, LO = 7 and N = 3 (as shown) for the top pattern; and for the bottom pattern, HI = 3, LO = 9 and N = 2 (as shown). It is to be noted that the Tcycle (e.g., Tcycle 211 of Figure 2) will be longer than the time interval shown in Figure 8, such that the number N will be higher than those shown separately in Figure 8.

The FFFD technique, in many other embodiments, has a number of FFFD pulses (〝G pulses 产生) produced by analog rather than digital components, which can be explained with respect to FIG.

Figure 11 depicts a circuit outline of an analog circuit 1100 designed to generate FFFD pulses in accordance with an exemplary embodiment of the present invention. In FIG. 11, analog circuit 1100 includes two single-use (or single-shot) components 1150 and 1190, such as a CD4047 CMOS device, or its equivalent in transistor electro-crystalline logic, or other solid state variations. As shown in FIG. 11, the number of pulses 1105 generated by the G pulse during this cycle time is downloaded to the decrement counter 1110. The non-zero state of the counter causes the zero (reverse) line to go high, 1115, to touch 1190 once. One use will output a set duration time pulse 1125 as determined by the resistor capacitor network 1120. In a hardware design, the time interval of the G pulse must be fixed. This architecture is most useful. The adjustment of the resistor capacitor time can be obtained, for example, by using a semi-fixed resistor or tuning capacitor within the resistor capacitor architecture. Pulse 1115 can be inverted by circuit 1140 to provide a reverse pulse 1145 version of 1125. The rising edge of 1145 is then at the same time as the trailing edge of 1125, and touches once using 1150, which is adjusted by resistor capacitor network 1155 to provide a G pulse off or low time, 1160. Furthermore, the resistor capacitor network can be trimmed by a semi-fixed resistor or a tuning capacitor, if desired. Pulse 1160 and pulse 1125 combine back or gate 1165 to provide pulse 1170, which is shown by timing diagram 1195. Pulse 1170 is used to disable the advancement of counter 1110 at the pin/disarm (negative disable line). When pulse 1170 is complete, rising edge 1180 of pulse 1170 allows counter 1110 to advance to the next G pulse. When counter 1110 counts down to zero, it stops issuing pulses to line 1190 via line 1115. At 1130, a G pulse will appear in this circuit. At the end of the Tcycle 211, the next batch of G pulses is output by loading the counter 1110 again with the number of pulses.

Thus, embodiments of the present invention can provide benefits associated with prior art, including PWM and VF techniques. The FFFD technique designed in accordance with the present invention utilizes a power train pulse having a fixed frequency fixed duration pulse to control the power applied to a known electrical load. This load is any type of DC load. For example, embodiments of the present invention may provide precise power control for fine work such as prosthetics, robots, remote robots on a space shuttle, and motorized medical or surgical equipment, where fine touch is important . Other applications requiring precise motor movement include control of aircraft such as unmanned remotely piloted aircraft, movement of astronomical telescopes, and movement of long range weapons such as naval cannons, and the like.

Although the present invention has been described in connection with the specific embodiments, it should be noted that those skilled in the art can change within the spirit of the invention.

Many of the functions and elements described herein can be distinguished from those shown without departing from the spirit and scope of the invention. Various changes to these embodiments will be apparent to those skilled in the art, and the class principles defined herein may be applied to other embodiments. Therefore, many changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Those skilled in the art will appreciate that embodiments and/or portions of the present invention can be implemented with/with a computer readable storage medium (eg, hardware, software, firmware, or any combination of these). And can be distributed across one or more networks. The steps described herein include obtaining, learning, or calculating a processing function of a formula and/or a mathematical mode applied and/or generated by an embodiment of the present invention, which may be processed by one or more suitable processors, such as a central A processing unit (CPU) to implement appropriate code/instructions in any suitable language (hardware dependent or hardware independent).

Furthermore, embodiments of the invention may be implemented with signals and/or carriers, such as control signals transmitted over a communication channel or network. Furthermore, software implementing the methods, processes, and/or algorithms of the present invention can be implemented or carried by electrical signals, for example, for use by the Internet and/or wireless network.

100A. . . Simplified circuit

100B. . . Simplified circuit

105. . . Positive voltage rail

106. . . DC load

107. . . Power switch

108. . . Pulse train

110. . . Negative voltage rail

115. . . Switching element

125. . . Switching element

120. . . load

130. . . G pulse train

140. . . Split diode

150. . . Shunt resistor

201. . . pulse

205. . . pulse

210. . . pulse

211. . . cycle

300. . . set

301. . . pulse

304. . . Pulse length

305. . . pulse

310. . . Pulse flow

315. . . Pulse flow

400. . . set

401. . . pulse

410. . . Current flow

415. . . Full current flow

420. . . pulse

430. . . Current flow

435. . . Full current flow

501. . . pulse

505. . . Wave pattern

510. . . curve

520. . . pulse

525. . . Current flow

530. . . Full current flow

600. . . set

601. . . curve

620. . . curve

640. . . curve

650. . . curve

621. . . First package

622. . . Second packet

630. . . Current flow

700. . . set

701. . . curve

705. . . pulse

710. . . Current packet

715. . . Current packet

717. . . Relaxation time

800. . . Wave set

810. . . Pulse train

830. . . Discontinuous time

840. . . High state period

850. . . Low state period

860. . . High state period

875. . . Low state period

880. . . Column

910. . . Computer clock

920. . . Clock frequency

930. . . CPU

940. . . (input/output) port

950. . . G pulse signal

1000. . . Subprogram

1070. . . Shunt loop

1075. . . Subprogram shunt

1100. . . Analog circuit

1105. . . Number of pulses

1110. . . counter

1115. . . pulse

1120. . . Resistor capacitor network

1125. . . pulse

1140. . . Circuit

1145. . . Reverse pulse

1150. . . One-time use of components

1160. . . pulse

1165. . . Reverse or gate

1170. . . pulse

1180. . . Rising edge

1190. . . One-time use of components

The invention may be more completely understood from the following description, taken in conjunction with the accompanying drawings, which are considered to be illustrative, but not limiting. The drawings are not necessarily drawn to scale, but instead the emphasis is placed on the principles of the invention. In the picture:

1A depicts a simplified circuit that schematically illustrates a method for controlling current flow through a general electrical load using an electronic switcher in accordance with an exemplary embodiment of the present invention;

1B depicts a simplified circuit that schematically illustrates a method for controlling current flow through a load using an electronic switcher in accordance with an exemplary embodiment of the present invention;

2 includes a set of timing diagrams showing basic timing diagrams of pulses for use in FFFD control techniques designed in accordance with an exemplary embodiment of the present invention;

3 includes a set of timing diagrams showing the difference between the FFFD pulse train technique embodiment and the previous PWM pulse method in accordance with the present invention;

Figure 4 includes a collection of waveforms showing inaccuracies of previous PWM methods;

Figure 5 includes a collection of modes of accuracy of an embodiment of an FFFD technique designed in accordance with an exemplary embodiment of the present invention;

Figure 6 includes a collection of waveforms comparing the true life current flow to the ideal current flow of the same pulse;

7 includes a set of waveforms designed to show why a FFFD pulse produces a uniform current flow to each pulse, in accordance with an exemplary embodiment of the present invention;

8 includes a collection of waveforms of timing signals of a G FFFD pulse generated by a display computer or processor designed in accordance with an exemplary embodiment of the present invention;

9 is a circuit diagram of a processor system for generating a G-pulse of FFFD power control technology in accordance with an architecture designed in accordance with an exemplary embodiment of the present invention;

10 depicts a flow diagram of generating a G FFFD pulse by a processor system designed in accordance with an exemplary embodiment of the present invention;

Figure 11 depicts an overview of the circuitry of an analog circuit designed to generate FFFD pulses in accordance with an exemplary embodiment of the present invention.

Although the specific embodiments are described in the drawings, it will be understood by those skilled in the art that the described embodiments are not illustrative and those illustrated and other embodiments described herein may be It is conceived and implemented within the scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as

100A. . . Simplified circuit

105. . . Positive voltage rail

106. . . DC load

107. . . Power switch

108. . . Pulse train

110. . . Negative voltage rail

Claims (25)

A method of using a fixed duration and a fixed frequency pulse for power control of an electrical load, the method comprising: providing a timing signal to a circuit in a processing system, wherein the timing signal includes an on state and a shutdown a state in which a desired power level for an electrical load is determined; a control signal is generated based on the timing signal, comprising a fixed duration and a fixed frequency of a series of control pulses within the timing signal, And corresponding to the desired power level; and supplying the control signal to an input connected to one of the electrical load current switches, in the circuit to place the switch in one of each pulse period One of an open state and one of a closed state after each pulse to cause a current to flow from a first potential through the electrical load to a second potential during the on state; wherein the circuit has current flow After the previous start condition of the current switch, and during the time period between the pulses of the timing cycle, the system will be compared to the time of the sequence From a longer time after the pulse circuit back to the starting conditions. The method of claim 1, further comprising changing the number of pulses in a repeating time period. The method of claim 1, wherein the electrical load comprises one or more direct current electric motors. The method of claim 1, wherein a timing signal is provided, comprising using a software that utilizes a decrementing or incrementing counter to control the time interval of the control pulse. The method of claim 3, further comprising controlling movement of the one or more direct current electric motors. The method of claim 1, wherein the generating a control signal comprises using an analog pulse shaping circuit. The method of claim 6, further comprising controlling the power applied to the one or more electric motors. The method of claim 1, further comprising controlling the power applied to the one or more electric light sources. The method of claim 8, further comprising controlling the intensity of the optical output of the one or more sources by varying the number of pulses over a repeating period of time. The method of claim 1, further comprising applying a control power to the one or more heating devices. The method of claim 10, further comprising controlling the heat output by varying the number of pulses over a repeating time period. The method of claim 1, further comprising controlling the power applied to the one or more switching power supplies by varying the number of pulses over a repeating time period. An FFFD power control circuit comprising: a first potential; a second potential; An electrical load; and a current switch coupled to the electrical load and including an input to receive a current switching control signal to place the switch in one of an open state and a closed state, The system includes a timing cycle having a fixed duration of a series of pulses and a fixed frequency within the timing cycle to cause a current flow from the first potential through the load to the second potential during an on state In order to cause the load to receive power on a timing loop, wherein the circuit has a starting condition before current flows through the current switch, and during a period of time between pulses of the timing period, the system is pulsed compared to the timing period Later, the circuit will return to the starting condition for a longer time interval. The circuit of claim 13, wherein the load is a light emitting diode (LED). The circuit of claim 13, wherein the load comprises an array of light emitting diodes. The circuit of claim 13, wherein the load comprises a circuit of a DC motor. The circuit of claim 16, wherein the DC motor is a brushless DC motor. The circuit of claim 13, wherein the load comprises a circuit of an AC motor. The circuit of claim 14, wherein the number of pulses in the timing period varies from zero to a maximum number, which corresponds to an intensity level of the LED from zero to a maximum intensity. The circuit of claim 13, wherein the load comprises a heating element. A circuit as claimed in claim 20, wherein the number of pulses in the timing period varies from zero to a maximum number corresponding to a thermal output level of the heating element from zero to a maximum heat output. The circuit of claim 13 further comprising a processing device that generates the current switching control signal supplied to the current switch and will time the beginning and end of each pulse within the timing cycle. The circuit of claim 13 further comprising a second current switch connected to the load. The circuit of claim 23, further comprising a shunt resistor connected to the first or second current switch and the first or second potential. The circuit of claim 23, further comprising a shunt diode connected to the first or second current switch and the first or second potential.