TWI462261B - A co-package of high side and low side mosfets and its method - Google Patents

Description

Semiconductor component combining high-end and low-end wafers and method of manufacturing the same

The present invention relates to a package structure and a manufacturing method of a semiconductor device, and more particularly to a semiconductor device incorporating a packaged high-end and low-end wafer and a method of fabricating the same.

In power transistor applications, the size and heat dissipation of semiconductor components are two important parameters. The heat dissipation performance of the semiconductor device is usually improved by exposing the gate and the drain of the transistor, but the implementation process is often complicated.

In some switching circuits, such as synchronous buck converters, half-bridge converters, and inverters, two power MOSFETs are required to switch in a complementary manner. The switching circuit shown in FIG. 1 includes two series-connected MOSFETs connected to the voltage source 3, which are generally referred to as high-end and low-side MOSFET chips (referred to as high-end wafer 1 and low-end wafer, respectively). 2). The source of the high-end wafer 1 is connected to the drain of the low-end wafer 2 via a plurality of parasitic inductances LDHS, LSHS, LDLS, LSLS.

For these semiconductor elements, if the high-end wafer and the low-end wafer can be packaged at the same time, and the two wafers are connected by wires inside the package, the lead inductance can be reduced. In actual operation, the high-end wafer and the low-end wafer are generally arranged side by side on the same side of the lead frame, but such a planar configuration makes the size of the entire semiconductor element relatively large.

It is an object of the present invention to provide a semiconductor device incorporating a packaged high-end and low-end wafer and a method of fabricating the same, by stacking a high-end wafer and a low-end wafer on both sides of a lead frame, thereby stacking the three to reduce the entire semiconductor component size of. And, the back side of the wafer can be directly exposed or exposed to the outside of the package via the heat sink to improve heat dissipation performance.

In order to achieve the above object, a technical means of the present invention is to provide a semiconductor device incorporating a packaged high-end and low-end wafer, comprising: a conductive lead frame provided with a carrier base; a high-end wafer and a low-end wafer, each of which a top source, a top gate and a bottom drain are disposed, wherein the top source of the high-end wafer is provided with a plurality of conductive source solder balls, and the top gate is provided with a plurality of conductive gate solder balls; The back side of the low-end wafer is fixedly connected to the front surface of the lead frame, and the bottom of the low-end wafer is electrically connected to the top surface of the slide base, and the front surface of the high-end wafer is fixedly connected to the back surface of the lead frame, and The top source of the high-end wafer is electrically connected to the bottom surface of the carrier base by the plurality of source solder balls; and the semiconductor component further comprises a package, and the low-end wafer and the lead frame of the lead frame are sequentially stacked. The pedestal and the high-end wafer are molded in the package, and the back surface of the high-end wafer is exposed outside the package on the back surface of the semiconductor element for heat dissipation.

The lead frame further includes a first pin, a second pin, a third pin, and a fourth pin electrically connected to the carrier base, which are separated from the carrier base and electrically connected.

The bottom drain of the low-end wafer and the top source of the high-end wafer are respectively connected The two sides of the chip base are electrically connected to the external semiconductor component by the fourth pin.

The top gate of the high-side wafer is electrically connected to the third pin by a plurality of gate solder balls.

The rear surface of the high-end wafer is covered with a heat dissipating component. After the semiconductor component is packaged, the heat dissipating component is exposed outside the package body on the back surface of the semiconductor component, and the bottom drain of the high-end wafer is electrically connected to the external component by the exposed heat dissipating component. .

The heat sink is a metal layer having a certain thickness formed by evaporation sputtering on the back side of the high-end wafer. Alternatively, the heat sink is a conductive metal patch adhered to the back side of the high end wafer.

The top source of the low-end wafer is electrically connected to the first lead by a metal connecting piece, and the top gate of the low-end wafer is electrically connected by another metal connecting piece provided To the second pin.

Between the metal connecting piece and the low-end wafer, a high-temperature alloy is disposed between the metal connecting piece and the first pin and the second pin to be adhesively bonded and electrically connected.

A high-temperature alloy is provided between the low-end wafer and the carrier base of the lead frame so that the two are adhered to each other and electrically connected.

On the top source and the top gate of the high-end wafer, a plurality of corresponding solder balls are respectively made of a low temperature alloy.

Another technical means of the present invention is to provide a method for fabricating a semiconductor component that packages a high-end and low-end wafer, comprising the following steps: Step 1. A lead frame is formed from a conductive material, and a carrier substrate is disposed on the lead frame corresponding to each semiconductor component; and step 2, a front surface of a plurality of low-end wafers is formed on a front surface of a low-end semiconductor wafer. a source and a top gate, on the back side of the wafer, corresponding to the bottom bucks of the plurality of low-end wafers, the wafer is diced and separated to form the plurality of low-end wafers; and step 3, in a high-end semiconductor wafer The front side of the wafer is corresponding to the top source and the top gate of the plurality of high-end wafers. On the back side of the wafer, the bottom drain of the plurality of bottom wafers is correspondingly formed, and the top and top gates of the high-end wafer are borrowed. The ball is formed by correspondingly forming a plurality of conductive source solder balls and gate solder balls, and then the wafer is cut and separated to form a plurality of the high-end chips; in step 4, the low-end wafer faces up, and the low-end wafer is The back side is adhered to the front surface of the lead frame, so that the bottom of the lead is electrically connected to the top surface of the slide base; in step 5, the lead frame is turned over so that the back side faces upward, so that the front side of the high-end wafer faces downward. The front side of the high-end wafer is adhered to the back surface of the lead frame, and the top source is electrically connected to the bottom surface of the carrier base by a plurality of source solder balls, thereby electrically connecting the bottom of the low-end wafer. Connecting; step 6, by molding, the sequentially stacked low-end wafer, the carrier base of the lead frame, and the high-end wafer are all encapsulated in the package, and the back surface of the high-end wafer is exposed on the back surface of the semiconductor component In addition, the bottom of the bottom is electrically connected to the external component and heat is dissipated; and in step 7, the individual semiconductor components on the lead frame are separated by shear molding.

In step 3, a metal layer having a certain thickness is formed by evaporation on the back side of the high-end wafer by a gate metallization process, or a conductive metal patch is pasted on the back surface of the high-end wafer; After the semiconductor device is packaged in step 6, the metal layer or metal patch is exposed to the outside of the package on the back side of the semiconductor device for heat dissipation.

In step 1, corresponding to each semiconductor component, a first pin, a second pin, a third pin, and a carrier base separated from the carrier base and electrically connected to the substrate are further disposed on the lead frame. The fourth pin of the electrical connection.

In the step 4, the top source and the top gate of the low-end wafer are electrically connected to the first pin and the second pin of the lead frame by metal connecting pieces, respectively.

In step 5, the top gate of the high-side wafer is electrically connected to the third pin of the lead frame by the plurality of gate solder balls.

After the step 5, the bottom drain of the low-end wafer and the top source of the high-end wafer are respectively connected to both sides of the carrier base, so as to be electrically connected to the external component by the fourth pin.

In step 4, a high temperature alloy is used as the between the low-end wafer and the carrier base, between the metal connecting piece and the low-end wafer, and between the metal connecting piece and the first pin and the second pin. Sexually bonded bonding material.

In step 3, a plurality of solder balls corresponding to the top source and the top gate of the high-end wafer are respectively made of a low temperature alloy.

In the semiconductor component of the packaged high-end and low-end chip of the present invention, the low-end wafer and the high-end wafer are respectively located on the upper and lower sides of the lead frame, and the three form a three-dimensional stack. The structure is effective in reducing the size of the entire semiconductor element compared to the prior art in which the low-end and high-end wafers are attached side by side to the same side of the lead frame. In addition, the present invention uses a metal layer or a conductive metal patch covered on the bottom of the high-end wafer as a heat sink, and is exposed outside the back surface of the packaged semiconductor element, thereby effectively improving the heat dissipation performance of the semiconductor element.

1, 300‧‧‧ high-end chips

100‧‧‧ lead frame

110‧‧‧Slide base

121‧‧‧First pin

122‧‧‧second pin

123‧‧‧ third pin

124‧‧‧fourth pin

2, 200‧‧‧ low-end wafer

211‧‧‧ source

212‧‧‧ gate

220‧‧‧High temperature alloy

230‧‧‧Metal connecting piece

3‧‧‧voltage source

311‧‧‧Source solder balls

312‧‧‧ gate solder balls

320‧‧‧metal layer

320’‧‧‧Metal patch

400‧‧‧Package

1 is a circuit model of a synchronous buck converter in the prior art, in which a source of a high-end chip is electrically connected to a drain of a low-end wafer; and FIG. 2 is a high-end and low-end chip of the package of the present invention. FIG. 3 is a schematic view showing the connection of a low-end wafer and a lead frame in the semiconductor device of the present invention; and FIG. 4 is a schematic structural view of a high-end wafer in the semiconductor device of the present invention; The figure is a schematic diagram of the connection of the high-end wafer and the lead frame in the semiconductor device of the present invention; and FIG. 6 is a side view of the low-end wafer and the high-end wafer of the semiconductor device respectively connected to the upper and lower sides of the lead frame; The front view of the semiconductor device after packaging according to the present invention; FIG. 8 is a schematic view of the back surface structure of the semiconductor device after packaging according to the present invention; and FIG. 9 is a schematic front view of the semiconductor device after separation according to the present invention; Figure 10 is a schematic view showing the structure of the back surface of the semiconductor device after separation according to the present invention; and Figure 11 is a separation of the semiconductor device of the present invention. Rear side cross-sectional view.

Specific embodiments of the present invention are described below in conjunction with the drawings.

Referring to Figures 2 to 11, the present invention provides a semiconductor device incorporating a packaged high-end and low-end wafer, and a method of fabricating the same, and Fig. 11 is a side cross-sectional view showing the overall structure of the semiconductor device. The semiconductor device includes a lead frame 100, and a low-end wafer 200 and a high-end wafer 300 respectively connected to the upper and lower sides of the lead frame 100. In the low-end wafer 200 and the high-end wafer 300, the gate and the source are respectively located at the top of the wafer, and the drain is located at the bottom of the wafer.

As shown in FIG. 2, the lead frame 100 includes a carrier base 110 and a plurality of pins disposed around the carrier base 110. The pins are in the same plane as the slide base 110. Inside. The first pin 121, the second pin 122, the third pin 123, and the carrier base 110 are separated from each other and are not electrically connected, and are respectively referred to as a low-end source pin and a low-side gate. The pin and the high-side gate pin, the fourth pin 124 is integrally connected with the carrier base 110 or formed by the carrier base 110, and serves as both a high-end drain pin and a low-end source pin.

Referring to FIG. 3, FIG. 6, and FIG. 11, the back side of the low-end wafer 200 is adhered to the lead frame 100, and the bottom of the low-end wafer 200 is electrically connected to the top surface of the slide base 110. Two metal connecting pieces 230 (for example, copper pieces) are disposed, and two ends of one of the metal connecting pieces 230 are respectively adhered to the top source 211 of the low-end wafer 200 and the first pin 121 of the lead frame 100, and the other metal The two ends of the connecting piece 230 are respectively adhered to the top gate 212 of the low-end wafer 200 and the second pin 122 of the lead frame 100, and the connecting strip, the connecting lead or other conductive connecting body may be used instead of the metal connecting piece. 230, in order to realize the electrical connection between the source 211 and the gate 212 of the low-end wafer 200 and the corresponding pins on the lead frame 100. In a preferred embodiment, the top source 211 of the low-end wafer 200 is electrically connected to the lead frame 100 by a metal tab 230. On a pin 121, the top gate 212 of the low side wafer 200 is electrically connected to the second pin 122 of the lead frame 100 by a connecting lead. When the above-described wafer and lead frame 100, the metal connecting piece 230 and the wafer or the lead are electrically connected, the high temperature alloy 220 can be used as the bonding material.

Referring to FIG. 4, FIG. 5, FIG. 6 and FIG. 11 , the gate and the source of the top of the high-end wafer 300 are formed by ball implantation, and a plurality of source solder balls 311 and gate pads are formed correspondingly. Balls 312, each of which is made of a low temperature alloy. A metal layer 320 having a certain thickness is formed on the back surface of the high-end wafer 300 by evaporating and sputtering Ti, Ni or Ag (titanium, nickel or silver), or a conductive metal patch 320' is pasted on the high-end wafer 300. back. The front side of the high-end wafer 300 is adhered to the back surface of the lead frame 100, and the plurality of source solder balls 311 corresponding to the source of the high-end wafer 300 are electrically connected to the bottom surface of the slide substrate 110, so that the corresponding high-end wafer 300 is gated. The gate electrode 312 of the pole electrode is electrically connected to the third pin 123. As can be seen from the above, the source of the high-end wafer 300 and the drain of the low-end wafer 200 are electrically connected to both sides of the carrier substrate 110, and thus will be connected to the external component by the fourth pin 124 together.

Referring to FIG. 6 to FIG. 11 , the low-end wafer 200 stacked up to the top, the carrier base 110 of the lead frame 100 , and the high-end wafer 300 are all molded in the package 400 by molding. The stereo configuration can reduce the size of the entire semiconductor component. At this time, the first lead 121 to the fourth lead 124, each of which is exposed outside the package 400, is bent so that the end of the lead is at the same level as the back surface of the semiconductor element. In addition, the metal layer 320 or the metal patch 320' on the back side of the high-end wafer 300 not only protects the bottom drain but also exposes the bottom and the outside of the high-end wafer 300 after being exposed to the back surface of the semiconductor component after packaging. When the components are electrically connected, the semiconductor components can be further cooled. In a better In the embodiment, the top source 211 connecting the low-end wafer 200 and the metal tab 230 of the first lead 121 of the lead frame 100 have a top surface exposed outside the package 400 (not shown) to further help the semiconductor device to dissipate heat.

The following describes the method for fabricating the above-mentioned semiconductor components for packaging high-end and low-end wafers, including the following steps:

Step 1. Making a lead frame 100 from a conductive material;

As shown in FIG. 2, corresponding to each semiconductor element, a first lead 121 separated from the slide base 110 and a second lead are disposed on the same plane on the lead frame 100. The pin 122, the third pin 123 and the fourth pin 124 communicating with the slide base 110.

Step 2, on a low-end semiconductor wafer, correspondingly make a plurality of low-end wafers 200;

The gate 212 and the source 211 of each of the low-end wafers 200 are formed on the front surface of the wafer, and the drain of each of the low-end wafers 200 is formed on the back surface of the wafer.

The wafer is diced and separated to form a plurality of the low end wafers 200.

Step 3, on a high-end semiconductor wafer, correspondingly make a plurality of high-end wafers 300;

As shown in FIG. 4, the gate and the source of each high-end wafer 300 are formed on the front surface of the wafer, and the drain of each high-end wafer 300 is formed on the back surface of the wafer.

A plurality of source solder balls 311 and gate solder balls 312 are formed on the gate and the source of the top of the high-end wafer 300 by ball implantation, and the solder balls are respectively made of a low temperature alloy.

The back side of the high-end wafer 300 is evaporatively sputtered with Ti, Ni or Ag (titanium, nickel or silver) to form a metal layer 320 having a certain thickness by a metallization process; or, at the height A conductive metal patch 320' is adhered to the back side of the end wafer 300.

The wafer is diced and separated to form a plurality of the high-end wafers 300.

Step 4, the back side of the low-end wafer 200 is pasted on the front surface of the lead frame 100;

As shown in FIG. 3, the front end of the low-end wafer 200 faces upward, and the bottom of the low-end wafer 200 is electrically connected to the top surface of the carrier base 110, and the source and the gate of the top are respectively connected by metal. The sheet 230 (or a connecting strip or a connecting lead or similar conductive connecting body) is electrically connected to the first pin 121 and the second pin 122 of the lead frame 100.

The high temperature alloy 220 can be used as the bonding material for electrically connecting the low-end wafer 200 and the carrier base 110, the metal connecting piece 230 and the low-end wafer 200, or the metal connecting piece 230 to the lead.

Step 5, the front side of the high-end wafer 300 is adhered to the back surface of the lead frame 100;

As shown in Fig. 5, the lead frame 100 is flipped so that its back side faces upward. The top surface of the high-end wafer 300 faces downward, and the source of the top portion is electrically connected to the bottom surface of the substrate base 110 by a plurality of source solder balls 311; the gate of the top is soldered by the gate. The ball 312 is electrically connected to the third pin 123 of the lead frame 100.

Step 6. The stacked low-end wafer 200, the carrier base 110 of the lead frame 100, and the high-end wafer 300 are molded in the package 400 by molding;

Referring to FIG. 6 to FIG. 8 , the metal layer 320 or the metal patch 320 ′ on the back surface of the high-end wafer 300 is exposed outside the package 400 on the back surface of the packaged semiconductor device to realize the bottom bucking and the outside. Electrical connection of components while helping to dissipate heat from semiconductor components. In a preferred embodiment, the top source 211 connecting the low-end wafer 200 and the metal tab 230 of the first lead 121 of the lead frame 100 have a top surface exposed thereto. The package 400 is external (not shown) to further assist in dissipating heat from the semiconductor component.

Step 7. Separating the respective semiconductor elements on the lead frame 100 by means of Trim/Forming;

As shown in Figs. 9 to 11, the portions in which the plurality of pins are exposed outside the package 400 are cut to separate the respective semiconductor elements. Further, the exposed end portion of the lead is bent at the same level as the back surface of the semiconductor element.

So far, the fabrication of the entire semiconductor component is completed. The steps to be performed may be arbitrarily changed in different orders, for example, the order of steps 1, 2, and 3, and the order of steps 4 and 5 may be arbitrarily changed. In addition, several actions in one step may also be interspersed with several of the other steps. For example, in step 4, the metal connecting piece 230 (or the connecting tape or the connecting lead or the like conductive connecting body) is respectively electrically connected. Sub-steps of being selectively connected to the first pin 121 and the second pin 122 of the lead frame 100 may also be performed after the completion of step 5. Therefore, the sequence of steps cited in the above method does not mean that the sequence of steps cited is strictly adhered to in time, but rather to the convenient classification of different operational tasks in the fabrication of semiconductor components. In summary, in the semiconductor device of the present invention, the low-end wafer and the high-end wafer are respectively located on the upper and lower sides of the lead frame, and the three form a three-dimensional stacked structure; the low-end and high-end wafers are attached side by side compared with the prior art. The structure of the same side of the lead frame, the present invention effectively reduces the size of the entire semiconductor element. In addition, the present invention uses a metal layer or a conductive metal patch covered on the bottom of the high-end wafer as a heat sink, and is exposed outside the back surface of the packaged semiconductor element, thereby effectively improving the heat dissipation performance of the semiconductor element. The invention can further expose a top surface of the low-end wafer and a top surface of the metal connecting piece of the lead frame to the outside of the top surface of the semiconductor element to further help the semiconductor element to dissipate heat.

Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the description Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

110‧‧‧Slide base

122‧‧‧second pin

123‧‧‧ third pin

200‧‧‧ low-end wafer

220‧‧‧High temperature alloy

230‧‧‧Metal connecting piece

300‧‧‧High-end wafer

311‧‧‧Source solder balls

312‧‧‧ gate solder balls

320‧‧‧metal layer

320’‧‧‧Metal patch

Claims (16)

A semiconductor component incorporating a packaged high-end and low-end wafer, comprising: a conductive lead frame provided with a carrier base; and a low-end wafer and a high-end wafer each having a top source and a top gate a pole and a bottom drain, wherein the top source of the high-end wafer is implanted with a plurality of conductive source solder balls, and the top gate is provided with one or a plurality of conductive gate solder balls; wherein the low The back surface of the end wafer is fixedly connected to the front surface of the lead frame, and the bottom electrode of the low end wafer is electrically connected to the top surface of the slide substrate, and the front surface of the high end wafer is fixedly connected to the back surface of the lead frame And the top source of the high-end wafer is electrically connected to the bottom surface of the substrate base by the plurality of source solder balls, and a heat sink is covered on the back surface of the high-side wafer, and the heat sink is splashed by evaporation Forming a metal layer having a certain thickness; wherein the semiconductor component further comprises a package, the low-end wafer to be sequentially stacked, the carrier base of the lead frame, and the high Forming the wafer in the package, and exposing the heat sink on the back surface of the high-end wafer to the outside of the package on the back side of the semiconductor component for heat dissipation, the bottom drain of the high-side wafer being exposed by the heat sink An external component is electrically connected. The semiconductor device according to claim 1, wherein the lead frame further comprises a first pin and a second separated from the substrate base and electrically connected. a pin, a third pin, and a fourth pin electrically connected to the carrier base. The semiconductor device of claim 2, wherein the bottom drain of the low-end wafer and the top source of the high-end wafer are respectively connected to the carrier base. The two sides are electrically connected together with an external component by the fourth pin. The semiconductor device of claim 2, wherein the top gate of the high-end wafer is electrically connected to the third lead by the one or more gate solder balls. foot. The semiconductor component of the packaged high-end and low-end wafers as described in claim 1, wherein the heat sink is a conductive metal patch adhered to the back side of the high-end wafer. The semiconductor device of claim 2, wherein the top source of the low-end wafer is electrically connected to the first pin by a metal connecting piece disposed. The top gate of the low-end wafer is electrically connected to the second pin by another metal connection piece disposed. The semiconductor component of the packaged high-end and low-end chip according to claim 6, wherein the metal connection piece and the low-end chip, the metal connection piece and the first pin and the second pin are respectively A high-temperature alloy is provided between them for adhesive bonding and electrical connection. The semiconductor device according to claim 1, wherein the low-end wafer and the carrier base of the lead frame are disposed such that the two are adhered to each other and electrically connected. A superalloy that is connected. The semiconductor component of the packaged high-end and low-end chip according to the first aspect of the invention, wherein the top source and the top gate of the high-end wafer are respectively made of low-temperature alloy. to make. A method for fabricating a semiconductor device packaged with a high-end and low-end chip, comprising The following steps: Step 1, making a lead frame from a conductive material, and corresponding to each of the semiconductor elements, a carrier base is disposed on the lead frame; Step 2, on the front side of a low-end semiconductor wafer, correspondingly making a plurality of a top source and a top gate of the low-end wafer, on the back side of the low-end semiconductor wafer, corresponding to a bottom buck of the plurality of low-end wafers, the low-end semiconductor wafer is cut and separated to form the a plurality of low-end wafers; step 3, on the front side of a high-end semiconductor wafer, corresponding to the top source and the top gate of the plurality of high-end wafers, corresponding to the plurality of high-end semiconductor wafers on the back side of the high-end semiconductor wafer The bottom drain of the wafer, by the ball implantation on the top source and the top gate of the high-side wafer, correspondingly forming a plurality of conductive source solder balls and one or more gate solder balls, and then The high-end semiconductor wafer is diced and separated to form the plurality of high-end wafers, wherein the high-end wafer is vapor-sputtered on the back side of the high-end wafer to form a certain thickness by a gate metallization process a metal layer, or a conductive metal patch adhered to the back side of the high-end wafer; step 4, the low-end wafer faces up, and the back side of the low-end wafer is pasted on the front surface of the lead frame to make the bottom portion Electrode is electrically connected to the top surface of the substrate base; step 5, flipping the lead frame with the back side facing up, the front side of the high-end wafer facing downward, and bonding the front side of the high-end wafer to the back of the lead frame The top source is electrically connected to the bottom surface of the bottom of the substrate by the plurality of source solder balls, so as to be electrically connected to the bottom of the low-end wafer; step 6, borrow Forming the low-end wafer, the carrier base of the lead frame, and the high-end wafer, which are sequentially stacked, in a package, and exposing the metal layer or the metal patch on the back surface of the high-end wafer to The back of the semiconductor component In addition to the package, an electrical connection between the bottom drain and an external component is achieved and heat is dissipated; and in step 7, the semiconductor components on the lead frame are separated by shear molding. The method for fabricating a semiconductor device for packaging a high-end and low-end wafer according to claim 10, wherein in step 1, corresponding to each of the semiconductor components, the substrate is further disposed on the lead frame. a first pin, a second pin, a third pin and a fourth pin electrically connected to the carrier base are separated and electrically connected. The method for fabricating a semiconductor device for packaging a high-end and a low-end chip according to claim 11, wherein in step 4, the top source and the top gate of the low-end wafer are respectively connected by a metal The chip is electrically connected to the first pin and the second pin of the lead frame. The method for fabricating a semiconductor device for packaging high-end and low-end chips according to claim 11, wherein in step 5, the top gate of the high-end wafer is electrically connected to the gate electrode by the one or more gate electrodes. The connection is made on the third pin of the lead frame. The method for fabricating a semiconductor device for packaging high-end and low-end chips according to claim 11, wherein after the step 5, the bottom drain of the low-end wafer is respectively connected to the top source of the high-end wafer. The two sides of the substrate base are electrically connected to the external component by the fourth pin. The method for fabricating a semiconductor device for packaging a high-end and low-end wafer according to claim 12, wherein in the step 4, a high-temperature alloy is used as the metal between the low-end wafer and the substrate base. Between the connecting piece and the low-end wafer, the metal connecting piece is electrically connected to the first pin and the second pin. The method for fabricating a semiconductor device for packaging a high-end and low-end chip according to claim 10, wherein in the step 3, the top source of the high-end wafer and the plurality of solder balls corresponding to the top gate are implanted , are made of low temperature alloys, respectively.