TWI462227B - Memory structure - Google Patents

Description

Memory structure

Embodiments of the present invention are directed to a semiconductor component, and more particularly to a memory structure that avoids wordline opening or linewidth necking.

Memory is a semiconductor component used to store data or data. It is widely used in computers or electronic devices. As microprocessor functions become more powerful, the demand for various types of memory increases. Different memory structure designs depending on different memory type requirements, such as vertical channel memory (VC memory) with vertical channel structure design, floating gate with oxide recess structure A floating memory (FG memory) and a three-dimensional memory (3D memory) having a thin film stacked structure.

In a general memory layout, a word line is an active region, that is, a component-intensive region in which a plurality of memory cells are disposed, or a memory cell region. In general, in the front-end process of a semiconductor device, a conductor layer for forming a word line causes a large step difference at a boundary across a dense region of the element due to the design of the memory structure. This step difference causes a phenomenon of defocusing in the subsequent lithography step of patterning the conductor layer, so that the formed word line is broken or the line width is necked, thereby reducing the memory. Production quality and efficiency of body components. With the accumulation of semiconductor components, more needs To propose an appropriate solution to this problem.

An embodiment of the present invention provides a memory structure that avoids word line breakage or line width necking and improves the quality of memory components.

An embodiment of the present invention provides a memory structure that is divided into a memory cell region and a non-memory cell region, and includes a plurality of memory cells and a conductor material. A plurality of memory cells are disposed in the memory cell region, and have a plurality of first recesses in the memory cells. The conductor material spans the memory cell area and the non-memory cell area, and covers the memory cell and penetrates into the plurality of first recesses.

In an embodiment of the invention, the conductor material located in the memory cell region and the non-memory cell region has a substantially flat upper surface.

In an embodiment of the invention, in the memory cell region and the non-memory cell region, a ratio of a height change amount to a line width of the substantially flat upper surface of the conductor material is 0 to 1.0.

In an embodiment of the invention, the non-memory cell area is a semi-empty area.

In an embodiment of the invention, the non-memory cell region is a virtual memory cell region, and the memory structure further includes a plurality of virtual structures disposed in the virtual memory cell region, and the adjacent two virtual structures have a The two recesses have a bottom portion that is substantially at the same level as the bottom of the first recess and has substantially the same depth.

Another embodiment of the present invention provides a memory structure that is divided into Memory cells and non-memory cells, and include multiple memory cells and word lines. A plurality of memory cells are disposed in the memory cell region and have a non-coplanar dielectric structure in the memory cells. The word line spans the memory cell area and the non-memory cell area, and covers the memory cell, and the word line located in the memory cell area and the non-memory cell area has a substantially flat upper surface and a non-coplanar bottom surface, The planar bottom surface is connected to a non-coplanar dielectric structure.

In an embodiment of the invention, in the memory cell area and the non-memory cell area, the ratio of the height change amount of the substantially flat upper surface of the word line to the line width is 0 to 0.5.

In an embodiment of the invention, in the memory cell area and the non-memory cell area, the height of the substantially flat upper surface of the word line varies from 0 Å to 300 Å.

In an embodiment of the invention, the non-memory cell area is a semi-empty area.

In an embodiment of the invention, the non-memory cell region is a virtual memory cell region, and the memory structure further includes a plurality of virtual structures disposed in the virtual memory cell region, and the upper surface of the virtual structures is non-common The highest plane of the planar dielectric structure is substantially at the same level.

In summary, in the memory structure of the embodiment of the present invention, the word lines in the memory cell area and the non-memory cell area have substantially flat upper surfaces, and the word line lines can be prevented from being broken or line width. The problem of necking. In addition, the memory structure in the embodiment of the present invention can be applied to different types of memory elements to improve the production quality and efficiency of the semiconductor memory element.

In order to make the above features and advantages of the embodiments of the present invention more obvious Understand, the following is a detailed description with reference to the drawings.

Embodiments of the invention are described more fully hereinafter with reference to the accompanying drawings. However, the invention may be practiced in many different forms and is not limited to the embodiments described herein. The directional terms used in the following embodiments, such as "upper" and the like, are merely referring to the orientation of the additional drawings, and thus the directional terminology used is for the purpose of illustration and not limitation. In addition, the dimensions and relative dimensions of the various layers may be exaggerated in the drawings for clarity.

1A-1D are cross-sectional views showing a manufacturing process of a memory structure in accordance with an embodiment of the present invention. The memory structure in this embodiment is described by taking a vertical channel memory as an example.

First, referring to FIG. 1A, a substrate 110 is provided. The substrate 110 can be divided into a non-memory cell region 100a and a memory cell region 100b. In this embodiment, the non-memory cell region 100a is, for example, a semi-empty region and does not have any memory cells in the semi-empty region. Further, the substrate 110 in the memory cell region 100b has been formed with a plurality of protrusions 124. In the memory cell region 100b, the substrate 110 may further have a plurality of first doping regions 126a and a plurality of second doping regions 126b, wherein the first doping region 126a is disposed in the upper portion of the protruding portion 124, and the second doping The miscellaneous region 126b is disposed in the substrate 110 between adjacent protrusions 124.

A dielectric structure 120 is then formed on the substrate 110. The dielectric structure 120 is formed by, for example, chemical vapor deposition, in which a bottom dielectric layer 120c, a charge trap layer 120b, and a top dielectric layer 120a are sequentially formed on the substrate 110. The materials of the bottom dielectric layer 120c and the top dielectric layer 120a are, for example, tantalum oxide, respectively, and the material of the charge trap layer 120b is, for example, tantalum nitride.

Furthermore, since the dielectric structure 120 is formed on the substrate 110 having the plurality of protrusions 124, the dielectric structure 120 in the memory cell region 100b has a plurality of recesses 122 to form a non-coplanar structure. The non-coplanar dielectric structure 120 has, for example, a plurality of first surfaces 160a and a plurality of second surfaces 160b, and the first surface 160a is higher in the vertical direction than the second surface 160b. Here, the first surface 160a is the highest plane of the dielectric structure 120.

Then, referring to FIG. 1B, a conductor layer 130 is formed on the dielectric structure 120. The material of the conductor layer 130 is, for example, doped polysilicon. The method of forming the conductor layer 130 is, for example, a chemical vapor deposition method.

At this time, since the first surface 160a of the non-coplanar dielectric structure 120 in the memory cell region 100b is higher in the vertical direction than the upper surface 140 of the non-memory cell region 100a dielectric structure 120, it is deposited to form a word. After the conductor layer 130 of the line, the upper surface 130a of the conductor layer 130 is different in height from the non-memory cell region 100a and the memory cell region 100b, resulting in a step H as shown in FIG. 1B.

Next, referring to FIG. 1C, the conductor layer 130 is subjected to chemical mechanical polishing so that the upper surface 130a of the conductor layer 130 becomes flatter.

At this time, since the step difference H is eliminated, the phenomenon of defocusing of light in the subsequent lithography step of patterning the conductor layer 130 can be avoided, thereby preventing the word line from being broken or Line width necking problem.

Then, a deuterated metal layer can be selectively formed on the conductor layer 130. 132, to reduce the resistance of the subsequently formed word line. The material of the deuterated metal layer 132 is, for example, tungsten telluride. The method of forming the deuterated metal layer 132 is, for example, a metal deuteration process.

Thereafter, referring to FIG. 1D, the patterned metallization layer 132 and the conductor layer 130 are patterned to form a patterned deuterated metal layer 132a and a word line 134, respectively. The patterning process performed on the deuterated metal layer 132 and the conductor layer 130 is, for example, a lithography process and an etching process in sequence. However, in this embodiment, although the word line 134 is formed by the above method, the method of forming the word line 134 is not limited thereto.

Based on the above, the upper surface 130a of the conductor layer 130 can be made flatter by applying chemical mechanical polishing to the conductor layer 130 in the process. Therefore, light out of focus is prevented from occurring in the lithography step of patterning the conductor layer 130, so that the formed word line 134 can be prevented from being broken or the line width being necked.

1E is a top view of a memory structure in accordance with an embodiment of the present invention illustrated in FIG. 1D. Hereinafter, the memory structure proposed in the above embodiment will be described with reference to FIGS. 1D and 1E.

Referring first to FIG. 1D, the memory structure can be divided into a memory cell region 100b and a non-memory cell region 100a. In this embodiment, the non-memory cell region 100a is, for example, a semi-empty region, and does not have any memory cells in the semi-empty region. A plurality of memory cells 150 are disposed in the memory cell region 100b, and have a non-coplanar dielectric structure 120 in the memory cells 150. The non-coplanar dielectric structure 120 has, for example, a plurality of first surfaces 160a and a plurality of second surfaces 160b, and the first surface 160a is higher in the vertical direction than the second surface 160b. In addition, The memory structure further includes a word line 134 that spans the memory cell region 100b and the non-memory cell region 100a and covers the plurality of memory cells 150 as described above and penetrates the recess portion 122. In addition, the word line 134 located in the memory cell region 100b and the non-memory cell region 100a has a substantially flat upper surface 134a and a non-coplanar bottom surface 134d, and the bottom surface 134d is connected to a non-coplanar dielectric structure. 120. The materials, the arrangement, the forming method, and the functions of the components in the memory structure have been described in detail in the above embodiments, and thus will not be described again.

Further, the degree of flatness (flatness) of the upper surface 134a of the word line 134 can be defined by the ratio of the height change amount Δh1 on the upper surface 134a of the word line 134 to the line width of the word line 134, and this ratio is defined. For example, it is 0~1.0, but it can be 0~0.5. Further, the height change amount Δh1 on the upper surface 134a is, for example, in the range of 0 Å to 300 Å.

Referring also to FIG. 1E, the word line 134 includes a word line header 134c and a word line body 134b, and the line width of the word line header 134c is greater than the line width of the word line body 134b. Additionally, the patterned deuterated metal layer 132a can be selectively overlying the word line 134 to reduce the resistance of the word line 134. The material of the deuterated metal layer 132a is, for example, tungsten telluride.

The word line header 134c is located in the non-memory cell area 100a, and the word line line body 134b is located in the non-memory cell area 100a and the memory cell area 100b (the word line body 134b may also span to the non-memory cell area 100a). ). The word line header 134c can be used to connect to an external power source (not shown), and the external power source can apply a voltage to the word line body 134b through the word line head 134c to operate the respective memory cells 150.

Based on the above, the word line 134 in the memory structure has a substantially flat upper surface and is less prone to breakage or neckline necking.

2A-2B are cross-sectional views showing a manufacturing process of a memory structure in accordance with another embodiment of the present invention. The memory structure in this embodiment is described by taking a vertical channel memory as an example.

First, referring to FIG. 2A, a substrate 210 is provided. The substrate 210 can be divided into a non-memory cell region 200a and a memory cell region 200b. In this embodiment, the non-memory cell area 100a is, for example, a virtual memory cell area, and the virtual memory cell area is an area for forming a virtual structure without an operable memory cell.

A plurality of protrusions 224 have been formed on the base 210 of the non-memory cell area 200a and the memory cell area 200b. The substrate 210 may further have a plurality of first doping regions 226a and a plurality of second doping regions 226b, wherein the first doping regions 226a are disposed in the upper portion of the protrusions 224, and the second doping regions 226b are disposed adjacent to each other. In the base 210 between the protrusions 224.

A dielectric structure 220 is then formed on the substrate 210. At this time, a plurality of virtual structures 290 are formed in the non-memory cell area 200a. The method of forming the dielectric structure 220 is, for example, forming a bottom dielectric layer 220c, a charge trap layer 220b, and a top dielectric layer 220a on the substrate 210 by chemical vapor deposition. The materials of the bottom dielectric layer 220c and the top dielectric layer 220a are, for example, tantalum oxide, respectively, and the material of the charge trap layer 220b is, for example, tantalum nitride.

In addition, since the dielectric structure 220 is formed on the substrate 210 having the protrusions 224, the dielectric structure 220 is made non-coplanar in either the non-memory cell area 200a or the memory cell area 200b. The dielectric structure 220 in the memory cell region 200b has, for example, a plurality of first surfaces 260a and the plurality of second surfaces 260b, and the first surface 260a is higher than the second surface 260b in the vertical direction. Here, the first surface 260a is the highest plane of the dielectric structure 220. Furthermore, the upper surface 290a of the dummy structure 290 in the non-memory cell region 200a is substantially at the same level as the first surface 260a. And the distance d1 between two adjacent virtual structures 290 is substantially equal to the distance d2 between the adjacent two first surfaces 260a.

Further, a plurality of first recesses 228 are provided in the memory cell region 200b, and a plurality of second recesses 222 are provided between the dummy structures 290 of the non-memory cell regions 200a. The bottom of the first recess 228 is substantially at the same level as the bottom of the second recess 222 and has substantially the same depth. That is, the depth H1 of each of the first recesses 228 is substantially equal to the depth H2 of each of the second recesses 222. Further, the distance d3 of the adjacent two second recesses 222 is substantially equal to the distance d4 of the adjacent two first recesses 228.

That is, the combined structure of the dummy structure 290 and the second recess 222 in the non-memory cell region 200a has substantially the same contour as the dielectric structure 220 in the memory cell region 200b.

Next, a conductor layer 230 is formed on the dielectric structure 220. The material of the conductor layer 130 is, for example, doped polysilicon. The method of forming the conductor layer 230 is, for example, a chemical vapor deposition method.

Since the combined structure of the dummy structure 290 and the second recess 222 in the non-memory cell region 200a has substantially the same contour as the dielectric structure 220 in the memory cell region 200b, after depositing the conductor layer 230, the conductor layer 230 The upper surface 230a coincides with the height in the non-memory cell region 200a and the memory cell region 200b without the aforementioned step difference.

At this time, since the non-memory cell region 200a and the upper surface 230a of the conductor layer 230 in the memory cell region 200b are flat, it is possible to avoid the occurrence of optical defocus in the subsequent lithography step of patterning the conductor layer 230. The phenomenon can further prevent the problem that the word line is broken or the line width is necked.

Then, a deuterated metal layer 232 is selectively formed on the conductor layer 230 to reduce the resistance of the subsequently formed word line. The material of the deuterated metal layer 232 is, for example, tungsten telluride. The method of forming the deuterated metal layer 232 is, for example, a metal deuteration process.

Thereafter, referring to FIG. 2B, the deuterated metal layer 232 and the conductor layer 230 are patterned to form a patterned deuterated metal layer 232a and a word line 234, respectively. The patterning process performed on the deuterated metal layer 232 and the conductor layer 230 is, for example, a lithography process and an etching process in sequence. In this embodiment, although the word line 234 is formed by the above method, the method of forming the word line 234 is not limited thereto.

Based on the above, in this embodiment, the combined structure of the dummy structure 290 and the second recess 222 in the non-memory cell region 200a has substantially the same contour as the dielectric structure 220 in the memory cell region 200b, so that After the conductor layer 230 is deposited, the upper surface 230a of the conductor layer 230 is flat, which avoids the phenomenon of light out of focus in the lithography step of patterning the conductor layer 230, thereby preventing the formation of the word line 234 formed. Broken wire or neckline necking problem.

It is to be noted that, in this embodiment, although the dummy structure 290 is formed together in the process of forming the memory cell 250, it has a structure similar to that of the memory cell 250. However, by the design of the layout, the virtual structure can be made 290 lost the ability to act as a memory cell. For example, when the bit lines connected to the first doped region 226a and the second doped region 226b in the dummy structure 290 are not externally connected to an external voltage, the dummy structure 290 can be caused to lose its ability as a memory cell. In addition, in this embodiment, although the virtual structure 290 has a structure similar to that of the memory cell 250, the structure of the virtual structure 290 of the present invention is not limited thereto, as long as the combined structure of the virtual structure 290 and the second recess 222 and the memory cell Dielectric structure 220 in region 200b has substantially the same profile, i.e., is within the scope of the present invention. In addition, in other embodiments, the virtual structure 290 does not have to be formed together with the memory cell 250, and the virtual structure 290 can also be formed separately by other processes.

2C is a top view of the memory structure in accordance with an embodiment of the present invention illustrated in FIG. 2B. Hereinafter, the memory structure proposed in the above embodiment will be described with reference to FIGS. 2B and 2C.

Referring first to FIG. 2B, the memory structure of the present embodiment is divided into a memory cell region 200b and a non-memory cell region 200a. In this embodiment, the non-memory cell area 200a is a virtual memory cell area in which a plurality of virtual structures 290 are disposed. A plurality of memory cells 250 are disposed in the memory cell region 200b. This memory structure includes a dielectric structure 220 disposed on a substrate 210. The dielectric structure 220 in the memory cell region 200b has, for example, a plurality of first surfaces 260a and a plurality of second surfaces 260b, and the first surface 260a is higher than the second surface 260b in the vertical direction. Here, the first surface 260a is the highest plane of the dielectric structure 220.

Furthermore, the upper surface 290a of the dummy structure 290 in the non-memory cell region 200a is substantially at the same level as the first surface 260a. And the distance d1 between two adjacent virtual structures 290 is substantially equal to two adjacent The distance d2 between the first surfaces 260a.

Further, a plurality of first recesses 228 are provided in the memory cell region 200b, and a plurality of second recesses 222 are provided between the dummy structures 290 of the non-memory cell regions 200a. The bottom of the first recess 228 is substantially at the same level as the bottom of the second recess 222 and has substantially the same depth. That is, the depth H1 of each of the first recesses 228 is substantially equal to the depth H2 of each of the second recesses 222. Further, the distance d3 of the adjacent two second recesses 222 is substantially equal to the distance d4 of the adjacent two first recesses 228.

That is, the combined structure of the plurality of dummy structures 290 and the second recesses 222 in the non-memory cell region 200a has substantially the same contour as the dielectric structure 220 in the memory cell region 200b.

In addition, the memory structure further includes a word line 234 that spans the memory cell region 200b and the non-memory cell region 200a and covers the plurality of memory cells 250, and the word line 234 can penetrate the first recess portion 228. Moreover, the word line 234 in the memory cell region 200b and the non-memory cell region 200a has a substantially flat upper surface 234a and a non-coplanar bottom surface 234d, and the bottom surface 234d connects the non-coplanar dielectric structure 220. .

The degree of flatness (flatness) of the upper surface 234a of the word line 234 can be defined by the ratio of the height variation Δh2 on the upper surface 234a of the word line 234 to the line width of the word line 234, which is preferable. It is 0~1.0, more preferably 0~0.5. Further, the height change amount Δh2 on the upper surface 234a is, for example, in the range of 0 Å to 300 Å.

Referring to FIG. 2C, the memory structure of this embodiment includes a word line 234 composed of a word line header 234c and a word line body 234b. The deuterated metal layer 232a is selectively covered thereon. The deuterated metal layer 232a is, for example, tungsten telluride.

The word line header 234c is located in the non-memory cell area 200a, and the word line line body 234b is located in the non-memory cell area 200a and the memory cell area 200b, and the line width of the word line head 234c is larger than the word line line body. Line width of 234b. The word line header 234c can be used to connect to an external power source (not shown), and the external power source can apply a voltage to the word line body 234b through the word line head 234c to operate the respective memory cells 250.

Furthermore, since the word line header 234c is disposed above the virtual structure 290, the structure in the virtual structure 290 of FIG. 2B cannot be a memory cell having a full function. Therefore, in this embodiment, the non-memory cell area 200a is a virtual memory cell area.

Based on the above, the word line 234 in the memory structure has a substantially flat upper surface and is less prone to breakage or neckline necking.

3 is a cross-sectional view showing a memory structure in accordance with another embodiment of the present invention.

Referring to FIG. 3, the memory structure in this embodiment is a floating gate memory. The substrate 310 of the memory structure of this embodiment can also be divided into a memory cell region 300b and a non-memory cell region 300a.

The memory structure includes a plurality of memory cells 312 disposed in the memory cell region 300b, and having a non-coplanar dielectric structure 350 in the memory cells 312. The memory structure further includes a word line 360 that spans the memory cell region 300b and the non-memory cell region 300a and covers the plurality of memory cells 312 described above. In addition, word lines in the memory cell region 300b and the non-memory cell region 300a 360 has a substantially flat upper surface 360a and a non-coplanar bottom surface 360d, and bottom surface 360d connects the non-coplanar dielectric structure 350. The memory structure may further include an isolation structure 320, a tunneling dielectric layer 330, a floating gate 340, and optionally a deuterated metal layer 370.

Moreover, this memory structure can optionally include a plurality of virtual structures 380. Specifically, when the non-memory cell 300a is a virtual memory cell region, there are a plurality of dummy structures 380 in the non-memory cell region 300a, and the upper surface 380a of the dummy structures 380 and the highest plane 350d of the dielectric structure 350 Substantially at the same level; and when the non-memory cell 300a is a half-empty area, there is no virtual structure 380.

In this embodiment, the dielectric structure 350 can be laminated by a plurality of layers. The dielectric structure 350 includes, for example, a bottom dielectric layer 350c, a charge trapping layer 350b, and a top dielectric layer 350a. However, the structure of the dielectric structure 350 is not limited thereto, and the dielectric structure 350 may actually be a single layer structure.

In addition, in the floating gate memory proposed in the embodiment, the technical content, features and effects of the word line for fabricating the substantially flat upper surface have been described in detail in the above embodiments. This will not be repeated here.

4 is a cross-sectional view showing a memory structure in accordance with still another embodiment of the present invention. The memory structure in this embodiment is a three-dimensional memory, and its structure can also be divided into a memory cell region 400b and a non-memory cell region 400a.

The memory structure includes a plurality of memory cells 412 disposed in memory cell region 400b, with non-coplanar dielectric structures 430 in such memory cells 412. The memory structure further includes a word line 460 that spans the memory cell region The 400b and non-memory cells 400a cover a plurality of memory cells 412 as described above.

In addition, word line 460 located in memory cell region 400b and non-memory cell region 400a has a substantially flat upper surface 460a. The memory structure can also include a substrate 410, a plurality of insulating layers 420, a plurality of conductor layers 440, a dielectric structure 430, and a selectively deposited deuterated metal layer 470.

Moreover, this memory structure can optionally include a plurality of virtual structures 480. Specifically, when the non-memory cell area 400a is a virtual memory cell area, there are a plurality of virtual structures 480 in the non-memory cell area 400a, and a plurality of concave parts 422 are present between the virtual structures 480, and the virtual structures are The combined structure of 480 and recess 422 has substantially the same contour as dielectric layer 430 in memory cell region 400b; and when non-memory cell region 400a is used as a half open region, there is no virtual structure 480.

Moreover, in the present embodiment, the dielectric structure 430 may be laminated by a plurality of layers, for example, including a bottom dielectric layer 430c, a charge trapping layer 430b, and a top dielectric layer 430a.

In addition, in the three-dimensional memory proposed in the embodiment, the technical content, features and effects of the word line for fabricating the substantially flat upper surface have been described in detail in the above embodiments, so Let me repeat.

In summary, in the memory structure of the embodiment of the present invention, the word line has a substantially flat upper surface in the memory cell area and the non-memory cell area, and the problem of disconnection or line width necking is less likely to occur. In addition, the memory structure of the present invention can be applied to different types of memory elements, and can improve the production quality and efficiency of various memory elements.

Although the invention has been disclosed above by way of example, it is not intended to be limiting The scope of the present invention is defined by the scope of the appended claims, and the scope of the invention is defined by the scope of the appended claims. Prevail.

100a, 200a, 300a, 400a‧‧‧ non-memory cells

100b, 200b, 300b, 400b‧‧‧ memory cells

110, 210, 310, 410‧‧‧ base

120, 220, 350, 430‧‧‧ dielectric structure

120a, 220a, 430a‧‧‧ top dielectric layer

120b, 220b, 430b‧‧‧ charge trapping layer

120c, 220c, 430c‧‧‧ bottom dielectric layer

122, 222, 422‧‧ ‧ recess

124, 224‧‧ ‧ protruding parts

126a, 226a‧‧‧ first doped area

126b, 226b‧‧‧second doped area

130a, 134a, 140, 230a, 234a, 360a, 380a, 460a‧‧‧ upper surface

132, 132a, 232, 232a, 370, 470‧‧‧ deuterated metal layer

134, 234, 360, 460‧‧ ‧ character lines

134b, 234b‧‧‧ character line body

134c, 234c‧‧‧ character line head

134d, 234d, 360d‧‧‧ bottom surface

150, 250, 312, 412‧‧‧ memory cells

290‧‧‧Area

160a, 160b, 222b, 260a, 260b, 270a, 270b‧‧‧ surface

D1, d2, d3, d4‧‧‧ distance

H‧‧‧ step

H1, H2‧‧‧ height

△h1, △h2‧‧‧ height change

380, 480‧‧‧ virtual structure

320‧‧‧Isolation structure

330‧‧‧Tunnel dielectric layer

340‧‧‧The gate area

350a, 350b, 350c‧‧‧ dielectric layer

350d‧‧‧highest plane

420‧‧‧Insulation

440‧‧‧ conductor layer

1A-1D are cross-sectional views showing a manufacturing process of a memory structure in accordance with an embodiment of the present invention.

1E is a top view of a memory structure in accordance with an embodiment of the present invention illustrated in FIG. 1D.

2A-2B are cross-sectional views showing a manufacturing process of a memory structure in accordance with an embodiment of the present invention.

2C is a top view of the memory structure in accordance with an embodiment of the present invention illustrated in FIG. 2B.

3 is a cross-sectional view of a memory structure in accordance with another embodiment of the present invention.

4 is a cross-sectional view showing a memory structure according to still another embodiment of the present invention.

100a‧‧‧ non-memory area

100b‧‧‧ memory area

110‧‧‧Base

120‧‧‧Dielectric structure

120a‧‧‧Top dielectric layer

120b‧‧‧ charge trapping layer

120c‧‧‧ bottom dielectric layer

126a‧‧‧First doped area

126b‧‧‧Second doped area

134a‧‧‧ upper surface

132a‧‧‧Deuterated metal layer

134‧‧‧ character line

150‧‧‧ memory cells

△h1‧‧‧ height change

Claims (9)

A memory structure is divided into a memory cell region and a non-memory cell region, and includes: a plurality of memory cells disposed in the memory cell region, and having a plurality of first recesses in the memory cells; and a a conductor material spanning the memory cell region and the non-memory cell region and covering the memory cells and penetrating the first recesses, wherein the conductor material located in the memory cell region and the non-memory cell region has a substantially flat and located The upper surface of substantially the same level. The memory structure according to claim 1, wherein in the memory cell region and the non-memory cell region, a ratio of a height variation of the substantially flat upper surface of the conductor material to a line width is 0~ 1.0. The memory structure of claim 1, wherein the non-memory cell is a half open area. The memory structure of claim 1, wherein the non-memory cell is a virtual memory cell, and the memory structure further comprises a plurality of virtual structures disposed in the virtual memory cell, adjacent to two There is a second recess between the dummy structures, and the bottom of the second recess is substantially at the same level as the bottoms of the first recesses and has substantially the same depth. A memory structure is divided into a memory cell region and a non-memory cell region, and includes: a plurality of memory cells disposed in the memory cell region, and in the memory cells a dielectric structure having a non-coplanar plane; and a word line spanning the memory cell region and the non-memory cell region and covering the memory cells, and the character located in the memory cell region and the non-memory cell region The wire has an upper surface that is substantially flat and at substantially the same level and a non-coplanar bottom surface that joins the non-coplanar dielectric structure. The memory structure of claim 5, wherein in the memory cell region and the non-memory cell region, the height of the upper surface of the word line that is substantially flat and at substantially the same level is changed. The ratio of the amount to the line width is 0~0.5. The memory structure of claim 5, wherein in the memory cell region and the non-memory cell region, the height of the upper surface of the word line that is substantially flat and at substantially the same level is changed. The amount is 0Å~300Å. The memory structure of claim 5, wherein the non-memory cell is a half open area. The memory structure of claim 5, wherein the non-memory cell is a virtual memory cell, and the memory structure further comprises a plurality of virtual structures disposed in the virtual memory cell, the virtual structures The upper surface is substantially at the same level as the highest plane of the non-coplanar dielectric structure.