TWI462189B - Thin film transistor substrate and method of making the same, and display including the thin film transistor substrate - Google Patents

Description

Thin film transistor substrate and manufacturing method thereof, and display having thin film transistor substrate

The present invention relates to a thin film transistor substrate and a method of fabricating the same, and more particularly to a thin film transistor substrate having a short channel and a method of fabricating the same, and a display of a thin film transistor substrate having a short channel.

Referring to FIG. 1 , a conventional liquid crystal display mainly includes a backlight module 11 and a liquid crystal display panel 12 on the backlight module 11 .

In detail, the backlight module 11 is located on the back surface of the liquid crystal display panel 12 and emits light toward the liquid crystal display panel 12. The liquid crystal display panel 12 has a thin film transistor substrate 13 , a color filter substrate 14 , a liquid crystal layer 15 , a second alignment layer 16 , and two polarizing plates 17 interposed between the two substrates 12 and 13 . The thin film transistor substrate 13 includes a substrate layer 131, a plurality of thin film transistors 132, a plurality of circuit traces (not shown), a plurality of storage capacitors 151, and a pixel electrode layer 152. The color filter substrate 14 includes a substrate layer 141, a plurality of black matrixes 142, a plurality of color filters 143 (including three colors of red, green, and blue) and a transparent common electrode layer 144. When the liquid crystal layer 15 is changed in its state by the driving voltage, affecting the amount of delay of the transmitted light, the light will exhibit a gray scale display effect after passing through the polarizing plate 17.

Referring to FIG. 2, the bottom gate thin film transistor 132 of the thin film transistor substrate 13 includes a gate 133, a gate insulating layer 134, a semiconductor layer 135, an ohmic contact layer 136, and a source 137. , a drain 138 and a protective layer 139. The patterned gate 133 is formed on the substrate layer 131, and the gate insulating layer 134 covers the substrate layer 131 and the gate 133. The patterned semiconductor layer 135 is formed on the gate insulating layer 134 with respect to the gate 133, and then a patterned ohmic contact layer 136 is formed thereon. The two boundaries of the ohmic contact layer 136 define one of the lower semiconductor layers 135. The channel, the length of which is related to the conductive properties of the thin film transistor. Generally, the short length of the channel gives good conductivity. The patterned source 137 and the drain 138 are respectively covered on both sides of the semiconductor layer 135, and then covered with a protective layer 139 having a contact hole 140.

At present, the channel length of such a bottom gate thin film transistor 132 is limited by the limitation of yellow light and etching process, and is about several micrometers (um), which is difficult to continue to shrink, so it cannot correspond to a high frequency driven product. How to shorten the channel length is related to the improvement of product technology, and can also effectively reduce costs.

Accordingly, it is an object of the present invention to provide a thin film transistor substrate having a short channel. Another object of the present invention is to provide a method of fabricating a thin film transistor substrate having short vias. Another object of the present invention is to provide a display having a thin channel plasma substrate.

The thin film transistor substrate of the present invention comprises a substrate layer, a gate on the substrate layer, a gate insulating layer on the gate, a semiconductor layer on the gate insulating layer, and an electrode layer The semiconductor layer is disposed on the gate insulating layer and includes a first flat portion, a second flat portion, and a slope portion connecting the first flat portion and the second flat portion. The electrode layer includes a drain and a source, the drain is located on the first flat portion, and the source is located above the second flat portion.

In addition, the method for fabricating the thin film transistor substrate of the present invention comprises a step (a), a step (b), a step (c), and a step (d).

In the step (a), a gate is formed on a substrate layer.

The step (b) sequentially forming a gate insulating layer, a semiconductor layer and an electrode preparation layer on the gate and the substrate layer, wherein the semiconductor layer has a first flat portion and a second flat portion, and A slope connecting the first flat portion and the second flat portion.

In the step (c), a patterned photoresist layer is formed on the electrode preparation layer, the photoresist layer includes a first photoresist layer, a second photoresist layer and a third photoresist layer, wherein the second layer The photoresist layer is disposed opposite to the slope portion, and the thickness of the second photoresist layer is less than the thickness of the first photoresist layer and the thickness of the third photoresist layer, and the second photoresist layer is removed.

This step (d) removes the electrode preparation layer from the second photoresist layer until the semiconductor layer is exposed.

The step (e) removes the first photoresist layer and the third photoresist layer.

Furthermore, the display of the present invention has a thin film transistor substrate, comprising a circuit unit, a thin film transistor substrate, and a display unit.

The thin film transistor substrate is electrically connected to the circuit unit for driving. The thin film transistor substrate includes a substrate layer, a gate on the substrate layer, a gate insulating layer on the gate, and the gate. a semiconductor layer on the insulating layer, and an electrode layer on the semiconductor layer, wherein the semiconductor layer includes a first flat portion, a second flat portion, and a first flat portion and the second flat portion In the slope portion of the portion, the electrode layer includes a drain and a source, wherein the drain is located above the first flat portion, and the source is located above the second flat portion. The display unit is disposed on the thin film transistor substrate to controllably generate a predetermined image.

The effect of the invention is that the thickness of the second photoresist layer having a gradient of the photoresist layer is smaller than the thickness of the first photoresist layer and the third photoresist layer, and then etching is performed to make the slope of the semiconductor layer as a channel The length is significantly shortened to the nanometer scale, thereby improving the driving characteristics of the thin film transistor, while improving the charge and discharge and switching effects.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention.

Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.

Referring to FIG. 3, a first preferred embodiment of a thin film transistor substrate 2 of the present invention includes a substrate layer 21, a gate 22, a gate insulating layer 23, a semiconductor layer 24, an ohmic contact layer 26, An electrode layer 25, a protective layer 27 and a pixel electrode layer 28.

The gate electrode 22 is disposed on the substrate layer 21; the gate insulating layer 23 is covered by the insulating dielectric material and substantially equal in thickness on the substrate layer 21 and the gate 22; the semiconductor layer 24 is made of a semiconductor material and substantially Covering the surface of the gate insulating layer 23 with a film thickness, and including a first flat portion 241 opposite to the gate 22, a slope portion 242 extending outward from the edge of the first flat portion 241 and decreasing in height, And a second flat portion 243 extending outward from the edge of the slope portion 242, the slope portion 242 is connected to the first flat portion 241 and the second flat portion 243; the electrode layer 25 includes a first portion a drain 251 of one of the flat portion 241 and the second flat portion 243, and a drain 251 and the drain 251 are electrically connected to each other of the first flat portion 241 and the second flat portion 243 Source 252. When a predetermined potential difference between the source 252 and the drain 251 and the source 252 is applied to the gate 22, a current is electrically conducted from the drain 251 through the slope portion 242 of the semiconductor layer 24 to the source 252. .

In detail, the substrate layer 21 is a support body on which other elements are supported. In the first preferred embodiment, the substrate layer 21 may be a glass substrate having a flat surface. The substrate layer 21 may also be a plastic substrate, a thin metal substrate (Metal Foil) or other polymer composite substrate, but is not limited thereto.

The gate 22 is formed on the surface of the substrate layer 21 and has a substantially flat top surface 221 and a side surface 222 extending obliquely from the periphery of the top surface 221 toward the substrate layer 21, the side surface 222 and the substrate layer The surface of 21 is at an angle of not less than 90° ψ ₁ . The material of the gate 22 may be a metal such as Al, Mo, Ti, Cu, Mg, In, Zn, Mn, Ag, Au, or an alloy, oxide or nitride of the above metal, and has a single layer or a plurality of layers. Stack formation (eg Ag, Mo/Al, MoN/Al, Ti/Cu, Mo/Cu, etc.) with a thickness range of 500 ~5000 between.

The gate insulating layer 23 covers the surface of the substrate layer 21 and the gate 22 substantially in equal thickness. The gate insulating layer 23 is a transparent insulating dielectric material, which may be tantalum nitride (SiNx), yttrium oxide (SiOx), aluminum oxide (AlOx) or other organic materials, but is not limited thereto. The thickness of the gate insulating layer 23 ranges from 500 ~5000 The element formed on the surface of the gate insulating layer 23 and the gate 22 have good dielectric properties.

The semiconductor layer 24 covers the surface of the gate insulating layer 23 substantially in film thickness. The semiconductor layer 24 may be amorphous germanium (α-Si), polycrystalline germanium (poly-Si) or transparent amorphous oxide semiconductor (Transparent Amorphous Oxide Semiconductor (TAOS, such as IGZO, IZO, etc.), but not Limited. The semiconductor layer 24 has a film thickness ranging from 500 ~5000 The thickness of the thin film transistor is adjusted according to the design of the thin film transistor. The semiconductor layer 24 includes a first flat portion 241 opposite to the gate 22, a slope portion 242 extending outward from an edge of the first flat portion 241, and a second extending from the edge of the slope portion 242. Two flat portions 243.

Therefore, in more detail, the surface of the first flat portion 241 correspondingly above the gate 22 is parallel to the top surface 221 of the gate 22 and extends in the same direction. The slope portion 242 extends obliquely outward from the opposite sides of the first flat portion 241 and forms a slope along the side surface 222 of the gate 22 . The second flat portion 243 extends outward from the edge of the slope portion 242 and extends parallel to the surface of the substrate 21 and in the same direction. When the substrate 21 is used as a reference surface, the first flat portion 241 is higher than the second flat portion 243. Preferably, the angle ψ ₂ formed by the slope portion 242 and the second flat portion 243 is greater than 90° and less than 150°.

The ohmic contact layer 26 is subjected to ion doping to change the conductive properties of the surface of the semiconductor layer 24. The conductive property of the ohmic contact layer can reduce the contact resistance of the conductor to the semiconductor junction, and the ohmic contact layer 26 can be selectively removed if the contact resistance is suitable for driving. The ohmic contact layer 26 is patterned and has a first ohmic contact layer 261 and at least one second ohmic contact layer 262. Wherein, the first ohmic contact layer 261 is located above the first flat portion 241 of the semiconductor layer 24, and the second ohmic contact layer 262 is located above the second flat portion 243 of the semiconductor layer 24, and the slope portion 242 of the semiconductor layer 24 Part of the ohmless contact layer 26 is covered. The ohmic contact layer 26 has a thickness of 100 ~1000 .

The electrode layer 25 includes a drain 251 and a source 252, and is formed on the patterned ohmic contact layer 26, and the drain 251 and the source 252 are respectively opposite to the first flat of the semiconductor layer 24. The portion 241 or the second flat portion 243 is disposed, that is, the ohmic contact layer 26 is interposed between the electrode layer 25 and the semiconductor layer 24. In the first preferred embodiment, the drain 251 is opposite to the first flat portion 241 and the first ohmic contact layer 261, and the source 252 is opposite to the second flat portion 243 and the second portion. The case of the ohmic contact layer 262 will be described. The drain 251 and the source 252 can be swapped for their position to correspond to the semiconductor layer 24.

The material of the drain 251 and the source 252 may be a metal such as Al, Mo, Ti, Cu, Mg, In, Zn, Mn, Ag, Au, or an alloy, oxide or nitride of the above metal, Single or multi-layer structures are stacked (eg, Ag, Mo/Al, MoN/Al, Ti/Cu, Mo/Cu, etc.) with a thickness ranging from 500 ~5000 between.

The protective layer 27 covers the surface of the electrode layer 25, the ohmic contact layer 26 and the gate insulating layer 23 substantially in equal thickness, and has at least one contact hole 271 on the drain 251. The contact hole 271 is an electrode. For interconnection. The contact hole can also be located at the source 252, as desired for the end view. The protective layer may be, but is not limited to, tantalum nitride (SiNx), yttrium oxide (SiOx), aluminum oxide (AlOx) or other organic materials. The protective layer 27 has a thickness in the range of 500 ~5000 .

After being patterned, the pixel electrode layer 28 partially covers the surface of the protective layer 27 as a pixel display region, and is partially filled in the contact hole 271 to be electrically connected to the electrode layer 25. The pixel electrode layer 28 may be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode layer 28 has a thickness of 500 ~5000 .

The gate 22, the gate insulating layer 23, the semiconductor layer 24, the ohmic contact layer 26, the drain 251, and the source 252 function as a Thin Film Transistor (TFT). Wherein, the gate insulating layer 23 serves as a dielectric layer, and the slope portion 242 of the semiconductor layer 24 can form a channel. The length of the channel is defined by two adjacent ohmic contact layer boundaries, and the source can also be roughly used. The boundary between the pole 252 and the drain 251 is defined.

If the present invention is applied to a display, when a gate driving signal is applied to the gate 22 via a gate line (not shown) to turn on a predetermined voltage, a channel located in the slope portion 242 of the semiconductor layer 24 is formed, and the thin film transistor is formed. In the on state, the pixel data signal may be sequentially passed through the data line (not shown), the source 252, the second ohmic contact layer 262, the channel of the slope portion 242 of the semiconductor layer 24, and the first ohmic contact. The layer 261 is transferred to the drain 251, and the pixel electrode layer 28 is applied with a predetermined gray scale voltage via the contact hole 271 to change the liquid crystal state of the pixel unit. Conversely, when the gate 22 is applied to turn off the predetermined voltage, the channel of the slope portion 242 of the semiconductor layer 24 is not formed, and the thin film transistor is in a closed state, so that the source 252 and the drain 251 are not electrically connected. Turned on, the pixel data signal cannot be sent to the pixel unit. In the preferred embodiment, an n-type transistor is taken as an example, so that the voltage for forming the channel by the ramp portion 242 is a positive value; and if the p-type transistor is used, the gate 22 is for the source electrode 252. The predetermined voltage between them is a negative value, and this is also familiar to those skilled in the art, and will not be further described herein.

The present invention provides a horizontal channel type thin film transistor which is different from the conventional "channel correspondingly above the gate, and the drain 251 and the source 252 are symmetrically located on both sides of the channel". The drain 251 of the present invention is located above the gate 22, and the source 252 is correspondingly located on the side of the gate 22, and the slope portion 242 of the semiconductor layer 24 is a channel, and the gate 22 and the substrate can be used according to the gate 22 The height difference between the layers 21 and the thickness of the gate insulating layer 23 and the semiconductor layer 24 determine the length of the channel. Since the length L _{1 of} the slope portion 242 is much smaller than the length L _{2 of} the gate 22 (about 1/10 to 1/20 of the horizontal channel type, between 0.05 μm and 1 μm), the thin film transistor of the present invention The on-current can be much larger than the on-state current of the thin film transistor currently applied to the display, which can be increased by about 5 to 50 times.

It should be noted that the pixel electrode layer 28 and the protective layer 27 may be omitted if the thin film transistor substrate of the present invention is applied to other devices.

The method for fabricating the first preferred embodiment of the present invention will become more apparent from the following description.

Referring to FIG. 4, the manufacturing method of the first preferred embodiment includes a step 31, a step 32, a step 33, a step 34, a step 35, a step 36 and a step 37.

In step 31, a gate having a top surface higher than a surface of the substrate layer is formed on a substrate layer. In the step 32, a gate insulating layer, a semiconductor layer, and an electrode preparation layer are sequentially formed on the gate and the substrate according to the substrate layer and the gate. The step 33 is to apply a photoresist layer to form a first photoresist layer opposite to the gate, a second photoresist layer extending from the edge of the first photoresist layer, and having a decreasing height, and a The second photoresist layer extends to the third photoresist layer of the second flat portion. The second photoresist layer has a thickness smaller than the thickness of the first photoresist layer and the thickness of the third photoresist layer, and the second photoresist layer is removed. Until the electrode preparation layer under the second photoresist layer is exposed, that is, the second photoresist layer is removed, the gate insulating layer under the bare, the semiconductor layer and the electrode preparation layer are exposed, and the light is removed. The gate insulating layer, the semiconductor layer, the ohmic contact preparation layer, and the electrode preparation layer covered by the resist layer. This step 34 is to remove the electrode preparation layer of the bare portion until the underlying semiconductor layer is exposed. This step 35 is to remove the remaining photoresist. The step 36 is to form a protective layer having a contact hole penetrating the electrode preparation layer, and the step 37 is to form a pixel electrode layer covering the surface of the protective layer and filling the contact hole.

The manufacturing method of the first preferred embodiment will be described in more detail below.

Referring to FIG. 5, first, in step 31, the substrate layer 21 is prepared, and a gate preparation layer 51 is formed on the surface of the substrate layer 21. The substrate 21 of the first preferred embodiment is a glass substrate. Then, the gate 22 is defined by a gate mask and a lithography and etching process removing portion of the gate preparation layer 51.

Referring to FIG. 4 and FIG. 6, then, in step 32, the gate insulating layer 23 is formed on the gate 22 and the substrate layer 21. The gate insulating layer 23 is, for example, hafnium oxide. The gate insulating layer 23 is formed along the appearance of the substrate layer 21 and the gate 22, and the gate insulating layer 23 is substantially equal in film thickness.

Next, the semiconductor layer 24 is deposited on the surface of the gate insulating layer 23. The semiconductor layer 24 has a configuration similar to that of the gate insulating layer 23, and has a first flat portion 241, a slope portion 242, and a second portion. The flat portion 243 is connected to the first flat portion 241 and the second flat portion 243. In the fabrication method of the first preferred embodiment, the semiconductor layer 24 is amorphous.

Then, the surface of the semiconductor layer 24 is doped into the n-type carrier in a doped manner, and the depth of the n-type doping is controlled by the type of the carrier at the time of doping, the intensity of the energy, or the temperature, thereby forming an ohmic contact preparation. Layer 52.

Next, an electrode preparation layer 53 having substantially the same film thickness is formed on the surface of the ohmic contact preparation layer 52. It should be noted that the electrode preparation layer 53 may be formed directly on the semiconductor layer 24, and the procedure for forming the ohmic contact preparation layer 52 may be omitted.

Referring to FIG. 4, FIG. 7, and FIG. 8, the step 33 is performed, and a photoresist layer 54 is coated on the surface of the electrode film 53. Since the photoresist layer 54 is viscous and flowable before the hard baking process, When the photoresist layer 54 is applied to the surface of the electrode preparation layer 53, in addition to being attached to the surface of the electrode preparation layer 53, the undulations flow according to the height, thereby forming a first light with respect to the first flat portion 241. a resistive layer 541, a second photoresist layer 542 extending from an edge of the first photoresist layer 541 with respect to the slope portion 242, and a second extending from the edge of the second photoresist layer 542 with respect to the second flat portion 243 Three photoresist layer 543. The film thickness of the second photoresist layer 54 is smaller than the thickness of the first photoresist layer 541 and the thickness of the third photoresist layer 543, since the photoresist has fluidity before the photoresist is cured.

Next, a mask is used in conjunction with the lithography to define a region that will later become the electrode layer 25 and the channel (see FIG. 3), and the photoresist layer 54 is hardened, for example, by hard baking to shape the photoresist layer 54. The electrode preparation layer 53, which is not covered by the photoresist layer 54, the ohmic contact preparation layer 52 and the photoresist layer 54 patterned by the semiconductor layer 24 are removed.

Then, the photoresist layer 54 is subjected to an ashing process, and a portion of the structure of the photoresist layer 54 is removed by high-temperature oxygen combustion, since the thickness of the second photoresist layer 542 is smaller than the first photoresist layer 541. The thickness and the thickness of the third photoresist layer 543, so the second photoresist layer 542 is removed first, and the ashing is stopped when the electrode preparation layer 53 is exposed, leaving the first photoresist that has not been completely removed. Part of the structure of the layer 541 and the third photoresist layer 543.

Referring to FIG. 4, FIG. 7, and FIG. 9, this step 34 is performed to remove a part of the structure of the electrode preparation layer 53. In the manufacturing method of the first preferred embodiment, the bare electrode preparation layer 53 is removed by wet etching until the underlying ohmic contact preparation layer 52 is exposed, and is formed correspondingly to the semiconductor layer 24, respectively. The first flat portion 241 and the drain 251 and the source 252 above the second flat portion 243.

Then, the exposed ohmic contact preparation layer 52 is removed by dry etching, that is, the ohmic contact preparation layer 52 correspondingly located on the slope portion 242 of the semiconductor layer 24 is removed, and is formed without being connected to each other and relative to The first flat portion 241 of the semiconductor layer 24 and the first ohmic contact layer 261 and the second ohmic contact layer 262 of the second flat portion 243. In this step, the semiconductor layer 24 may also be etched due to physical etching by dry etching, and it is necessary to ensure that the first ohmic contact layer 261 and the second ohmic contact layer 262 are electrically connected.

It should be noted that, if the n-type doping process is omitted, since the ohmic contact preparation layer 52 is not formed, the slope portion 242 of the semiconductor layer 24 can be exposed after the exposed electrode preparation layer 53 is removed. A program that can be used with or without dry etching.

Referring to FIG. 3 and FIG. 4, then, step 35 is performed to remove the remaining photoresist layer 54, that is, to remove the remaining first photoresist layer 541 and third photoresist layer 543.

Then, the step 36 is performed to form a protective layer 27 and form a contact hole 271 penetrating the electrode layer 25. Finally, step 37 is performed to form a patterned pixel electrode layer 28, and the pixel electrode layer 28 is filled in the contact hole 271 for electrical connection. The thin film transistor substrate 2 of the first preferred embodiment of the present invention is completed, and the thin film transistor substrate 2 can be used for a general transparent liquid crystal display, a reflective liquid crystal display, a transflective liquid crystal display, and an organic electroluminescence A polar body display, detector or other device having a semiconductor switching element.

The current thin film transistor must pass through a reticle with lithography and etching to form a channel, and the method of making the channel is limited by the limit of the yellow light processing device, and can only be controlled in a few micrometers (um The scale of the film can no longer further reduce the channel to the nanometer scale, which makes the driving ability and electrical performance of the thin film transistor unable to meet the requirements. In contrast, the manufacturing method of the first preferred embodiment of the present invention utilizes the characteristic that the photoresist layer 54 itself can naturally flow, such that the thickness of the second photoresist layer 542 is smaller than the thickness of the first photoresist layer 541 and the third light. The thickness of the resist layer 543 can be completely removed first during the process of ashing the photoresist layer 54, and the electrode preparation layer 53 and the ohmic contact preparation layer 52 of the lower opposite slope portion 242 can be removed by etching first. Therefore, the length of the channel of the present invention is no longer limited by the yellow light device, but the shape of the photoresist layer 54 can be utilized to match the thickness of each layer, so that the channel length of the thin film transistor 61 is greatly reduced to nanometer ( The nm) scale can effectively improve the electrical performance of the thin film transistor.

It should be noted that, if the present invention is applied to other semiconductor devices, the step 36 and the step 37 may be omitted, that is, the pixel electrode layer 28 and the protective layer 27 are omitted and directly connected to the outside, which is also a complete film. A method of making a transistor.

Referring to FIG. 10, a second preferred embodiment of the present invention is similar to the first preferred embodiment, except that the substrate layer 21 of the second preferred embodiment includes a transparent The substrate 211, a patterned light shielding layer 212 extending upward from the transparent substrate 211, and a filler 213 covering the light shielding layer 212 and the surface of the substrate 211. The light shielding layer 212 is disposed corresponding to the gate portion 22 and the slope portion 242 of the semiconductor layer 24, and the width thereof can shield the semiconductor channel formed on the slope portion 242 from being irradiated by light to form aging or leakage, thereby prolonging the service life of the thin film transistor. . The light shielding layer 212 is a black matrix (BM), and the material thereof is, for example, a black photoresist or an opaque substance such as Cr. The filler 213 can approximately planarize the surface of the substrate layer 21 such that the process or characteristics of the subsequent thin film transistor do not cause problems due to unevenness of the surface. The filler 213 is made of a transparent material and may be a general photoresist.

Referring to Figures 4 and 11, the manufacturing method of the second preferred embodiment is similar to the manufacturing method of the first preferred embodiment, except that the step 31 is further Two sub-steps 311, 312 are included.

Referring to FIG. 10, FIG. 11, and FIG. 12, the sub-step 311 is to prepare a transparent substrate 211, and then apply a light-shielding preparation layer 544 on the substrate, and cooperate with the lithography and etching by a mask. a portion of the structure of the light-shielding preparation layer 544 is removed to form the patterned light-shielding layer 212. Then, the transparent filler material 213 is formed on the light-shielding layer 212 and the exposed surface of the substrate and cured for subsequent steps. This can be continued on the substrate layer 21 which is a flat surface. The sub-step 312 is formed on the surface of the substrate layer 21 and correspondingly above the light-shielding layer 212, and the slope portion 242 of the semiconductor layer 24 exposed in the step 34 is correspondingly located above the light-shielding layer 212.

Referring to FIG. 13, if the present invention is specifically used for a liquid crystal display, the application to the transmissive display includes a circuit unit 8, a thin film transistor substrate 2, and a display unit 7. The thin film transistor substrate 2 is electrically connected to the circuit unit 8 to transmit a driving signal. The thin film transistor substrate 2 is as described in the first preferred embodiment and has a plurality of thin film transistors arranged in an array. The display unit 7 is disposed on the thin film transistor substrate 2 and transmits the thin film through the thin film. Crystal control produces a predetermined image.

The display unit 7 includes a color filter substrate 71, a liquid crystal layer 72, two alignment layers 73, two optical films 74, and a backlight film group 75. In more detail, the color filter substrate 71 is disposed opposite to the thin film transistor substrate 2, and has a color filter 711, a black matrix 712, and a common electrode layer 713. A liquid crystal layer 72 is interposed between the thin film transistor substrate 2 and the color filter substrate 71. The alignment layers 73 are respectively located between the liquid crystal layer 72 and the thin film transistor substrate 2 and the color filter substrate 71. The optical films 74 are respectively located on the outer surface of the thin film transistor substrate 2 and the color filter substrate 71. The optical film 74 is, for example, a polarizing plate, a compensation film or a composite film. The backlight module 75 is disposed relative to the thin film transistor substrate 2 , and the thin film transistor substrate 2 is interposed between the color filter substrate 74 and the backlight module 75 .

Referring to FIG. 14, in particular, since the light of the backlight module 75 first passes through the thin film transistor substrate 2, when light passes through the slope portion 242 of the semiconductor layer 24, the channel will be affected to affect the characteristics of the thin film transistor switch. Therefore, if the thin film transistor substrate 2 is as described in the second preferred embodiment above, light from the backlight unit can be blocked from being irradiated to the semiconductor layer 24 to avoid affecting channel characteristics.

It is worth mentioning that, when the thin film transistor substrate of the present invention is applied to an organic light emitting diode display, the display unit is an organic light emitting diode element, and the organic light emitting diode element has one electrode layer generally known. (not shown), and an organic light-emitting layer (not shown) interposed between the electrode layer and the pixel electrode layer of the thin film transistor substrate.

In summary, the thin film transistor of the present invention uses the slope portion 242 of the semiconductor layer 24 as a channel, which is different from the conventional channel in parallel with the top surface of the gate; further, since the light located on the slope portion 242 is utilized The thickness of the resist layer 54 is smaller than the thickness of the photoresist layer 54 in other regions, without being limited by the size limit of the yellow light device, the channel length is greatly shortened, the thin film transistor switching capability is improved, and the update frequency is increased to achieve the object of the present invention.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

2. . . Thin film transistor substrate

twenty one. . . Substrate layer

211. . . Substrate

212. . . Shading layer

213. . . Filler

twenty two. . . Gate

221. . . Top surface

222. . . side

twenty three. . . Gate insulation

twenty four. . . Semiconductor layer

241. . . First flat

242. . . Slope

243. . . Second flat

25. . . Electrode layer

251. . . Bungee

252. . . Source

26. . . Ohmic contact layer

261. . . First ohmic contact layer

262. . . Second ohmic contact layer

27. . . The protective layer

271. . . Contact hole

28. . . Alizarin electrode layer

L ₁ . . . length

L ₂ . . . length

ψ ₁ . . . Angle

ψ ₂ . . . Angle

31. . . step

311. . . Substep

312. . . Substep

32. . . step

33. . . step

34. . . step

35. . . step

36. . . step

37. . . step

51. . . Gate preparation layer

52. . . Ohmic contact preparation layer

53. . . Electrode preparation layer

54. . . Photoresist layer

541. . . First photoresist layer

542. . . Second photoresist layer

543. . . Third photoresist layer

544. . . Shading preparation layer

6. . . Backlight module

7. . . Display unit

71. . . Color filter substrate

711. . . Color filter

712. . . Black matrix

713. . . Common electrode layer

72. . . Liquid crystal layer

73. . . Alignment layer

74. . . Optical diaphragm

75. . . Alignment layer

8. . . Circuit unit

Figure 1 is a cross-sectional view showing a liquid crystal display;

Figure 2 is a schematic cross-sectional view showing a thin film transistor substrate;

Figure 3 is a cross-sectional view showing a first preferred embodiment of the thin film transistor substrate of the present invention;

Figure 4 is a flow chart showing the manufacturing method of the first preferred embodiment;

Figure 5 is a cross-sectional view showing a step 31 of the manufacturing method of the first preferred embodiment;

Figure 6 is a cross-sectional view showing a step 32 of the manufacturing method of the first preferred embodiment;

Figure 7 is a schematic cross-sectional view showing a step 33 of the manufacturing method of the first preferred embodiment;

Figure 8 is a schematic cross-sectional view showing a step 33 of the manufacturing method of the first preferred embodiment;

Figure 9 is a cross-sectional view showing a step 34 of the manufacturing method of the first preferred embodiment;

Figure 10 is a cross-sectional view showing a second preferred embodiment of the thin film transistor of the present invention;

Figure 11 is a flow chart showing a method of fabricating a second preferred embodiment of the thin film transistor of the present invention;

Figure 12 is a cross-sectional view showing the step 31 of the manufacturing method of the second preferred embodiment further including a step 311 and a step 312;

Figure 13 is a cross-sectional view showing a liquid crystal display having the thin film transistor of the first preferred embodiment; and

Figure 14 is a cross-sectional view showing a liquid crystal display having the thin film transistor of the second preferred embodiment.

2. . . Thin film transistor substrate

twenty one. . . Substrate layer

twenty two. . . Gate

221. . . Top surface

222. . . side

twenty three. . . Gate insulation

twenty four. . . Semiconductor layer

241. . . First flat

242. . . Slope

243. . . Second flat

25. . . Electrode layer

251. . . Bungee

252. . . Source

26. . . Ohmic contact layer

261. . . First ohmic contact layer

262. . . Second ohmic contact layer

27. . . The protective layer

271. . . Contact hole

28. . . Alizarin electrode layer

L ₁ . . . length

L ₂ . . . length

ψ ₁ . . . Angle

ψ ₂ . . . Angle

Claims (19)

A thin film transistor substrate comprising: a substrate layer; a gate on the substrate layer; a gate insulating layer on the gate; a semiconductor layer on the gate insulating layer, including a first flat a second flat portion, and a slope portion connecting the first flat portion and the second flat portion; and an electrode layer including a drain and a source, the drain being located at the first flat portion Above, the source is located above the second flat portion. The thin film transistor substrate of claim 1, wherein the slope portion forms an angle with the second flat portion, the angle being greater than 90° and less than 150°. The thin film transistor substrate of claim 1, wherein the substrate layer has a light shielding layer disposed relative to the slope portion. The thin film transistor substrate of claim 1, wherein the first ohmic contact layer is between the drain and the first flat portion, and the first and second flat portions have a first Two ohmic contact layer. The thin film transistor substrate of claim 1, further comprising a protective layer and a pixel electrode layer interposed between the pixel electrode layer and the electrode layer, the protective layer comprising a contact a hole through which the pixel electrode layer is electrically connected to the source. The thin film transistor substrate according to claim 1, wherein the slope portion has a length of from 0.05 μm to 1 μm. A method for fabricating a thin film transistor substrate comprises: (a) forming a gate on a substrate layer; (b) sequentially forming a gate insulating layer, a semiconductor layer and a gate on the gate and the substrate layer; An electrode preparation layer, wherein the semiconductor layer has a first flat portion, a second flat portion, and a slope portion connecting the first flat portion and the second flat portion; (c) forming a layer on the electrode preparation layer a patterned photoresist layer, the photoresist layer includes a first photoresist layer, a second photoresist layer, and a third photoresist layer, wherein the second photoresist layer is disposed opposite to the slope portion, and the second layer The thickness of the photoresist layer is less than the thickness of the first photoresist layer and the thickness of the third photoresist layer, and then removing the second photoresist layer; (d) removing the electrode preparation layer opposite to the second photoresist layer, Until the semiconductor layer is exposed, forming a drain and a source respectively corresponding to the first flat portion and the second flat portion; and (e) removing the first photoresist layer and the third light Resistance layer. The method for fabricating a thin film transistor substrate according to claim 7 , wherein the step (a) forms a patterned light shielding layer on a substrate, and then forms a filling material on the patterned light shielding layer. The substrate layer is formed. The method for fabricating a thin film transistor substrate according to claim 7, wherein the step (b) further forms a patterned ohmic contact preparation layer between the semiconductor layer and the electrode preparation layer. Fabrication of a thin film transistor substrate according to item 7 of the patent application scope The method further includes a step (f) and a step (g) after the step (e), wherein the step (f) is to form a protective layer, the protective layer has a contact hole, and the step (g) is forming a pixel electrode layer, the pixel electrode layer being electrically connected to the drain electrode by the contact hole. A display having a thin film transistor substrate, comprising: a circuit unit; a thin film transistor substrate electrically connected to the circuit unit for driving, the thin film transistor substrate comprising: a substrate layer, a gate On the substrate layer, a gate insulating layer is disposed on the gate, and a semiconductor layer is disposed on the gate insulating layer, including a first flat portion, a slope portion and a second flat portion, and an electrode The layer includes a drain and a source, the drain is located above the first flat portion, the source is located above the second flat portion, and a display unit is disposed on the thin film transistor substrate A predetermined image is produced in a controlled manner. A display having a thin film transistor substrate according to claim 11, wherein the slope portion of the thin film transistor substrate forms an angle with the second flat portion, the angle being greater than 90° and less than 150°. A display having a thin film transistor substrate according to claim 11, wherein the substrate layer of the thin film transistor substrate has a light shielding layer disposed relative to the slope portion. According to the invention of claim 11, the thin film transistor substrate The display has a first ohmic contact layer between the drain of the thin film transistor substrate and the first flat portion, and a second ohmic contact layer between the source and the second flat portion. The display device with a thin film transistor substrate according to claim 11, wherein the thin film transistor substrate further comprises a protective layer and a pixel electrode layer, the protective layer being interposed between the pixel electrode layer and the electrode Between the layers, the protective layer includes a contact hole, and the pixel electrode layer is electrically connected to the source via the contact hole. A display having a thin film transistor substrate according to claim 11, wherein the slope of the thin film transistor substrate has a length of from 0.05 μm to 1 μm. The display unit of claim 11, wherein the display unit comprises a color filter substrate, and the color filter substrate is disposed opposite to the thin film transistor substrate. A display having a thin film transistor substrate according to claim 17, wherein the display unit comprises a liquid crystal layer interposed between the thin film transistor substrate and the color filter substrate. The display unit having a thin film transistor substrate according to claim 18, wherein the display unit comprises a backlight module, wherein the backlight module is disposed relative to the thin film transistor substrate, and the thin film transistor substrate is interposed therebetween Between the color filter substrate and the backlight module.