TWI460516B - Pixel structure and manufacturing method thereof - Google Patents

Description

Pixel structure and its making method

The invention relates to a pixel structure and a manufacturing method thereof, in particular to a high-resolution pixel structure and a manufacturing method thereof.

Flat-panel displays, such as liquid crystal displays, have replaced traditional cathode ray tube (CRT) displays due to their thinness, shortness, low radiation and low power consumption, and have become the mainstream of displays. In the development of displays, the system continues to develop in the direction of high resolution requirements. However, as the resolution increases, the number of thin film transistors (TFTs) on the panel also increases, making the available space on the panel shrink. At the same time, in order to improve the aperture ratio and the performance of the thin film transistor, the number of times of photolithography and photo-etching process (hereinafter referred to as PEP) is increased in the process design. However, the reduction of available space and the increase in the number of PEPs have led to the difficulty and cost of process control, which is not conducive to the production and development of display panels. Therefore, the current production methods of displays are not important to reduce the number of PEPs. Development goals.

In addition, in the display, a flat layer having a large thickness is often provided to facilitate the rotation of the liquid crystal molecules. However, the arrangement of such a thick flat layer often results in its front and back layers, for example, pixels formed after the flat layer and formed thereon. The electrode is not easily electrically connected to the gate electrode formed before and under the flat layer, and the yield of the display is lowered.

It can be seen that there is still a need for a pixel structure that can reduce the difficulty of process and process cost, and can effectively improve the electrical connection of the film layer before and after the flat layer and the manufacturing method thereof.

An object of the present invention is to provide a pixel structure and a manufacturing method thereof, which can reduce process difficulty and process cost, and at the same time improve display yield.

To achieve the above object, the present invention provides a method of fabricating a pixel structure. First, a substrate is provided on which at least one thin film transistor is formed, and the thin film transistor includes a gate electrode, a source electrode, and a drain electrode. Next, a first protective layer and a flat layer are sequentially formed on the substrate, the first protective layer covers the thin film transistor, and the flat layer covers the first protective layer. The planarization layer has a first opening, and the first opening corresponds to the drain electrode and exposes a portion of the first protective layer on the drain electrode. Subsequently, a patterned first conductive layer is formed on the first protective layer, the patterned first conductive layer covers the sidewall of the first opening and a portion of the first protective layer, and the patterned first conductive layer has a second opening, which is exposed A portion of the first protective layer within the first opening. After forming the patterned first conductive layer, a second protective layer is formed on the patterned first conductive layer. Subsequently, a photoresist pattern layer is formed on the second protective layer, and the photoresist pattern is formed The layer exposes a portion of the second protective layer within the first opening. Next, the second protective layer exposed by the photoresist pattern layer is etched to form a third opening, and the third opening exposes a partially patterned first conductive layer and a portion of the first protective layer. After forming the third opening, the first protective layer exposed by the patterned first conductive layer is etched to form a fourth opening in the first protective layer, and the fourth opening exposes a portion of the drain electrode, and then removed Photoresist pattern layer. After the photoresist pattern layer is removed, a patterned second conductive layer is formed on the second protective layer and in the second opening, the third opening and the fourth opening, and the patterned second conductive layer is electrically connected and exposed. The first conductive layer and the drain electrode are patterned.

In order to achieve the above object, the present invention further provides a pixel structure, disposed on a substrate, comprising at least one thin film transistor disposed on the substrate, a first protective layer disposed on the substrate and covering the thin film transistor, a planar layer disposed on the first protective layer, a pixel electrode disposed on the planar layer, a second protective layer disposed on the pixel electrode, and a bridge electrode disposed on the second protective layer. The thin film transistor includes a gate electrode, a source electrode, and a drain electrode, and the first protective layer has a fourth opening, and the fourth opening exposes a portion of the drain electrode. The flat layer includes a first opening corresponding to the fourth opening and exposing a portion of the first protective layer on the drain electrode. The pixel electrode includes a second opening corresponding to the first opening and the fourth opening and exposing the drain electrode. The second protective layer has a third opening corresponding to the second opening, and the fourth opening and the third opening expose the drain electrode and the partial pixel electrode on the first protective layer. And the bridge electrode disposed on the second protective layer is more The first electrode, the second opening, the third opening and the fourth opening are disposed, and the bridge electrode is electrically connected to the exposed drain electrode and the partial pixel electrode on the first protective layer.

The present invention will be further understood by the following detailed description of the preferred embodiments of the invention, .

Please refer to FIG. 1 to FIG. 9 , wherein FIG. 1 to FIG. 7 are schematic diagrams showing a method for fabricating a pixel structure according to a preferred embodiment of the present invention, and FIG. 8 is a preferred embodiment of the present invention. A schematic diagram of one of the pixel structures is provided, and FIG. 9 is a partially enlarged schematic view of the pixel structure. As shown in Fig. 1, a substrate 102 is first provided. The substrate 102 can be a rigid substrate such as a glass substrate or a flexible substrate such as a plastic substrate, but is not limited thereto. Next, at least one thin film transistor 110 is formed on the substrate 102. In one embodiment, a patterned first conductor layer M1 and an insulating layer 114 covering the patterned first conductor layer M1 are sequentially formed on the substrate 102. The patterned first conductor layer M1 includes at least one gate electrode 112. The patterned first conductive layer M1 may be a single conductive layer or a plurality of conductive layers. For example, the material of the patterned first conductive layer M1 may be a metal conductive material, a transparent conductive material or a stack of a metal conductive material and a transparent conductive material. Floor. The metal conductive material is, for example, a metal such as aluminum, copper, silver, gold, titanium, molybdenum or tungsten, and an alloy or a laminate thereof; a transparent conductive material For example, indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and the like. The insulating layer 114 can be used as a gate insulating layer, and the material thereof can be yttrium oxide, tantalum nitride or yttrium oxynitride, but is not limited thereto. Then, a patterned second conductor layer M2 is formed on the insulating layer 114. The patterned second conductor layer M2 includes at least one source electrode 116a and one drain electrode 116b, and the source electrode 116a corresponds to the drain electrode 116b. The ground is located on both sides of the gate electrode 112. The patterned second conductor layer M2 may be a single metal layer or a plurality of metal layers. The material of the patterned second conductor layer M2 may also be a metal conductive material, a transparent conductive material or a laminate of a metal conductive material and a transparent conductive material. The metal conductive material is, for example, a metal such as aluminum, copper, silver, gold, titanium, molybdenum or tungsten, and an alloy or a laminate thereof; and the transparent conductive material is, for example, indium tin oxide, indium zinc oxide, aluminum zinc oxide or the like.

Please refer to Figure 2. After forming the patterned second conductor layer M2, a patterned semiconductor layer 118 is formed on the insulating layer 114; in another embodiment, a patterned protective layer 119 is further formed on the patterned semiconductor layer 118. As shown in FIG. 2, the patterned semiconductor layer 118 and the patterned protective layer 119 correspond to the gate electrode 112 and cover part of the source electrode 116a and the part of the drain electrode 116b on the adjacent sides. In the present embodiment, the material of the patterned semiconductor layer 118 is, for example, indium gallium zinc oxide (IGZO), amorphous germanium, a germanium germanium or the like. The patterned protective layer 119 may include an inorganic protective layer or an organic protective layer, and the inorganic protective layer is made of, for example, oxygen. Silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, etc.; the material of the organic protective layer is, for example, polyamine (polyimide), organic silica glass, etc., but are not limited thereto. The material of the patterned semiconductor layer 118 may also include other semiconductor materials, and the material of the patterned protective layer 119 may also be other inorganic or organic materials. As shown in FIG. 2, in this embodiment, at least one thin film transistor 110 is formed on the substrate 102. Since the steps of forming the constituent film layers of the thin film transistor 110 are well known to those of ordinary skill in the art, such details are not described herein again, and those of ordinary skill in the art can make equivalent Variety.

Please continue to see Figure 2. After the fabrication of the thin film transistor 110 is completed, the first protective layer 120 and a flat layer 130 are sequentially formed on the substrate 102. The first protective layer 120 covers the thin film transistor 110; and the flat layer 130 covers the flat layer 130. The first protective layer 120. The first protective layer 120 may include an inorganic protective layer made of a material such as tantalum nitride, hafnium oxide, tantalum oxynitride, etc.; the flat layer 130 may include an organic insulating layer or an inorganic insulating layer, and the material of the organic insulating layer is, for example, polyamidamide. , acrylics, polypropylene, derivatives thereof, and the like; the material of the inorganic insulating layer is, for example, spin-on glass (SOG), but is not limited thereto. As shown in FIG. 2, the planarization layer 130 has a first opening 132 corresponding to the gate electrode 116b and exposing a portion of the first protective layer 120 on the drain electrode 116b. The flat layer 130 preferably uses a photosensitive material such as a positive or negative photoresist material. Thereby, the first opening 132 can be defined by an exposure development process without requiring an additional etching process. As shown in Fig. 2, the flat layer 130 has a relatively thick thickness so that a relatively flat surface can be obtained on the substrate 102 to facilitate the rotation of the liquid crystal molecules.

Please refer to Figure 3. After forming the planarization layer 130 having the first opening 132, a patterned first conductive layer 140 is then formed on the substrate 102, i.e., on the planarization layer 130. In this embodiment, the patterned first conductive layer 140 can serve as a pixel electrode PI of the pixel structure 100 (shown in FIG. 8), which can include a transparent conductive layer, and the material of the transparent conductive layer is, for example, indium tin. Oxide, indium zinc oxide or aluminum zinc oxide, etc., but is not limited thereto. The patterned first conductive layer 140 may further include a metal conductive layer overlapping and electrically connected to the transparent conductive layer to enhance the electrical conductivity of the patterned first conductive layer 140. As shown in FIG. 3, the patterned first conductive layer 140 covers a portion of the first protective layer 120 that covers the sidewall of the first opening 132 and the bottom of the first opening 132. In addition, the patterned first conductive layer 140 has a second opening 142 exposing a portion of the first protective layer 120 in the first opening 132 , and the second opening 142 is smaller than the first opening 132 . It is also worth noting that the patterned first conductive layer 140 has a bridging portion 140a on the first protective layer 120 at the bottom of the first opening 132.

Please refer to Figure 4. After the patterned first conductive layer 140 is formed, a second protective layer 150 is formed on the patterned first conductive layer 140 and the flat layer 130, and a photoresist pattern layer 160 is formed on the second protective layer 150. second The protective layer 150 may have the same inorganic material as the first protective layer 120 such as tantalum nitride, hafnium oxide, tantalum oxynitride, or the like, but may also contain other materials without being limited thereto. As shown in FIG. 4, the photoresist pattern layer 160 has an etch opening that exposes a portion of the second protective layer 150 within the first opening 132.

Please refer to Figure 5. Next, the second protective layer 150 exposed by the photoresist pattern layer 160 is etched to form a third opening 152 in the second protective layer 150. As shown in FIG. 5, the third opening 152 is formed in the first opening 132 and smaller than the first opening 132, and the third opening 152 exposes the bridging portion 140a of the patterned first conductive layer 140 in the first opening 132. And a portion of the first protective layer 120.

Please refer to Figure 6. After the third opening 152 is formed, the photoresist pattern layer 160 and the partially patterned first conductive layer 140 (ie, the bridge portion 140a) are used as an etch mask to etch the patterned first conductive layer 140. The first protective layer 120 is etched into the first protective layer 120 exposed to the third opening 152 and the second opening 142, and a fourth opening 122 is formed in the first protective layer 120. The fourth opening 122 is smaller than the first opening 122. The opening 132 and the fourth opening 122 expose a portion of the drain electrode 116b as shown in FIG.

Please refer to Fig. 7. Fig. 7 is a cross-sectional view taken along line A-A' in Fig. 8. The design of Fig. 8 can be changed according to the designer's requirements, and the layout design is not limited. After forming the fourth opening 122, the photoresist pattern is removed Case 160. Subsequently, a patterned second conductive layer 170 is formed on the second protective layer 150 and in the second opening 122, the third opening 132 and the fourth opening 142. In this embodiment, the patterned second conductive layer 170 includes a bridge electrode 171 and a common electrode 172. The bridge electrode 171 and the common electrode 172 are electrically isolated from each other by the gap 176, and the bridge electrode 171 preferably includes an island. shape. Since the patterned second conductive layer 170 includes the common electrode 172, it is preferably a patterned transparent conductive layer made of, for example, indium tin oxide or the like, but is not limited thereto. The patterned second conductive layer 170 further includes a patterned conductive metal layer (not shown) overlapping and electrically connected to the patterned transparent conductive layer to reduce the resistance value of the patterned second conductive layer 170. In other words, the bridge electrode 171 and the common electrode 172 can be formed by the same layer of patterned transparent conductive layer. In addition, in the present embodiment, the common electrode 172 may include a slit 174 as shown in FIG. 8, but those skilled in the art should understand that the shape of the slit 174 in FIG. 8 is merely an example. Not limited to this. More importantly, in the present embodiment, the bridge electrode 171 of the patterned second conductive layer 170 is electrically connected to the exposed patterned first conductive layer 140 and the drain electrode 116b as shown in FIG. That is, the pixel electrode PI and the drain electrode 116b are electrically connected by the bridge electrode 171.

Please refer to Figures 7 to 9. According to the method for fabricating the pixel structure provided in the embodiment, a pixel structure 100 is provided on the substrate 102. The pixel structure 100 includes at least one thin film transistor 110 disposed on the substrate 102, and the thin film transistor 110 includes a gate electrode 112 and a source electrode 116a. And the drain electrode 116b. The pixel structure 100 further includes a first protective layer 120 disposed on the substrate 102 and covering the thin film transistor 110, a flat layer 130 disposed on the first protective layer 120, a pixel electrode PI disposed on the flat layer 130, and a setting The second protective layer 150 on the pixel electrode PI and the bridge electrode 171 disposed on the second protective layer 150. As shown in FIGS. 7 to 9, the first protective layer 120 has a fourth opening 122, and the fourth opening 122 exposes a portion of the drain electrode 116b. The planarization layer 130 includes a first opening 132 that corresponds to the fourth opening 122 and the first opening 132 exposes a portion of the first protective layer 120 on the drain electrode 116b. The pixel electrode PI includes a second opening 142, and the second opening 142 corresponds to the first opening 132 and the fourth opening 122 and exposes the drain electrode 116b. The second protective layer 150 has a third opening 152 corresponding to the second opening 142, and the fourth opening 122 and the third opening 152 expose the drain electrode 116b and a portion of the pixel electrode PI located on the first protective layer 120. That is, the bridge portion 140a of the pixel electrode PI is exposed. In addition, as shown in FIG. 8 and FIG. 9, the third opening 152 and the second opening 142 preferably have a cross-staggered overlapping pattern to ensure the bridging portion 140a of the pixel electrode PI (such as the oblique line in FIG. 9). The location may be as an etch mask when etching the fourth opening 122, and the fourth opening 122 is obtained at a predetermined position, and the pixel electrode PI is exposed to the opening 132/142/152 to be disposed on the second protective layer. The bridge electrode 171 in the first opening 132, the second opening 142, the third opening 152 and the fourth opening 122 can be successfully electrically connected to the exposed drain electrode 116b and the portion located on the first protective layer 120. Prime electrode PI.

According to the pixel structure and the manufacturing method thereof provided by the embodiment, the photoresist pattern layer 160 for etching the third opening 152 in the second protective layer 150 and the pixel electrode PI (especially the pixel electrode PI) are utilized. The bridging portion 140a) acts as an etch mask, so that when the first protective layer 120 is etched to form the fourth opening 122, an additional PEP step is no longer needed. In other words, the method for fabricating the pixel structure provided by the embodiment can reduce the PEP step once, and effectively achieve the purpose of reducing the process cost. In addition, since the PEP step of forming the fourth opening 122 can be eliminated, the method for fabricating the pixel structure provided by the present invention can also dispense with problems derived from the PEP step, such as alignment problems and the like. Due to the high resolution and high pixel structure density requirements, the available space on the panel is more and more limited. The PEP step minus one time can not only shorten the process time and reduce the cost, but also avoid it. The problem of PEP steps occurs in the increasingly small space, which reduces the complexity of the process. Briefly, the method for fabricating the pixel structure provided by the embodiment can achieve the purpose of simplifying the process, reducing the process cost, and the complexity of the process.

According to the pixel structure 100 provided in this embodiment, since the third opening 152 and the second opening 142 have a cross-staggered overlapping pattern, the fourth opening 122 can be ensured to be interlaced with the second opening 152 and the second opening 142. The overlap, and ensuring that the bridging portion 140a of the pixel electrode PI is exposed in the opening 132/142/152, the hole in the hole is structured such that the bridging electrode 171 is accurately electrically connected to the crucible exposed in the fourth opening 122. The electrode electrode 116b and the pixel electrode PI on the first protective layer 120. In addition, due to electrical connection The island-shaped bridge electrode 171 of the gate electrode 116b and the pixel electrode PI is electrically isolated from the common electrode 172 by the gap 176. Therefore, the pixel structure 100 provided in this embodiment can ensure that the electrical performance is not affected. Under the premise, the electrical connection between the pixel electrode PI and the drain electrode 116b is successfully provided.

Please refer to FIG. 10 to FIG. 12 . FIG. 10 to FIG. 12 are schematic diagrams showing a method for fabricating a pixel structure according to another embodiment of the present invention. It should be noted that the same constituent elements in the embodiment as the foregoing embodiments may include the same material selection, and thus are not described herein again. As shown in FIG. 10, in the method for fabricating the pixel structure provided in this embodiment, a substrate 202 is first provided, and then a thin film transistor 210 is formed on the substrate 202. As previously mentioned, in one embodiment, the thin film transistor 210 includes a patterned first conductor layer M1 and an insulating layer 214 overlying the patterned first conductor layer M1. The patterned first conductor layer M1 includes at least one gate electrode 212. Next, a patterned semiconductor layer 218 is formed over the insulating layer 214. In the present embodiment, the patterned semiconductor layer 218 includes a patterned amorphous germanium semiconductor layer. The material of the patterned semiconductor layer 118 may also include other semiconductor materials.

Please refer to Figure 11. After forming the patterned semiconductor layer 218, a patterned second conductor layer M2 is formed on the substrate 202. The patterned second conductor layer M2 includes at least one source electrode 216a and one drain electrode 216b, and the source electrode 216a. It is located on both sides of the gate electrode 212 corresponding to the gate electrode 216b. As described above, the steps of forming the constituent film layers of the thin film transistor 110 The details are well known to those of ordinary skill in the art, and such details are not described herein.

Please refer to Figure 12. After the fabrication of the thin film transistor 210 is completed, a first protective layer 220 and a flat layer 230 covering the first protective layer 220 and having a first opening 232 are sequentially formed on the substrate 202. A patterned first conductive layer 240 is then formed on the substrate 202. The patterned first conductive layer 240 can serve as the pixel electrode PI and has a second opening 242. It should be noted that the patterned first conductive layer 240 has a bridging portion 240a on the first protective layer 220 at the bottom of the first opening 232. After forming the patterned first conductive layer 240, a second protective layer 250 and a photoresist pattern layer (not shown) are formed on the patterned first conductive layer 240 and the flat layer 230, and then the photoresist pattern layer is utilized. A second protective layer 250 is etched as a mask, and a third opening 252 is formed in the second protective layer 250. After the third opening 252 is formed, the first protective layer 220 is etched by using the same photoresist pattern layer and the patterned first conductive layer 240 at the bottom of the third opening 252 as an etch mask to form an exposure in the first protective layer 220. A fourth opening 222 of a portion of the drain electrode 216b is exited.

Please continue to see Figure 12. A patterned second conductive layer 270 is formed on the substrate 202, and the patterned second conductive layer 270 includes a common electrode 272 and a bridge electrode 271. It is noted that the bridge electrode 271 is formed in the second opening 242, the third opening 252 and the fourth opening 222, and is electrically connected to the gate electrode 216b and the bridge portion 240a of the pixel electrode PI (240). Pick up. In addition, the common electrode 272 and the bridge electrode 271 are electrically isolated from each other by the gap 276. The above steps are the same as those exemplified in the foregoing preferred embodiment, and therefore those skilled in the art should be readily aware of the foregoing embodiments and FIGS. 2 through 9, so that the details are no longer Narration.

The pixel structure and the manufacturing method thereof provided by the invention can be successfully integrated into the existing thin film transistor process, and a PEP step can be reduced, thereby reducing cost and process complexity. In addition, in the method for fabricating the pixel structure provided by the present invention, the second opening of the pixel electrode and the third opening of the second protective layer are formed by a cross-hole-stacked hole-like hole pattern. Ensure that both the drain electrode and the pixel electrode are exposed in the opening, further ensuring that the bridge electrode can provide an electrical connection between the drain electrode and the pixel electrode. In other words, the pixel structure and the manufacturing method thereof provided by the invention can effectively simplify the process, shorten the process time, and reduce the process cost and the process complexity under the premise of ensuring the electrical relationship of the pixel structure.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200‧‧‧ pixel structure

102, 202‧‧‧ substrate

110, 210‧‧‧ film transistor

112, 212‧‧ ‧ gate electrode

114, 214‧‧‧ insulation

116a, 216a‧‧‧ source electrode

116b, 216b‧‧‧汲electrode

118, 218‧‧‧ patterned semiconductor layer

119‧‧‧ patterned protective layer

120, 220‧‧‧ first protective layer

122, 222‧‧‧ fourth opening

130, 230‧‧‧ flat layer

132, 232‧‧‧ first opening

140, 240‧‧‧ patterned first conductive layer

140a, 240a‧‧‧bridged parts

142, 242‧‧‧ second opening

150, 250‧‧‧ second protective layer

152, 252‧‧‧ third opening

160‧‧‧ photoresist pattern layer

170, 270‧‧‧ patterned second conductive layer

171, 271‧‧ ‧ bridging electrodes

172, 272‧‧‧ common electrode

174, 274‧‧ slit

176, 276‧‧ ‧ gap

M1‧‧‧ patterned first conductor layer

M2‧‧‧ patterned second conductor layer

PI‧‧‧ pixel electrodes

A-A’‧‧‧ cut line

1 to 7 are schematic views showing a method of fabricating a pixel structure according to an embodiment of the present invention.

Figure 8 is a schematic diagram showing one of the pixel structures provided in the embodiment.

FIG. 9 is a partially enlarged schematic view showing the structure of the pixel provided by the embodiment.

10 to 12 are schematic views showing a method of fabricating a pixel structure according to another embodiment of the present invention.

100‧‧‧ pixel structure

102‧‧‧Substrate

110‧‧‧film transistor

112‧‧‧gate electrode

114‧‧‧Insulation

116a‧‧‧Source electrode

116b‧‧‧汲electrode

118‧‧‧ patterned semiconductor layer

119‧‧‧ patterned protective layer

120‧‧‧First protective layer

122‧‧‧fourth opening

130‧‧‧flat layer

132‧‧‧ first opening

140‧‧‧ patterned first conductive layer

140a‧‧‧Bridge section

142‧‧‧ second opening

150‧‧‧Second protective layer

152‧‧‧ third opening

170‧‧‧ patterned second conductive layer

171‧‧‧Bridge electrode

172‧‧‧Common electrode

174‧‧‧slit

176‧‧‧ gap

M1‧‧‧ patterned first conductor layer

M2‧‧‧ patterned second conductor layer

PI‧‧‧ pixel electrodes

A-A’‧‧‧ cut line

Claims (13)

A method for fabricating a pixel structure, comprising: providing a substrate on which at least one thin film transistor is formed, the thin film transistor comprising a gate electrode, a source electrode and a drain electrode; Forming a first protective layer and a flat layer, the first protective layer covers the thin film transistor, and the flat layer covers the first protective layer, the flat layer has a first opening, and the first opening corresponds to The drain electrode exposes a portion of the first protective layer on the drain electrode; forming a patterned first conductive layer on the planar layer, the patterned first conductive layer covering sidewalls and portions of the first opening The first protective layer has a second opening exposing a portion of the first protective layer in the first opening; forming a second protective layer on the patterned first conductive layer; Forming a photoresist pattern layer on the second protective layer, the photoresist pattern layer exposing a portion of the second protective layer in the first opening; etching the second protective layer exposed by the photoresist pattern layer, To form a third opening, The third opening exposes a portion of the patterned first conductive layer and a portion of the first protective layer; etching the first protective layer exposed by the patterned first conductive layer to form a first layer in the first protective layer a fourth opening exposing a portion of the drain electrode; Removing the photoresist pattern layer; and forming a patterned second conductive layer on the second protective layer and the second opening, the third opening and the fourth opening, the patterned second conductive layer electrical The exposed patterned first conductive layer and the drain electrode are connected. The method of claim 1, wherein the forming the thin film transistor further comprises: forming the gate electrode and an insulating layer covering the gate electrode on the substrate; forming the source on the insulating layer An electrode and the drain electrode; and a patterned semiconductor layer and a patterned protective layer are formed on the insulating layer. The method of claim 2, wherein the patterned semiconductor layer comprises a patterned oxide semiconductor layer. The manufacturing method of claim 1, wherein the forming the thin film transistor comprises: forming the gate electrode and an insulating layer covering the gate electrode on the substrate; forming a patterned semiconductor on the insulating layer And forming the source electrode and the drain electrode on the insulating layer and the patterned semiconductor layer. The method of claim 4, wherein the patterned semiconductor layer comprises a patterned amorphous germanium semiconductor layer. The method of claim 1, wherein the patterned second conductive layer comprises a bridge electrode and a common electrode, the bridge electrode and the common electrode are electrically isolated from each other, and the patterned first conductive layer comprises a pixel An electrode, wherein the pixel electrode and the gate electrode are electrically connected by the bridge electrode. A pixel structure is disposed on a substrate, the pixel structure includes: at least one thin film transistor disposed on the substrate, the thin film transistor comprising a gate electrode, a source electrode and a drain electrode; a first protective layer disposed on the substrate and covering the thin film transistor, the first protective layer has a fourth opening, and the fourth opening exposes a portion of the drain electrode; a flat layer is disposed on the first protection On the layer, the flat layer includes a first opening corresponding to the fourth opening, and the first opening exposes a portion of the drain electrode and a portion of the first protective layer; a pixel electrode is disposed On the flat layer, the pixel electrode includes a second opening corresponding to the first opening and the fourth opening and exposing the drain electrode; a second protective layer disposed on the pixel The second protective layer has a third opening corresponding to the second opening, and the fourth opening and the first a third opening exposing the drain electrode and a portion of the pixel electrode on the first protective layer; and a bridge electrode disposed on the second protective layer and the first opening, the second opening, the third The opening is electrically connected to the exposed electrode and the portion of the pixel electrode on the first protective layer. The pixel structure of claim 7, further comprising a common electrode disposed on the second protective layer. The pixel structure of claim 8, wherein the common electrode and the bridge electrode are formed by the same layer of patterned transparent conductive layer, and the common electrode and the bridge electrode are electrically isolated from each other. The pixel structure of claim 7, wherein the first opening is larger than the second opening, the third opening, and the fourth opening. The pixel structure of claim 7, wherein the thin film transistor further comprises a patterned semiconductor layer corresponding to the gate electrode. The pixel structure of claim 11, wherein the patterned semiconductor layer comprises a patterned oxide semiconductor layer, and the source electrode and the drain electrode are disposed on the patterned oxide semiconductor layer and the gate Between the electrodes. The pixel structure of claim 11, wherein the patterned semiconductor layer comprises a patterned amorphous germanium semiconductor layer, and the patterned amorphous germanium semiconductor layer is disposed on the source electrode and the drain electrode and the gate Between the poles.