TW200522168A - Manufacturing method of thin film transistor array substrate - Google Patents

Abstract

A manufacturing method of thin film transistor array substrate is disclosed. First, offering a substrate that has a pixel area and a pad area. A plurality of scan lines, a plurality of data lines and a plurality of thin film transistors are disposed on the pixel area of substrate. A plurality of bonding pads is disposed on the pad area of substrate. Then, form a passivation layer and a planarization layer in order. The planarization layer has a plurality of first opens and a plurality of second opens. The planarization layer has a first thickness in the pixel area and has a second thickness in the pad area. After, remove the material layer exposed by the first opens and the second opens with the planarization layer for mask until the drains of thin film transistors and the bonding pads are exposed. Final, form a plurality of pixel electrodes that electrically connecting to the drains and a plurality of electrode layer that electrically connecting to the bonding pads.

Description

200522168 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a method for manufacturing a thin film transistor array substrate (TFT array substrate), and in particular, to an avoidable metal Method for manufacturing thin film transistor array substrate in which layer and protective layer are damaged during heavy work. 2. prior art thin film transistor liquid crystal display panel

Liquid Crystal Display panel (TFT LCD panel) is mainly composed of a thin film transistor array substrate, a color filter array substrate (Color fi Iter array substrate), and a liquid crystal layer. The thin film transistor array substrate is composed of a plurality of arrayed arrays. A thin film transistor, and a pixel electrode (Pixel Electrode) arranged corresponding to each thin film transistor. The aforementioned thin film transistor system includes a gate, a channel layer, a drain, and a source. The thin film transistor system is used as a switching element of a liquid crystal display unit. The operation principle of a thin film transistor is similar to that of a conventional semiconductor device, which is a device with three terminals (gate, drain, and source). Generally, thin film transistor components can be divided into two types: polycrystalline silicon (? 〇1 丫 3 丨 1 丨 (: 〇11) and amorphous silicon (Amorphous si 1 i con)). Among them, amorphous silicon thin film transistors are more mature. Technology. As far as the amorphous silicon thin film liquid crystal display is concerned, its manufacturing process generally includes forming a gate, a channel layer, a source / drain, a day electrode and a protective layer on a substrate. The first figure is shown as a Top view of a conventional thin film transistor array substrate

12028twf.ptd Page 7 200522168

The figure shows the cross section of the process from 1-1 in Figure 1

Figures, 2A to 2E. Please refer to the first picture. 9 A country m / r ^ ^ ^ Μ # ϋ $ A 4 /, Figure 2A, S know that the thin film transistor array substrate 100 first performs the first optical military system ... on the substrate 50 "A" and the scanning wiring 120 connected to it, and at the same time, a pad 122 is formed at the end of the scanning wiring 120. Then, a gate dielectric layer 130 is covered over the substrate 50. Next, referring to FIG. 1 and Figure 2B, the second mask process is performed to form a channel layer 114 on the gate dielectric layer 13 above the gate 112. Next, referring to Figure 1 and Figure 2c, the third mask process is performed. The source / drain 116/118 and the data wiring 140 'connected to the source 16 are formed, and at the same time, another pad 142 is formed at the end of the data wiring 丨 40. Then, a protective layer 150 is covered on the substrate 50 Next, referring to FIG. 1 and FIG. 2D, a fourth photomask process is performed to form a patterned planar layer (Planarization layer) 160 'on the protective layer 150. The drain electrode 118 and the solder pad 122 are exposed. The protective layer 150 above 142. Then, using the flat layer 160 as an etching mask, the solder pads 1 2 2, 142 are removed. The gate dielectric layer 130 and the protective layer 150 are removed, and the protective layer 150 is removed from the drain 118. Finally, referring to FIG. 1 and FIG. 2E, a fifth photomask process is performed on the flat layer 160. A day electrode 170 is formed, and an electrode material layer 172 is covered on the surfaces of the pads 122 and 142. The purpose of forming the flat layer on the protective layer is to improve the aperture ratio of the liquid crystal display. Due to the existence of the flat layer, the pixel electrode can Extended cover

12028twf.ptd Page 8 200522168 V. Description of the invention (3) Covering part of the data wiring to improve the aperture ratio. This is because the thickness of the flat layer is thick enough to avoid parasitic capacitance between the pixel electrode and the data wiring ( Parasitic capacitance) is too large without affecting the characteristics of the panel. In the subsequent process, the driving chip for driving the data wiring and the scanning wiring is made of an anisotropic conductive adhesive film (Anis〇tr〇pic

Conductive Film (ACF) is electrically connected to the pad. However, the bonding wafer + ^ process often requires heavy work. During heavy work, because the area around the pad is covered with a flat layer, if you want to remove the anisotropic conductive adhesive film, it will often tear up the material similar to the Tan layer, and then cause damage to the underlying protective layer and metal layer, which The entire thin film transistor array substrate can no longer be used. Therefore, the purpose of the present invention is to provide a method for manufacturing a thin-film ray afp, which is suitable for reducing the manufacturing process of subsequent wafer bonding. The purpose of the present invention is to provide a thin-film transistor array substrate area plate and a bonding pad. This area :: The system first provides-the basic substrate is provided with-pixel data wiring and ;; area: J area; there are less than a plurality of scanning wiring, multiple formation-ΐ: There are multiple pads. Next, there are a plurality of first layers on the substrate; a flat layer is formed on the protective layer, and the flat layer is above the :; on; and a plurality of second openings σ. The first opening is located in the drain electrode layer, which has a stem and an eyebrow. It is located at the first thickness of the day zone and the flat layer at the pad area has a second 12028twf.ptd. Page 9 200522168 5. Description of the Invention (4) The thickness is greater than the first thickness. Then, using the flat layer as a mask ', the material layers exposed by the first opening and the second opening are removed until the electrode and the pad are exposed. Finally, a plurality of pixel electrodes and a plurality of electrode material layers are formed on the flat layer. Among them, the drain electrode is electrically connected to the day element electrode, and the electrode material layer is electrically connected to the pad. In addition, in the manufacturing method of the thin film transistor array substrate of this embodiment, before removing the material layer exposed by the first opening and the second opening, the first thickness of the flat layer is, for example, between 2 and 6 microns (# m), the second thickness of the flat layer is, for example, between 0.3 μm and 1.4 μm. 8 微米。 After removing the material layer exposed by the first opening and the second opening, the second thickness of the flat layer is, for example, less than 0.8 microns. Based on the above object, the present invention further proposes a method for manufacturing a thin film transistor array substrate. In this method, a substrate is first provided. The substrate has a pixel region and a pad region. Next, a plurality of scanning wiring spots and a plurality of gates are formed on the day element area. A plurality of first pads are formed in the pad region, and the gate and the first series are respectively electrically connected to the scanning wiring. After that, a free dielectric layer is formed on the substrate to cover the scan wiring and the gate. Then, a plurality of channel layers are formed in the gate, and the position of the channel layer corresponds to the position of the gate electrode ^. Next, a source and a drain are formed on each channel layer, a plurality of data wirings are drawn, and a plurality of second pads are formed in the pad area. In 17, the source and the second pad are electrically connected to the data wiring, respectively; and the electrode, the channel layer, the source and the drain constitute a plurality of thin film transistors. After that, a protective layer is formed over the substrate. Then, a layer is formed on the protective layer, and the flat layer has a plurality of first openings and a plurality of second openings. two

12028twf.ptd Page 10 200522168 V. Description of the Invention (5) is located above the drain electrode, square. Among them, the flat layer in the pad area has a thickness. Then, flatten the exposed material layer. Finally, on a flat material layer. Wherein, the drain electrode and the first bonding pad and the second, in this implementation, after removing the first thickness of the first open layer, for example, if the material layer is between 0.3 and 1.4, exposed in the above two The pair of photo-sensitive dielectric layer type photomasks that form a flat layer include, for example, a striped half-tone type photomask. The first ^ opening system element area is flat with a second thick tan layer as a mask. Until the multi-system and pixel electrical pads are formed on the exposed layer, the thin film electrical port and the second opening are located on the first layer. In addition, the drain electrode is electrically connected to the day electrode. The crystal array exposes the thickness of a welding ridge and the second welding sound, and the degree is greater than Chu_ The first opening and the second opening: a pad and a second ridge and a plurality of electrode materials. The electrode material layer is a first. The first thick, first electrode is connected between 2 and 6 microns. The method of removing the thin film of the second embodiment of the first layer is, for example, performing a plurality of micron-thickness transistors to form an exposure electrical layer for one exposure, a half-tone photomask, and a flat layer opening of a grid substrate. The exposure of the second opening is less than 0.8 microns. The manufacturing method of the array substrate is a photosensitive dielectric layer, a process' or a half-modulation process. Among them, the second thickness example of flatness before the half-tone half-tone mask or dot-shaped manufacturing method material layer, as described above, because the flat layer in the pad area has almost disappeared, so when subsequent wafer bonding rework, It will not damage the protective layer and metal layer in the pad area, so it can improve the success rate of wafer bonding rework. First, in order to make the above and other objects, features, and advantages of the present invention more clear * ,,, and easy 1 * 蓳, the following exemplifies a preferred embodiment and cooperates with the accompanying drawings for details

200522168

V. Description of the invention (6) The following embodiment is illustrated. Figure 3 is not a schematic top view of a thin film transistor array substrate according to a preferred embodiment of the present invention, and Figures 4A to 4F are shown in Figure 3. Schematic sectional view of the process of Π-Π. The present invention discloses a method for manufacturing a thin-film transistor array substrate. The thin-film transistor array, a daylight element structure, and a part of the pads are described in detail below and in the drawings. Referring to FIG. 3 and FIG. 4A, the manufacturing method of the thin film transistor array substrate 2000 is to first provide a substrate 50, which has a pixel area A and a pad area B. Next, a first mask process is performed to form a plurality of scanning wirings “ο” and a plurality of gates 212 on the pixel area A of the substrate 50, and a plurality of first pads 222 are formed on the pad area b, and The gate electrode 212 and the first bonding pad 222 are respectively electrically connected to the scanning wiring 220. Among them, the scanning wiring 22, the gate electrode 212, and the first bonding pad 222 belong to the first metal layer (M1). Then, on the substrate 50, A gate dielectric layer 230 is formed thereon to cover the scan wiring 220 and the gate electrode 212. The material of the gate dielectric layer 23 is, for example, silicon nitride or stone oxide. Next, please refer to FIG. 3 and FIG. 4B. A second mask process is performed to define a channel layer 214 on the gate dielectric layer 230 above the gate electrode 212. At the same time, for example, in the same mask process, an etch stop layer δ 280 and an ohmic contact layer 285 are successively formed. On the channel layer 214. The material of the channel 9 layer 214 is, for example, amorphous silicon (a-Si), the material of the etch stop layer 280 is, for example, silicon nitride, and the material of the ohmic contact layer 285 is, for example, doped Of the amorphous stone (n + a-Si).

200522168 V. Description of the invention (7) Next, referring to FIG. 3 and FIG. 4C, the third mask process is performed, and a source electrode 216, a drain electrode 218, and a plurality of data wirings 240 are formed above each channel layer 214. A plurality of second pads 242 are formed in the pad region b of the substrate 50. The source electrode 216 and the second pad 242 are electrically connected to the data wiring 240, respectively. The gate electrode 212, the channel layer 214, the source electrode 216, and the drain electrode 218 constitute a plurality of thin film transistors 2 1 0. The source electrode 2 1 6, the drain electrode 2 1 8, the data wiring 240 and the second bonding pad 242 are all a second metal layer (M2). After defining the second metal layer, a protective layer 2 50 is formed on the substrate 50 to cover the second metal layer (source 2 丨 6, drain 2 丨 8, data wiring 240, and second pad 242). ). The material of the protective layer 25 is, for example, nitrided oxide or oxidized stone. Referring to FIG. 3 and FIG. 4D, a fourth mask process is performed to form a flat layer 260 on the protection layer. The flat layer 260 has a plurality of first and second openings 02. The first opening 01 is located at the second side. The first opening 02 is located at the sides of the first pad 222 and the second pad 242. In the middle of the eighth, the flat layer 26o located in the pixel area A has a first pad area B. The flat layer 260 has a second thickness. The production H1 is larger than the second thickness. At this time, if the thickness of the flat layer 介于 is between 2 and 6 micrometers, the flat layer 260: J = 0.3 ~ 1.4 micrometers. For example, the method of forming a flat layer 2 60 is performed, for example, using a method shown in FIG. The photomask (not shown in the figure) has a photoresist material V :: Material = if the system is shown as a thin film according to the preferred embodiment of the present invention. 200522168 V. Description of the invention (8) A schematic diagram of a half-tone mask. Please refer to FIG. 31) and FIGS. 5a to%. The half-tone mask 300 can be divided into, for example, a completely transparent region, a transparent region 320, and an opaque region 33. Taking the flat layer 26 ° as a negative photoresistor blade as an example, in the exposure process, the completely transparent area 31 ° area is aligned above the pixel area A, and the partially transparent area 32 ° is aligned, for example, at the pad. Above the region 6, the opaque region 330 is aligned above the first pad 222 and the second pad 242, for example. Since the flat layer 26 of the pad area 6 is only partially exposed, its second thickness H2 will be smaller than the first thickness after development. The half-tone mask 3 0 0 is, for example, a striped half-tone mask (as shown in FIG. 5A), a mesh half-tone mask (as shown in FIG. 5B), or a dot-shaped half-tone mask (as shown in FIG. Do not). In this process, the gap of the half-tone mask 300 should be smaller than the resolution of the exposure process, and the flat layer 260 should be made of a material that is easier to reflow (Ref low), so that it will be easier to obtain the desired flatness. . In addition, the method for forming the flat layer 260 can also be performed in a multiple exposure process. The material of the flat layer 260 is, for example, a photosensitive dielectric layer, which has the characteristics of a photoresist material. Figures 6A to 6B are schematic cross-sectional views of the process of performing two exposures to form a flat layer. Please refer to FIG. 3 and FIG. BA. For the first exposure process, for example, a first photomask is used (not shown in the figure) so that the drain electrode 218 and the flat layer 260 above the pad region 6 undergo a photoreaction. Hi 者 ' Referring to FIG. 6B, a second photomask is used for the second exposure process, so that the flat layer 26 above the drain electrode 218, the first pad 222, and the second pad 242 (shown in FIG. 2 and 3) is used. 〇 Complete photoreaction. Therefore, the protection of the drain electrode 218, the first solder pad 222, and the second solder pad 242 after removing the flat layer 26 (the shaded part) that has undergone photo-reaction to make the photoreaction occur. The layer 12028twf 4pt (j page 14 200522168) 5. Description of the invention (9) 250 will be exposed, and the second thickness H2 of the flat layer 26 in the pad area b will also be smaller than the first thickness hi of the pixel area A. Then, referring to Figure 3 and Figure 4E, using the flat layer 2 60 as a mask, remove the material layers exposed by the first opening 01 and the second opening 0 2 until the drain electrode 218 and the first solder are removed. The pad 222 and the second solder pad 242. After removing the material layers in the first opening 01 and the second opening 02, the thickness of the flat layer 26o will also be slightly reduced, so the second thickness is, for example, less than 0. · 8 microns is preferred, or the flat layer 26 on the pad area B will completely disappear. However, if the flat layer 260 on the pad area B completely disappears, the gate dielectric layer 23 and protection of the pad area B will be completely eliminated. The total thickness of the layer 250 is preferably greater than 500 angstroms. ”” Finally, please refer to FIG. 3 and FIG. 4F to perform the fifth photomask f. A plurality of day element electrodes 27 and a plurality of electrode materials are formed on the layer 26. Among them, the drain electrode 218 is electrically connected to the pixel electrode 2 70 in the first opening 01, and the electrode material layer 272 is connected to the second opening. 〇2 is electrically connected to the first 222 and the second pad 242. According to FIG. 4F, Yu F, because the thickness of the flat layer 260 on the pad area B is "micron" or even completely disappeared, even after subsequent bonding Wafers 1. Need to rework 'will not break during the process of removing the anisotropic conductive adhesive film. The protective layer 250 under the tank layer 260, the gate dielectric layer 230 and the solder pad 222 are broken: 7 2? : Figures,! Are shown as another way to form a flat layer as shown in Figure 40: 0. Two pictures. Please refer to Figure? A, another way to form the 250th previous one. Ϋ For example, first form a dielectric layer 262 For the protective layer, refer to FIG. 7B to form-patterned photoresist layer 292

12028twf.ptd Page 15 200522168 V. Description of the Invention (ίο) The 'patterned photoresist layer 292 on the electrical layer 262 has a plurality of third openings 03 and a plurality of fourth openings 04' and the third opening 03 is located at the drain Above the pole 2 1 8, the fourth opening 04 is located above the first pad 222 and the second pad 242 (shown in FIG. 3). Among them, the patterned photoresist layer 292 in the daytime region A has a third thickness H3, and the patterned photoresist layer 292 in the pad region β has a fourth thickness Η4, and the second thickness Η3 is greater than the fourth thickness Thickness JJ4. The method for forming the patterned photoresist layer 292 is, for example, first forming a photoresist material layer 290 on the dielectric layer 2 6 2. Next, a half-tone photomask 30Q shown in FIGS. 5A to 5C is used to perform an exposure process on the photoresist material layer 290 to form a patterned photoresist layer 292. The method of forming the patterned photoresist layer 292 may also be to first form a photoresist material layer 290 on the dielectric layer 262. Next, the photoresist material layer 290 is subjected to multiple exposure processes by the method shown in FIGS. 6A to 6B to form a patterned photoresist layer 292. Please refer to FIG. 7B and FIG. 7 (:), using the patterned photoresist layer 292 as a mask, and remove the dielectric layer 262 not covered by the patterned photoresist layer 292 to form a flat layer 260. Finally, please Referring to FIG. 70, removing the patterned photoresist layer 2 92 can obtain the same flat layer 260 as that in FIG. 4D. As described above, by using a half-tone mask or a double exposure process, The flat layers of different thicknesses were obtained in the daytime element area and the pad area of the thin-film transistor array substrate, and after the flat layer was used as a mask to remove the first opening and the second opening material layer, the pad area The flat layer has almost disappeared. Therefore, even if rework is required for subsequent wafer bonding, the protective layer and metal layer of the pad area will not be damaged because the anisotropic conductive adhesive film is similar to the material of the flat layer, and the wafer bonding rework Success rate. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to

12028twf.ptd Page 16 200522168 V. Description of the invention (11) The invention is limited. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the invention. Therefore, the scope of protection of the invention It shall be subject to the definition in the appended patent application scope.

12028twf.ptd Page 17 200522168

Brief Description of the Drawings Figure 1 is a top view of a conventional thin film transistor array substrate. Figures 2A to 2E are schematic diagrams of the process from 1_1 in Figure 1. FIG. 3 is a schematic top view of a thin film transistor array substrate according to a preferred embodiment of the present invention. Figures 4A to 4F are schematic diagrams of the manufacturing process from E to n in Figure 3. Figures 5A to 5C are schematic diagrams of a half-tone photomask used in a thin film body array substrate according to a preferred embodiment of the present invention. Figures 6A to 6B are schematic cross-sectional views of the process of performing two exposure processes to form flat chips. Figs. 7A to 7D of Fig. 9 are schematic cross-sectional views of another process for forming the method as shown in Fig. 4D. Continued formula [Schematic description] 50. Substrate I 00: Thin film transistor array substrate II 2: Gate 114: Channel layer 11 6: Source 11 8: Drain 1 2 0: Scanning wiring 122 142: Pad 1 3 0: Gate dielectric layer

12028twf.ptd Page 18 200522168

Brief description of the drawing 140 data wiring 150 protective layer 160 flat layer 170 day element 172 electrode material layer 200 thin film transistor array substrate 210 thin film transistor 212 gate 214 channel layer 216 source 218 drain 220 scanning wiring 222 ', 242: pad 230 gate dielectric layer 240 data wiring 250 protective layer 260 flat layer 262 dielectric layer 270 day electrode 272 electrode material layer 280 #etch stop layer 285 ohmic contact layer 290 photoresist material layer 292 patterned photoresist layer 12028twf.ptd Page 19 200522168

12028twf.ptd Page 20

Claims (1)

200522168 VI. Scope of patent application1. A method for manufacturing a thin film transistor array substrate, including providing a substrate with a daytime pixel area and a pad area, at least a plurality of scanning wirings and a majority of the pixel area are arranged on the pixel area. A piece of data wiring and a plurality of thin-film transistors having a pole, a source, and a drain, and at least a plurality of solder pads are arranged on the pad area; a protective layer is formed above the substrate; A flat layer is formed on the layer. The flat layer has a plurality of first openings, and second openings. The first openings are located on the drain electrodes, and the second openings are located above the pads. The flat layer in the pixel area has a first thickness, and the flat thickness in the pad area is greater than the second thickness. Doorway: ί: ί layer is a cover The curtain 'removes the first openings and the second fin material layers until the drain electrodes and the welds are exposed, and the material layers are electrically connected to the majority of pixel electrodes and the majority of electrode materials. i 材 i 声 S i 二 ^^ 极And the plurality; and electrically connected, and the plurality of m-based electrode material layer is electrically connected to Tu and the plurality of bonding pads. 2. The manufacturing method according to the scope of the patent application, wherein before removing the material layer exposed by the / special dielectric array substrate, the flattening is performed; the second openings are: -Thick sound & x drought is between 2 ~ 6 micro 3. As claimed; patent | Dagger: between 0.3 ~ 4 micron. 8 微 面 12028twf The manufacturing method, in which after removing the material layer exposed by the 4 film transistor array substrate, the second thickness of the flat opening and the second openings is less than 0.8 microface 12028twf .ptd Page 21 200522168 4. The method for manufacturing a thin film transistor array substrate according to item 丨 of the patent application, wherein the method for forming the flat layer includes: forming a photosensitive dielectric layer; and using a half-tone mask to the photosensitive dielectric layer. The layer undergoes an exposure process. 5. The manufacturing method of the thin film transistor array substrate according to item 4 of the scope of patent application, wherein the half-tone photomask is a striped half-tone half-tone mask or a dot-shaped half-tone mask. Thousands of seven styles nine mask shoulders 6. The manufacturing method of the thin film transistor array substrate described in item 丨 of the patent application 'wherein the method of forming the flat layer includes: forming a dielectric layer; forming a patterned photoresist layer on On the dielectric layer, the patterned photoresist layer has a plurality of second openings and a plurality of fourth openings. The third openings are located above the electrodes and the fourth openings are located on the bonding pads. The patterned photoresist layer in the daylight region has a third thickness, and the patterned photoresist layer in the pad region has a fourth thickness, and the third thickness is greater than the fourth thickness. Thickness; using the patterned photoresist layer as a mask, removing the dielectric layer not covered by the patterned photoresist layer to form the stratum layer; and removing the patterned photoresist layer. 7. The method of manufacturing a thin film transistor array substrate according to item 6 of the scope of patent application, wherein the method of forming the patterned photodandelion layer includes: forming a photoresist material layer on the dielectric layer; and 200522168 The photoresist material layer is subjected to a pass using a half-tone mask to form the patterned photoresist layer. Which 70 ash 8. The method for manufacturing a thin film transistor array beauty as described in item 7 of the scope of the patent application, wherein the half-tone photomask is a striped half-tone photomask, a clay half-tone photomask, or a dot-shaped half-tone photomask. . 9. The method for manufacturing a thin film transistor array as described in item 8 of the scope of patent application, wherein the method for forming the patterned photoresist layer includes: forming a photoresist material layer on the dielectric layer; and forming the pattern The photoresist layer is subjected to a plurality of exposure processes for the photoresist material layer. • 10 · The method for manufacturing a thin film transistor array substrate according to item 丨 of the patent application scope, wherein the method for forming the flat layer includes: forming a photosensitive dielectric layer; and performing the photosensitive dielectric layer a plurality of times An exposure process is performed to form the flat layer. 11 · A method for manufacturing a thin film transistor array substrate, including: a substrate for a substrate having a pixel area and a solder pad area, and forming a plurality of scanning wirings and a plurality of gates on the day pixel area Poles, and a plurality of first pads are formed in the pad area, and the gates and the first pads are respectively electrically connected to the scanning wirings; a gate dielectric layer is formed on the substrate to cover Hold the scan wirings and the gates; Μ form a plurality of channel layers on the gate dielectric layer, and the positions of the channel layers correspond to the positions of the gates; 12028twf.ptd Page 23 200522168 VI. Scope of patent application A source and a drain are formed on each of these channel layers, a plurality of data wirings are formed in the pixel area, and a plurality of data wirings are formed in the pad area. The second pads, the sources and the second pads are respectively electrically connected to the data wirings, and the gates, the channel layers, the sources, and the ^ electrodes constitute a majority A thin pseudo-transistor; forming a protective layer over the substrate; forming a flat layer on the protective layer, the flat layer having a plurality of openings and a plurality of second openings, the first openings are located in the drains Above the electrodes, the second openings are located above the first pads and the first pads, wherein the flat layer located in the day zone has a first thickness, and the flat layer located in the pad zone is The layer has a second thickness, and the first series is larger than the second thickness; a. Using the flat layer as a mask, remove the material layers exposed by the first openings and the second openings until exposed The drain electrodes, the first pads, and the second pads And forming a plurality of pixel electrodes and a plurality of electrode material layers on the flat layer, wherein the drain electrodes are electrically connected to the pixel electrodes, the electrode material layers are connected to the first pads and The second pads are electrically connected. 1 2 · The method for manufacturing a thin film transistor array substrate according to item 丨 丨 of the patent application, wherein before removing the material layers exposed by the first openings and the second openings, The first thickness is between 2 and 6 microns. The second thickness of the flat layer is between 0. 3 and 1. 4 microns. 1 3 · The method for manufacturing a thin film transistor array substrate according to item 11 of the scope of patent application, wherein the first openings and the second openings are removed m 12028twf.ptd Page 24 200522168 After the exposed material layer, the second thickness of the flat layer is less than 0.8 μm. 1 4 · The method for manufacturing a thin film transistor array substrate as described in the first paragraph of the patent application, wherein the method for forming the flat layer includes: forming a photosensitive dielectric layer; and using a half-tone mask to the photosensitive dielectric substrate. The electrical layer is subjected to an exposure process. ^ 1 5 · The method for manufacturing a thin film transistor array substrate as described in item 4 of the patent application scope, wherein the half-tone mask is a stripe half-tone mask, a mesh half-tone mask, or a dot-shaped half-tone light cover. 1 6 · The method for manufacturing a thin film transistor array substrate according to item 丨 丨 in the scope of patent application, wherein the method for forming the flat layer includes: forming a dielectric layer from soil; forming a patterned photoresist layer on the dielectric On the layer, the patterned photoresist layer has a plurality of third openings and a plurality of fourth openings, the third openings ^ are located above the drain electrodes, and the fourth openings are located between the first pads and the Above the second pads, the patterned photoresist in the pixel area has a third thickness, and the patterned photoresist layer in the pad area has a fourth thickness and the third The thickness is greater than the fourth thickness; using the patterned photoresist layer as a mask, removing the dielectric layer not covered by the patterned photoresist sound to form the flat layer; and removing the Patterned photoresist layer. 1 7 · The method for manufacturing a thin film transistor array substrate according to item 16 of the scope of patent application, wherein the method for forming the patterned photoresist layer includes: 12028twf.ptd Page 25 200522168 VI. Scope of patent application '"' ''-forming a photoresist material layer on the dielectric layer; and using a half-tone mask to perform an exposure process on the photoresist material layer to The patterned photoresist layer is formed. 18 · The method for manufacturing a thin film transistor array substrate according to item 17 in the scope of patent application, wherein the half-tone photomask is a striped half-tone photomask, a mesh half-tone photomask, or a dot-shaped half-tone photomask . 19 · The method for manufacturing a thin film transistor array substrate according to item 18 of the scope of patent application, wherein the method for forming the patterned photoresist layer includes: forming a photoresist material layer on the dielectric layer; and The photoresist material layer is subjected to multiple exposure processes to form the patterned photoresist layer. 2 0 · The method for manufacturing a thin film transistor array substrate as described in the 11th member of the scope of patent application, wherein the method for forming the flat layer includes: · forming a photosensitive dielectric layer; and ^ the photosensitive dielectric layer A plurality of exposure processes are performed to form the flat layer. ‘ 12028twf.ptd