TWI462168B - Integrated circuit with seal ring and forming method thereof - Google Patents
Integrated circuit with seal ring and forming method thereof Download PDFInfo
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- TWI462168B TWI462168B TW098111351A TW98111351A TWI462168B TW I462168 B TWI462168 B TW I462168B TW 098111351 A TW098111351 A TW 098111351A TW 98111351 A TW98111351 A TW 98111351A TW I462168 B TWI462168 B TW I462168B
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Description
本發明為一種半導體裝置，特別是一種具有晶片封圈(seal ring)的半導體裝置。The present invention is a semiconductor device, and more particularly a semiconductor device having a wafer seal.
在製造半導體裝置時，晶圓在製程完畢後要切割成裸晶(die)，並封裝成晶片(chip)。而這其中最重要的就是要避免晶片中的裸晶受潮，而造成晶片失效或效能降低。習知的一個方法是以金屬形成的晶片封圈(seal ring)，將裸晶包圍起來，用以防止受潮。但晶片在製造過程中可能會因為製造機器所產生的磁場而產生感應電流，造成晶片封圈燒毀，使得晶片的良率降低。When manufacturing a semiconductor device, the wafer is cut into a die after the process is completed, and packaged into a chip. The most important of these is to avoid the dampness of the bare crystal in the wafer, resulting in wafer failure or performance degradation. One conventional method is to seal the bare crystal with a seal ring formed of metal to prevent moisture. However, during the manufacturing process, the wafer may generate an induced current due to the magnetic field generated by the manufacturing machine, causing the wafer seal to burn and the yield of the wafer to be lowered.
本發明的一實施例為一種具有晶片封圈的積體電路，包括一積體電路以及一晶片封圈。該晶片封圈包圍該積體電路，包括一導電封圈以及一電阻層。該電阻層形成於導電封圈的一缺口，使該晶片封圈的電阻值不等於零。利用該電阻層就可以避免晶片封圈因為製造中機器所產生的磁場通過該晶片封圈產生過大的感應電流，而將封圈燒毀。An embodiment of the invention is an integrated circuit having a wafer seal, comprising an integrated circuit and a wafer seal. The wafer sealing ring surrounds the integrated circuit, and includes a conductive sealing ring and a resistance layer. The resistive layer is formed in a gap of the conductive sealing ring such that the resistance of the wafer sealing ring is not equal to zero. By using the resistive layer, the wafer seal can be prevented from being burnt due to excessive magnetic induction current generated by the machine in the manufacturing process through the wafer seal.
本發明的另一實施例提供一種具有晶片封圈的積體電路的形成方法，包括：形成一積體電路於一基板上；形成一晶片封圈，圍繞該積體電路，其中該晶片封圈具有一缺口；以及形成一電阻層於該缺口。Another embodiment of the present invention provides a method of forming an integrated circuit having a wafer sealing ring, comprising: forming an integrated circuit on a substrate; forming a wafer sealing ring surrounding the integrated circuit, wherein the wafer sealing ring Having a gap; and forming a resistive layer in the gap.
下文所討論者為本發明所揭露之較佳實施例。雖然本說明書在基於本發明之精神以下列實施例說明，但是並非用以限制本發明為該等實施例。本發明所舉之實施例僅用以為本說明書之舉例說明使用，並非用以限制本發明之觀點。The following discussion is a preferred embodiment of the invention. While the present invention has been described in the following examples, the invention is not intended to limit the invention. The embodiments of the present invention are intended to be illustrative only and not to limit the scope of the present invention.
第1圖為根據本發明之具有晶片封圈的積體電路的一實施例的示意圖。晶片封圈包含了導電封圈(conductive ring)12與電阻層13，用以圍繞一積體電路11。在本實施例中，積體電路11可以替換為任何相類似的半導體裝置。在本實施例中，電阻層13可能為N型井(N well)、P型井(P well)、N型重掺雜多晶矽(N+ Poly)或P型重掺雜多晶矽(P+ Poly)。利用該電阻層13就可以避免晶片封圈因為製造中機器所產生的磁場通過該晶片封圈產生過大的感應電流，而將封圈燒毀。要注意的是本實施例中，晶片封圈僅以一個電阻層13為例說明，但可將晶片封圈分為複數個不連續的段，再以電阻層形成且電性連接於每兩段導體封圈之間，使的晶片封圈的電阻值增加，可承受更大的感應電流。Figure 1 is a schematic illustration of an embodiment of an integrated circuit having a wafer seal in accordance with the present invention. The wafer seal includes a conductive ring 12 and a resistive layer 13 for surrounding an integrated circuit 11. In the present embodiment, the integrated circuit 11 can be replaced with any similar semiconductor device. In this embodiment, the resistive layer 13 may be an N-well, a P-well, an N-type heavily doped polysilicon (N+Poly), or a P-type heavily doped polysilicon (P+Poly). By using the resistive layer 13, it is possible to avoid the wafer encapsulation which burns the seal ring because the magnetic field generated by the machine during manufacture generates an excessive induced current through the wafer seal. It should be noted that in the embodiment, the wafer sealing ring is exemplified by only one resistive layer 13 , but the wafer sealing ring can be divided into a plurality of discrete segments, and then formed by a resistive layer and electrically connected to each of the two segments. Between the conductor seals, the resistance of the wafer seal is increased to withstand a larger induced current.
第2圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。與第1圖不同處在於電阻層21是形成於導電封圈12的缺口的一側。電阻層21的長度大於導電封圈12的缺口的長度，並與導電封圈12電性連接。在另一實施例中，電阻層21可形成於導電封圈12的缺口的一側。利用該電阻層21就可以避免晶片封圈因為製造中機器所產生的磁場通過該晶片封圈產生過大的感應電流，而將封圈燒毀。要注意的是本實施例中，晶片封圈僅以一個電阻層21為例說明，但可將晶片封圈分為複數個不連續的段，再以電阻層形成且電性連接於每兩段導體封圈之間，使的晶片封圈的電阻值增加，可承受更大的感應電流。Figure 2 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention. The difference from FIG. 1 is that the resistance layer 21 is formed on one side of the notch of the conductive sealing ring 12. The length of the resistive layer 21 is greater than the length of the notch of the conductive sealing ring 12 and is electrically connected to the conductive sealing ring 12. In another embodiment, the resistive layer 21 can be formed on one side of the notch of the conductive seal 12. By using the resistive layer 21, it is possible to prevent the wafer encapsulation from burning due to the excessive magnetic field generated by the machine in the manufacturing process by the magnetic field generated by the machine. It should be noted that in the embodiment, the wafer sealing ring is exemplified by only one resistive layer 21, but the wafer sealing ring can be divided into a plurality of discontinuous segments, and then formed by a resistive layer and electrically connected to each of the two segments. Between the conductor seals, the resistance of the wafer seal is increased to withstand a larger induced current.
第3圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。與第2圖相比，第3圖的晶片封圈增加了一個非導電部32，形成於該缺口的另一側，用以使晶片封圈能更有效的防止濕氣進入，避免積體電路11受潮。因為非導電部32並不會導電，因此可以與導電封圈12緊密連接。在本實施例中，非導電部32與電阻層31的位置僅以第3圖的位置為例說明，並非用以限制本發明於此。再另一實施例中，非導電部32可以設置在導電封圈12的缺口內。Figure 3 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention. Compared with FIG. 2, the wafer sealing ring of FIG. 3 has a non-conductive portion 32 formed on the other side of the notch for making the wafer sealing ring more effective in preventing moisture from entering, and avoiding the integrated circuit. 11 damp. Since the non-conductive portion 32 does not conduct electricity, it can be closely connected to the conductive sealing ring 12. In the present embodiment, the positions of the non-conductive portion 32 and the resistive layer 31 are only described by taking the position of FIG. 3 as an example, and are not intended to limit the present invention thereto. In still another embodiment, the non-conductive portion 32 can be disposed within the gap of the conductive seal 12.
第4圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。與第3圖相比，第4圖的晶片封圈增加了一個導電部42，形成於該缺口的另一側，用以使晶片封圈能更有效的防止濕氣進入，避免積體電路11受潮。因為導電部42會導電，因此不可以與導電封圈12電性連接，必需與導電封圈12保持一預定距離，否則導電部42一但與導電封圈12電性連接，就會造成電阻層41失效。在本實施例中，導電部42與導電封圈12是由相同的材料所形成。在本實施例中，導電部42與電阻層41的位置僅以第4圖的位置為例說明，並非用以限制本發明於此。Figure 4 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention. Compared with FIG. 3, the wafer sealing ring of FIG. 4 has a conductive portion 42 formed on the other side of the notch for making the wafer sealing ring more effective in preventing moisture from entering, thereby avoiding the integrated circuit 11 Get wet. Because the conductive portion 42 is electrically conductive, it cannot be electrically connected to the conductive sealing ring 12, and must be kept at a predetermined distance from the conductive sealing ring 12. Otherwise, the conductive portion 42 is electrically connected to the conductive sealing ring 12, thereby causing a resistance layer. 41 failed. In the present embodiment, the conductive portion 42 and the conductive sealing ring 12 are formed of the same material. In the present embodiment, the positions of the conductive portion 42 and the resistive layer 41 are only described by taking the position of FIG. 4 as an example, and are not intended to limit the present invention thereto.
第5圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。第5圖中，電阻層51形成於導電封圈12的缺口內。此外，第5圖的晶片封圈增加了一個非導電部52，形成於導電封圈12的缺口的內側，用以使晶片封圈能更有效地防止濕氣進入，避免積體電路11受潮。因為非導電部52並不會導電，因此可以與導電封圈12緊密連接。在本實施例中，非導電部52與電阻層51的位置僅以第5圖的位置為例說明，並非用以限制本發明於此。Figure 5 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention. In FIG. 5, the resistance layer 51 is formed in the notch of the conductive sealing ring 12. In addition, the wafer sealing ring of FIG. 5 adds a non-conductive portion 52 formed on the inner side of the notch of the conductive sealing ring 12 for the purpose of making the wafer sealing ring more effective in preventing moisture from entering and preventing the integrated circuit 11 from being wetted. Since the non-conductive portion 52 does not conduct electricity, it can be closely connected to the conductive sealing ring 12. In the present embodiment, the positions of the non-conductive portion 52 and the resistive layer 51 are only described by taking the position of FIG. 5 as an example, and are not intended to limit the present invention thereto.
第6圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。第6圖中，電阻層61形成於導電封圈12的缺口內。此外，第6圖中的晶片封圈增加了一導電部62，設置於導電封圈12的缺口的內側，用來使晶片封圈能更有效地防止濕氣進入，避免積體電路11受潮。因為導電部62會導電，因此不可以與導電封圈12電性連接，必需與導電封圈12保持一預定距離，否則導電部62一但與導電封圈12電性連接，就會造成電阻層61失效。在本實施例中，導電部62與導電封圈12是由相同的材料所形成。在本實施例中，導電部62與電阻層61的位置僅以第6圖的位置為例說明，並非用以限制本發明於此。Figure 6 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention. In FIG. 6, the resistance layer 61 is formed in the notch of the conductive sealing ring 12. In addition, the wafer sealing ring in FIG. 6 is provided with a conductive portion 62 disposed on the inner side of the notch of the conductive sealing ring 12 for making the wafer sealing ring more effective in preventing moisture from entering and preventing the integrated circuit 11 from being wetted. Because the conductive portion 62 is electrically conductive, it cannot be electrically connected to the conductive sealing ring 12, and must be kept at a predetermined distance from the conductive sealing ring 12. Otherwise, the conductive portion 62 is electrically connected to the conductive sealing ring 12, thereby causing a resistance layer. 61 failed. In the present embodiment, the conductive portion 62 and the conductive sealing ring 12 are formed of the same material. In the present embodiment, the positions of the conductive portion 62 and the resistive layer 61 are only described by taking the position of FIG. 6 as an example, and are not intended to limit the present invention thereto.
第7圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。在本實施例中，電阻層71位於晶片封圈的一個角落。第7圖中的晶片封圈增加了一導電部72來使晶片封圈能更有效地防止濕氣進入，避免積體電路11受潮。在本實施例中，導電部72是以一定的角度設置在晶片封圈的左下角。再者，因為導電部72會導電，因此不可以與導電封圈12電性連接，導電部72的兩端必需與導電封圈12保持一預定距離，否則導電部72一但與導電封圈12電性連接，就會造成電阻層71失效。在本實施例中，導電部72與導電封圈12是由相同的材料所形成。Figure 7 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention. In this embodiment, the resistive layer 71 is located at one corner of the wafer seal. The wafer sealing ring in Fig. 7 adds a conductive portion 72 to make the wafer sealing ring more effective in preventing moisture from entering, and to prevent the integrated circuit 11 from being wetted. In the present embodiment, the conductive portion 72 is disposed at a lower angle to the lower left corner of the wafer seal at a certain angle. Moreover, since the conductive portion 72 is electrically conductive, it cannot be electrically connected to the conductive sealing ring 12. Both ends of the conductive portion 72 must be kept at a predetermined distance from the conductive sealing ring 12, otherwise the conductive portion 72 and the conductive sealing ring 12 Electrical connection will cause the resistive layer 71 to fail. In the present embodiment, the conductive portion 72 and the conductive sealing ring 12 are formed of the same material.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
11．．．積體電路11. . . Integrated circuit
12．．．導電封圈12. . . Conductive seal
13、21、31、41、51、61、71．．．電阻層13, 21, 31, 41, 51, 61, 71. . . Resistance layer
32、52．．．非導電部32, 52. . . Non-conductive part
42、62、72．．．導電部42, 62, 72. . . Conductive part
第1圖為根據本發明之具有晶片封圈的積體電路的一實施例的示意圖。Figure 1 is a schematic illustration of an embodiment of an integrated circuit having a wafer seal in accordance with the present invention.
第2圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。Figure 2 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention.
第3圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。Figure 3 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention.
第4圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。Figure 4 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention.
第5圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。Figure 5 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention.
第6圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。Figure 6 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention.
第7圖為根據本發明之具有晶片封圈的積體電路的另一實施例的示意圖。Figure 7 is a schematic illustration of another embodiment of an integrated circuit having a wafer seal in accordance with the present invention.
11．．．積體電路11. . . Integrated circuit
12．．．導電封圈12. . . Conductive seal
13．．．電阻層13. . . Resistance layer
Claims (25)
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| Application Number | Priority Date | Filing Date | Title |
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| TW098111351A TWI462168B (en) | 2009-04-06 | 2009-04-06 | Integrated circuit with seal ring and forming method thereof |
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|---|---|---|---|
| TW098111351A TWI462168B (en) | 2009-04-06 | 2009-04-06 | Integrated circuit with seal ring and forming method thereof |
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| TW201037760A TW201037760A (en) | 2010-10-16 |
| TWI462168B true TWI462168B (en) | 2014-11-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004086492A1 (en) * | 2003-03-25 | 2004-10-07 | Dow Corning Toray Co. Ltd. | Semiconductor device and method of manufacturing thereof |
| TW200518267A (en) * | 2003-11-25 | 2005-06-01 | Airoha Tech Corp | Integrated circuit chip |
| TWI300604B (en) * | 2004-01-26 | 2008-09-01 | Yamaha Corp | Semiconductor substrate |
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2009
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004086492A1 (en) * | 2003-03-25 | 2004-10-07 | Dow Corning Toray Co. Ltd. | Semiconductor device and method of manufacturing thereof |
| TW200518267A (en) * | 2003-11-25 | 2005-06-01 | Airoha Tech Corp | Integrated circuit chip |
| TWI300604B (en) * | 2004-01-26 | 2008-09-01 | Yamaha Corp | Semiconductor substrate |
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