TWI462084B - Switch circuit, pixel element and display panel using the same - Google Patents

Description

Switch circuit and its pixel component and display panel

The present invention relates to a switching circuit and a pixel element thereof and a display panel, and more particularly to a pixel element capable of realizing a high aperture ratio or a high resolution, a display panel thereof and a control method thereof.

In order to increase the value of display devices such as liquid crystal displays (LCDs), a technique of memory in pixel (MIP) is used in various fields of application. MIPs, for example, can be used to reduce the power consumption of various display devices, such as reflective or non-reflective LCDs.

MIPs come in different styles. According to the same number of bits, compared with the static random access memory (SRAM) type of MIP, the dynamic random access memory (DRAM) type of MIP is required. The number of circuit components is small. In other words, compared to the MIP of the SRAM type, the MIP of the DRAM type, such as self-refreshing in pixel type MIP (SRP-MIP), has a low circuit complexity and an aperture ratio of penetration (Aperture) Ratio) is higher. It can be seen that the DRAM-based MIP is suitable for display devices requiring a high aperture ratio, or for display devices requiring high resolution such as pixels per inch (PPI).

Most MIPs use memory to maintain the grayscale of the MIP, eliminating the need for new data from the source driver, thus reducing power consumption. Such a memory is, for example, a capacitor for storing the state of the image data storage capacitor containing image data. When the state of the image data storage capacitor is remembered After the memory, the image data of the image data storage capacitor can be updated or maintained according to the state.

However, for MIP, the memory layout area reduces the transparency or penetration area of the entire pixel area. As a result, the aperture ratio and resolution of the display device will be affected. Due to the inverse relationship between the aperture ratio and the resolution, if the display device requires high resolution, the aperture ratio will decrease, and may even be reduced to an unacceptable level.

The invention relates to a switching circuit and a pixel element thereof and a display panel, which can realize a high aperture ratio or a high resolution.

According to an aspect of the invention, a switching circuit is proposed for a pixel element. The switching circuit includes a first switch and a second switch. The first switch is used to be turned on to perform a sampling operation on the pixel element. The second switch has a control end coupled to the image data storage capacitor of the pixel element via the first switch, and a first data end coupled to the source line corresponding to one of the pixel elements; the second data end Used to couple to the image data storage capacitor. When the sampling operation is performed, the second switch is used to store the image data in the image data storage capacitor in the stray gate capacitance of its control terminal. From the sampling operation to the update operation in which the pixel element is updated, the image data stored by the second switch is held by the stray gate capacitance. The second open relationship selectively electrically connects the first data end and the second data end to each other according to the image data stored in the stray gate capacitance.

According to another aspect of the present invention, a pixel element is proposed for a display panel. The pixel components include image data storage capacitors, gate switches, and A switch, a second switch, and a third switch. The image data storage capacitor is used to store image data. The gate switch has a control end coupled to the corresponding gate line, and two data ends coupled between the corresponding source line and the image data storage capacitor. The first switch has a control end to receive the sampling control signal. The second switch has a control end coupled to the image data storage capacitor via the first switch. The first data end is coupled to a corresponding source line of the pixel element. The second data end is coupled to the image data storage capacitor. The third switch has a control end for receiving the update control signal, and the two data ends are coupled between the second switch and the image data storage capacitor. The first open relationship is turned on to perform a sampling operation on the pixel element, and the third open relationship is turned on to perform an update operation on the pixel element. When the sampling operation is performed, the second switch is used to store the image data in the image data storage capacitor in the stray gate capacitance of its control terminal. From the sampling operation to the update operation, the image data stored by the second switch is held due to the stray gate capacitance. The second open relationship selectively electrically connects the first data end and the second data end to each other according to the image data stored in the stray gate capacitance.

According to another aspect of the present invention, a display panel is provided that includes an active matrix pixel array, a source driver, and a gate driver. The active matrix pixel array includes a plurality of gate lines, a plurality of source lines, and a plurality of pixel elements. The source driver is used to drive the source line. The gate driver is used to drive the gate line. The pixel elements are arranged in a matrix. Each pixel component includes an image data storage capacitor, a gate switch, a first switch, a second switch, and a third switch. The image data storage capacitor is used to store image data. The gate switch has a control end coupled to the corresponding gate line, and two data ends coupled between the corresponding source line and the image data storage capacitor. The first switch has a control end to receive the sampling control signal. The second switch has a control end coupled to the image via the first switch Data storage capacitor. The first data end is coupled to a corresponding source line of the pixel element. The second data end is coupled to the image data storage capacitor. The third switch has a control end for receiving the update control signal, and the two data ends are coupled between the second switch and the image data storage capacitor. The first open relationship is turned on to perform a sampling operation on the pixel element, and the third open relationship is turned on to perform an update operation on the pixel element. When the sampling operation is performed, the second switch is used to store the image data in the image data storage capacitor in the stray gate capacitance of its control terminal. From the sampling operation to the update operation, the image data stored by the second switch is held due to the stray gate capacitance. The second open relationship selectively electrically connects the first data end and the second data end to each other according to the image data stored in the stray gate capacitance.

In order to provide a better understanding of the above and other aspects of the present invention, the preferred embodiments of the present invention are described in detail below.

Embodiments of the switching circuit and its pixel elements and display panel are disclosed below. In some embodiments, in order to achieve a high aperture ratio or a high resolution such as a pixel per inch (PPI), the stray gate capacitance present in the switch is regarded as a sampling capacitor and is applied to the update picture. In the process of memory in pixel (MIP). Further explanations are provided below in conjunction with the relevant figures.

Please refer to FIG. 1 , which is a block diagram showing an example of a display panel. The display panel 100 includes at least an active matrix pixel array 110, a gate driver 120, and a source driver 130. The display panel 100 can be applied, for example, in a display device. The active matrix pixel array 110 includes a plurality of gate lines G1-Gn and Multiple source lines D1-Dm. The gate driver 120 drives the gate lines G1-Gn. The source driver 130 drives the source lines D1-Dm. The active matrix pixel array 110 further includes a plurality of pixel elements arranged in a matrix. Each pixel element is coupled to a corresponding gate line and source line. Taking the pixel element P(x, y) as an example, it is located at a coordinate position defined by the corresponding source line Dx and the corresponding scanning line Gy. The pixel element P(x, y) is exemplified by an image data storage capacitor C and a gate switch T. The gate switch T has a control end coupled to the corresponding gate line Gy, and two data ends coupled between the corresponding source line Dx and the image data storage capacitor C. Under the control of the gate switch T, the image data storage capacitor C receives the image data from the corresponding source line Dx and stores it.

Please refer to FIG. 2A, which is a schematic diagram showing an example of a switch circuit according to an embodiment of the present invention. The switch circuit 210 is used, for example, in the pixel element P(x, y) of Fig. 1. The switch circuit 210 includes a first switch 211 and a second switch 212. The second switch 212 has a control terminal 212g and two data terminals 212s and 212d, which are, for example, a gate, a source and a 汲 terminal, respectively. The control terminal 212g is coupled to the end point Tg of the switch circuit 210 via the first switch 211. The end point Tg is, for example, an image data storage capacitor C connected to the pixel element P(x, y). The data end 212s is coupled to the end point Ts of the switch circuit 210. The terminal Ts is, for example, coupled to a corresponding source line Dx of the pixel element P(x, y). The data end 212d is coupled to the end point Td of the switch circuit 210. The terminal Td is, for example, connected to the image data storage capacitor C.

The first switch 211 is used to be turned on to perform a sampling operation on the pixel element P(x, y). When the sampling operation is performed, the second switch 212 can store the image data in the image data storage capacitor C in the stray gate capacitance of its control terminal 212g. For example, when the sampling operation is performed, the image data The pixel voltage of the storage capacitor C is applied to the control terminal 212g of the second switch 212 via the first switch 211 that is turned on. At this time, the stray gate capacitance existing on the control terminal 212g of the second switch 212 is used to maintain the bias voltage received by the control terminal 212g. This means that in the sampling operation, the image data of the image data storage capacitor C can be stored in the second switch 212 or, more specifically, in its stray gate capacitance. From the sampling operation to the update operation in which the pixel element P(x, y) is updated, the image data stored by the second switch 212 is held by the stray gate capacitance. The second switch 212 selectively electrically connects the two data ends 212s and 212d to each other according to the image data stored in the stray gate capacitance.

In other words, the second switch 212 exhibits not only the characteristics of the switch, but also the characteristics of the capacitive element or memory used to store the image data. Thus, when the switching circuit 210 is implemented in the pixel element P(x, y) to form the MIP, an additional memory layout area can be saved. Compared to the conventional MIP using memory or sampling capacitor, the MIP implemented by the pixel element P(x, y) disclosed herein can use fewer circuit components, thereby reducing circuit complexity. In this way, a high aperture ratio or high resolution can be achieved.

Please refer to FIG. 2B, which is a cross-sectional view showing an exemplary structure of a second switch of the switch circuit of FIG. 2A. In this example, the second switch 212 is exemplified by a thin film transistor, and the gate, drain, and source terminals 212g, 212d, and 212s are respectively gate, drain, and source electrodes 212GE, 212DE, and 212SE. To represent. In the second switch 212, the stray gate capacitance Cg is present on the control terminal 212g, and is a combination of a plurality of stray capacitances. For example, stray capacitance can be divided into dielectric capacitors such as gate-base capacitance Cgb, and fringe capacitors such as gate-drain capacitance Cgd and gate- Source capacitance Cgs. The gate-base capacitance Cgb is formed between the gate electrode 212GE and the dielectric layer 212DL. The dielectric layer 212DL separates the gate electrode 212GE from a poly-silicon layer such as the channel layer 212CL. The gate-drain capacitance Cgd is formed between the gate electrode 212GE and the gate electrode 212DE at the edge of the gate electrode 212GE. The gate-source capacitance Cgs is formed at the other edge of the gate electrode 212GE between the gate electrode 212GE and the source electrode 212SE.

Please refer to Figures 2A and 2B. In some examples, when the first switch 211 is turned on and the gate-source voltage Vgs is higher than the threshold voltage of the second switch 212, the surface of the channel layer 212CL will form an inversion layer due to the accumulation of electrons. Since the inversion layer is electrically conductive, the gate-base capacitance Cgb will have a high capacitance value. In other examples, when the first switch 211 is turned off, the disappearance of the inversion layer will cause the channel layer 212CL to lose conductivity, so the gate-base capacitance Cgb will have a low capacitance value.

In order for the second switch 212 to store image data, the stray gate capacitance Cg needs to have a sufficient capacitance value to maintain the gate-source voltage Vgs. In some implementations, the capacitance of the stray gate capacitance Cg is approximately between tens of femto, such as 40fF or 50fF, but the invention is not limited thereto, and the actual value may be determined by empirical or experimental results. . Since the gate-base capacitance Cgb is small when the first switch 211 is turned off, the gate-source voltage Vgs is maintained by the marginal capacitance such as the gate-drain capacitance Cgd and the gate-source capacitance Cgs. . Applicants have found that the magnitude of the capacitance of the gate-drain capacitance Cgd and the gate-source capacitance Cgs is related to various factors including at least the width of the channel layer 212CL, the depth De of the dielectric layer 212DL, or the dielectric value, and The layout area or size of the second switch 212. Therefore, by the above The adjustment of at least one factor enables a switch to have a stray capacitance sufficient to stably maintain the gate-source voltage Vgs.

Please refer to FIG. 3A, which illustrates a schematic diagram of a pixel element for a display panel according to an embodiment of the invention. By replacing the pixel element P(x, y) of FIG. 1 with the pixel element P(x, y) of FIG. 3A, the display panel of the present invention can be realized, so the detailed schematic diagram is for the sake of brevity. Omitted. In Fig. 3A, the pixel element P(x, y) includes an image data storage capacitor C and a gate switch T similar to those of Fig. 1. In this example, the image data storage capacitor C is exemplified by the composition of two capacitors, such as a liquid crystal capacitor Clc and a storage capacitor Cs.

The pixel element P(x, y) further includes a first switch 211, a second switch 212, and a third switch 213. The first switch 211 has a control terminal to receive the sampling control signal SAMPLE. The second switch has a control end 212g, and the control end 212g is coupled to the pixel electrode of the image data storage capacitor C (indicated by the end point PE) via the first switch 211. The second switch 212 further includes: a first data end coupled to the source line Dx corresponding to the pixel element P(x, y); and a second data end 212d coupled via the third switch 213 To the image data storage capacitor C. The third switch 213 has a control terminal for receiving the update control signal REFRESH, and two data terminals coupled between the second switch 212 and the image data storage capacitor C. In practice, the pixel element P(x, y) may be referred to as a MIP containing 4T, ie four switches, one of which (ie the second switch 212 in this example) has a switch and a capacitive element (or memory) Dual characteristics.

In the pixel element P(x, y), the stray gate capacitance is present at the control end of the second switch 212. At the time of design, the stray gate capacitance can be made to have a sufficiently large capacitance value to maintain the bias voltage received by the control terminal 212g. Therefore, from Looking at the control terminal 212g of the second switch 212 and the source line Dx, the second switch 212 can be regarded as an equivalent circuit of the switch and the capacitive element (or memory). In this way, additional memory between the control terminal 212g and the source line Dx can be omitted, thereby achieving high aperture ratio or high resolution.

In a practical example, in order to achieve a high aperture ratio, the switches 211, 212, 213 are designed, for example, to a minimum acceptable size. At this time, since the second switch 212 can be used as a switch and can function as a capacitive element, the physical structure of the second switch 212 is different from the first switch 211 and the third switch 213. That is to say, at the time of design, the stray gate capacitance value of the second switch 212 can be made larger than the stray gate capacitance value of the first switch 211 and the third switch 213, but still smaller than the image data storage capacitor C.

In some embodiments, the switches 211, 212, 213 can be implemented as thin film transistors, as shown in FIG. 2B. In this embodiment, the second switch 212 has a channel layer such as the channel layer 212CL of FIG. 2B, the width of which is greater than the channel layer width of the first switch 211 or the third switch 213. In other words, referring to FIG. 2B, the channel layer 212CL can extend its width from a certain direction such as the direction of entering or exiting the paper surface, and the gate electrode 212GE is also the same. In other embodiments, the second switch 212 has a dielectric layer such as the dielectric layer 212DL of FIG. 2B, the depth of which is greater than the dielectric layer depth of the first switch 211 or the third switch 213. In other embodiments, the second switch 212 has a dielectric layer such as the dielectric layer 212DL of FIG. 2B, and the permittivity is lower than the dielectric layer dielectric constant of the first switch 211 or the third switch 213. . In other embodiments, the layout area of the second switch 212 is larger than the layout area of the first switch 211 or the third switch 213. In these embodiments, the marginal capacitance of the second switch 212, such as the gate-source capacitance Cgs or the gate-drain capacitance Cgd, is A large capacitance value is used to ensure that the control terminal bias of the second switch 212 is maintained.

Referring to FIG. 3B, an example of a timing diagram of a plurality of signal waveforms for the pixel elements of FIG. 3A is shown. In this example, the sampling control signal SAMPLE, the gate control signal GATE, and the update control signal REFRESH are sequentially enabled, so that the first switch 211, the gate switch T, and the third switch 213 are sequentially turned on, thereby The pixel element P(x, y) is subjected to a sampling operation, a precharge operation, and an update operation at different times. For the high or low binary image data, such as white or black, the pixel voltage Vpix of the pixel electrode PE of the image data storage capacitor C can be in two voltage states, such as the pixel voltage Vpix representing the high image data (white). ), or the pixel voltage Vpix (black) representing the low-level image data. In this way, the sampling operation, the pre-charging operation, and the updating operation can sequentially perform the updating process of the image data storage capacitor C to maintain the image data in the original state.

More specifically, the update process of the pixel element P(x, y) will be described below in conjunction with the signal waveform of FIG. 3B, and the pixel voltage Vpix(white) of the high-order image data is taken as an example. First, before the sampling period of FIG. 3B, the pixel voltage Vpix (white) is initially, for example, 5 V, and the common voltage Vcom is initially 0 V, for example. Next, referring to the sampling period, the sampling control signal SAMPLE is enabled to turn on the first switch 211, so the control terminal 212g of the second switch 212 is biased at 5V as indicated by the voltage 212g (white). The voltage 212g (white) on the control terminal 212g is maintained due to the stray gate capacitance between 212g and 212s across the second switch 212. As such, during sampling, the second switch 212 behaves like a capacitor to store image data.

Next, reference is made to the precharge period of FIG. 3B. The gate control signal GATE is enabled to turn on the gate switch T at a high level. Update data signal SOURCE is enabled at a high level, such as 5V. Via the turned-on gate switch T, the 5V update data signal SOURCE is used to maintain the 5V pixel voltage Vpix at 5V, and the common voltage Vcom is inverted at this time. Therefore, the image data storage capacitor C is electrically neutralized, that is, its voltage across is 0V. Furthermore, the source data signal SOURCE will transition from a low level to a high level. Via the stray gate capacitance of 212g and 212s across the second switch 212, the voltage 212g (white) on the control terminal 212g changes with the source data signal SOURCE. Therefore, during pre-charging, the voltage 212g (white) will be pushed up to about 10V.

Thereafter, the update period of FIG. 3B is referred to. The update control signal REFRESH is enabled at a high level to turn on the third switch 213. At this time, during the update, the voltage 212g (white) is pulled down to about 5V. Since the voltage between the two ends 212s and 212g is higher than the threshold voltage of the second switch 212, the level of the voltage 212g (white) at this time is still sufficient to turn on the second switch 212. In detail, since the voltage difference of 5V (212g(white)-SOURCE=5V-0V) is higher than the threshold voltage of 1V, the second switch 212 is turned on. Via the turned-on second switch 212 and the third switch 213, the 0V update data signal SOURCE is used to bias the pixel voltage Vpix to 5V. Thus, from the "Vpix (white), Vcom" = "5V, 0V" in the update period of the 3B picture and the "Vpix (white), Vcom" = "0V, 5V" during the sampling period, it is known that the image data will be It is updated and its polarity is reversed.

Similarly, "Vpix(black), Vcom" = "5V, 5V" during the update period of Fig. 3B and "Vpix(black), Vcom" = "0V, during the sampling period. 0V", it can be seen that the pixel voltage Vpix (black) of the low-order image data is also appropriately updated. The detailed update process of the pixel voltage Vpix (black) of the low-order image data should be made by those having ordinary knowledge. Inferred from the above description, it will not be repeated for the sake of brevity.

During operation of the pixel element P(x, y) described above, the second switch 212 can be considered or acted as a switching element and a capacitor for storing image data. Therefore, from the control terminal 212g of the second switch 212 and the source line Dx, the second switch 212 can be regarded as an equivalent circuit of the switch and the capacitive element (or memory). In this way, additional memory between the control terminal 212g and the source line Dx can be omitted, thereby achieving high aperture ratio or high resolution.

Please refer to Figures 4A and 4B. 4A is a schematic diagram of a pixel element for a display panel in accordance with another embodiment of the present invention. Fig. 4B is a diagram showing an example of a timing chart of a plurality of signal waveforms for the pixel elements of Fig. 4A. The pixel element P(x, y) of FIG. 4A is different from the pixel element P(x, y) of FIG. 3A in that the two data terminals 212s and 212d of the second switch 212 are electrically connected to the gate. The two data terminals of the switch T. The signal waveform of Figure 4B differs from the signal waveform of Figure 3B in that the update control signal REFRESH is enabled during the update period. By using an appropriate control signal such as the control signal shown in FIG. 4B, the pixel element P(x, y) of FIG. 4A has similar characteristics to the pixel element of FIG. 3A, so it is not for the sake of brevity. Detailed description.

In the switch circuit of the above embodiment of the present invention and its pixel elements and display panel, the stray gate capacitance in the switch is used as the memory of the MIP. In this way, a high aperture ratio or high resolution can be achieved.

In summary, although the present invention has been disclosed above in the preferred embodiment, It is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧ display panel

110‧‧‧Active Matrix Element Array

120‧‧‧gate driver

130‧‧‧Source Driver

210‧‧‧Switch circuit

211, 212, 213‧‧ ‧ switch

212CL‧‧‧ channel layer

212g‧‧‧ control terminal

212s, 212d‧‧‧ data side

212DL‧‧‧ dielectric layer

212GE, 212DE, 212SE‧‧‧ electrodes

C‧‧·Image data storage capacitor

Clc‧‧ liquid crystal capacitor

Cs‧‧‧ storage capacitor

Cg‧‧‧ stray gate capacitance

Cgb‧‧‧ gate-base capacitance

Cgs‧‧‧ gate-source capacitance

Cgd‧‧‧gate-dip capacitor

D1-Dm‧‧‧ source line

De‧‧‧depth

GATE‧‧‧ gate control signal

G1-Gn‧‧‧ gate line

P(x,y)‧‧‧ pixel components

PE‧‧‧ pixel electrode

REFRESH‧‧‧Update control signal

SAMPLE‧‧‧Sampling Control Signal

SOURCE‧‧‧Update data signal

T‧‧‧ gate switch

Ts, Td, Tg‧‧‧ endpoints

Vcom‧‧‧Common voltage

Vgs, 212g (black), 212g (white) ‧ ‧ voltage

Vpix, Vpix (black), Vpix (white) ‧ ‧ pixel voltage

FIG. 1 is a block diagram showing an example of a display panel.

FIG. 2A is a schematic diagram showing an example of a switch circuit according to an embodiment of the invention.

2B is a cross-sectional view showing an exemplary structure of a second switch of the switch circuit of FIG. 2A.

FIG. 3A is a schematic diagram of a pixel element for a display panel according to an embodiment of the invention.

FIG. 3B is a diagram showing an example of a timing chart of a plurality of signal waveforms for the pixel elements of FIG. 3A.

4A is a schematic diagram of a pixel element for a display panel in accordance with another embodiment of the present invention.

Fig. 4B is a diagram showing an example of a timing chart of a plurality of signal waveforms for the pixel elements of Fig. 4A.

210‧‧‧Switch circuit

211, 212‧‧ ‧ switch

212g‧‧‧ control terminal

212s, 212d‧‧‧ data side

Ts, Td, Tg‧‧‧ endpoints

Vgs‧‧‧ voltage

Claims (17)

A switching circuit for a pixel component, comprising: a first switch for being turned on to perform a sampling operation on the pixel element; and a second switch having: a control terminal via the first switch An image data storage capacitor coupled to the pixel component; a first data terminal coupled to the source line corresponding to one of the pixel components; and a second data terminal coupled to the source The image data storage capacitor; wherein, when the sampling operation is performed, the second switch is configured to store the image data in the image data storage capacitor in the stray gate capacitance of the control end thereof, from the sampling operation to the drawing The element component is updated by an update operation, and the image data stored by the second switch is held by the stray gate capacitance, and the second open relationship is selectively selected according to the image data stored in the stray gate capacitance. The first data end and the second data end are electrically connected to each other. The switch circuit of claim 1, wherein the second switch has a channel layer width greater than a channel layer width of the first switch. The switching circuit of claim 1, wherein the second switch has a dielectric layer depth greater than a dielectric layer depth of the first switch. The switching circuit of claim 1, wherein the dielectric property of the second switch is lower than the dielectric constant of the dielectric layer of the first switch. The switch circuit of claim 1, wherein a layout area of the second switch is larger than a layout area of the first switch. A pixel component for a display panel includes: an image data storage capacitor for storing image data; a gate switch having a control end coupled to a corresponding gate line, and two data terminals coupled Between a corresponding source line and the image data storage capacitor; and a first switch having a control terminal for receiving a sampling control signal; and a second switch having a control terminal coupled to the first switch The image data storage capacitor has a first data end coupled to the corresponding source line of the pixel element, a second data end coupled to the image data storage capacitor, and a third switch having a control end Receiving an update control signal, and the two data ends are coupled between the second switch and the image data storage capacitor; wherein the first open relationship is turned on to perform a sampling operation on the pixel element, and the third open relationship Turning on to perform an update operation on the pixel element; when the sampling operation is performed, the second switch is configured to store image data in the image data storage capacitor at a stray gate of the control terminal thereof The image data stored by the second switch is maintained by the stray gate capacitance according to the image data stored in the stray gate capacitance. The first data end and the second data end are electrically connected to each other. The pixel element of claim 6, wherein the second switch has a channel layer width greater than a channel layer width of the first switch. The pixel element of claim 6, wherein the second switch has a dielectric layer depth greater than a dielectric layer depth of the first switch. The switching circuit of claim 6, wherein the dielectric property of the second switch is lower than the dielectric constant of the dielectric layer of the first switch. The pixel element of claim 6, wherein a layout area of the second switch is larger than a layout area of the first switch. The pixel element of claim 6, wherein the two data ends of the second switch are electrically connected to the two data ends of the gate switch. A display panel includes: an active matrix pixel array comprising: a plurality of gate lines; a plurality of source lines; a plurality of pixel elements arranged in a matrix, each pixel element coupled to a corresponding gate line and The source line is characterized by each of the pixel elements as described in claim 6; a source driver for driving the source lines; and a gate driver for driving the gate lines. The display panel of claim 12, wherein the second switch has a channel layer width greater than a channel layer width of the first switch. The display panel of claim 12, wherein the second switch has a dielectric layer depth greater than a dielectric layer depth of the first switch. The display panel of claim 12, wherein a dielectric constant (permittivity) of the second switch is lower than the first opening The dielectric constant of the dielectric layer. The display panel of claim 12, wherein a layout area of the second switch is larger than a layout area of the first switch. The display panel of claim 12, wherein the two data ends of the second switch are electrically connected to the two data ends of the gate switch.