TWI458051B - Control Method of Vertical Double - gate Dynamic Random Access Memory - Google Patents

Description

Vertical double gate dynamic random access memory control method

The invention relates to a dynamic random access memory, in particular to a vertical double gate dynamic random access memory control method.

The continuous improvement of semiconductor process technology has greatly reduced the size of electronic components on the one hand, and greatly reduced the manufacturing cost of electronic components on the other hand. The semiconductor process technology used in the past years is limited to the formation of planar semiconductor structures by etching, ion cloth values, wiring, etc. on the substrate, and the minimum wafer size can reach 6F2. However, at present, such technologies tend to be flattened with the miniaturization of the feature size, and the area occupied by the semiconductor on the wafer cannot be significantly reduced. Thus, vertical (or three-dimensional) semiconductor process technology is gradually evolving, which reduces the area occupied by the transistor on the wafer surface by vertically growing the semiconductor on the wafer, and further The chip size is reduced to 4F2. DRAM arrays, vertical transistor structures and methods of forming transistor structure and DRAM Array, and "Folded bit line DRAM with vertical ultra thin body transistors", respectively, which are disclosed in U.S. Patent Publication No. 7,266,061, respectively. A vertical columnar transistor structure and a manufacturing method and process thereof, wherein a gate material is formed beside the columnar body to control the conduction of the columnar body used as the transistor No, it is usually to form a gate which is not in contact with each other and attached to the columnar body by etching the metal wire. However, as the feature size has dropped below 40 nanometers (nm), the way in which the metal lines are etched to form gates on both sides of the column is greatly challenged because of its thickness control. .

Therefore, "SEMICONDUCTOR DEVICE HAVING VERTICAL PILLAR TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME", which is disclosed in the U.S. Patent Publication No. 20090256187, discloses a gate which is provided only on one side of the columnar body, and is formed by etching the columnar body. a recess, and then a metal is formed in the recess to form a gate. Although it discloses a different manufacturing method from the prior art, it is difficult to control the thickness of the metal line by etching the metal line, but the same The gate must be etched to complete the gate arrangement, and the manner in which the pillars are etched to form the recesses is equally difficult.

The main object of the present invention is to solve the problem that the gate of the transistor is difficult to manufacture in the process technology in which the feature size is gradually reduced.

In order to achieve the above object, the present invention provides a method for controlling a vertical double gate dynamic random access memory, wherein the memory has a bit line disposed on a surface of a substrate, and a plurality of intervals are disposed on the bit line to form a plurality a columnar body accommodating the groove, a dielectric layer formed on the surface of the accommodating groove, and a plurality of gates disposed in the accommodating groove and separated from the columnar body by the dielectric layer, A plurality of the columnar bodies and a second columnar body are included in the plurality of columns, and the control method is:

When in a short circuit state, the gates on both sides of the first column body are defined as a first gate and a second gate, and the first gate and the second gate are controlled to be a turn-on voltage, so that the first The drains at both ends of a column are electrically connected to the source.

When in a clear state, the first gate and the second gate are controlled to clear a voltage, so that the drains at the two ends of the first column are electrically non-conductive, and the clear voltage is less than the turn-on voltage.

When in a pseudo open state, the gates defining the two sides of the second column are substantially the second gate and the third gate, so that the second gate and the third gate are electrically connected to each other, and the first gate is controlled. The gate has a cut-off voltage, and a pseudo open circuit is formed between the drain and the source at both ends of the first column, and the source and the drain of the two ends of the second column are electrically connected.

It can be seen from the above description that the source and the drain of the two ends of the column are electrically controlled by the two gates on both sides of the column, and therefore, the gates in the plurality of the recesses are controlled. The cutting separation is not required, and the etching process in the process with a small feature size can be avoided, and the problem that the gate separation process is not easy is solved. In addition, in the clear state, the two gates are controlled to clear the voltage, and the leakage current problem occurs when the short-circuit state transition state is the pseudo-open state, so as to improve the correctness of data reading.

The detailed description and technical contents of the present invention will now be described as follows:

Referring to FIG. 1 , the present invention is a vertical double gate dynamic random access memory control method. The memory has a bit line 20 disposed on a surface of a substrate 10 , and the plurality of intervals are set at a columnar body 30 of the plurality of accommodating recesses 31, a dielectric layer 40 formed on the surface of the accommodating recess 31, and a plurality of the recessed holes 31 are disposed in the accommodating recess 31 The columnar body 30 is separated from the gate 60 of the dielectric layer 40. The material of the substrate 10 and the columnar body 30 may be tantalum or niobium. The two ends of the columnar body 30 are respectively doped with a doping element to form a source or a drain. The doping element may be, for example, It is a 2A, 3A, 5A or 6A group element, but can be used as a P-type or N-type transistor, and there are many ways of forming the source/drainage method and the position, and it is not the focus of the present invention. This will not be explained in detail. The material of the dielectric layer 40 may be, for example, hafnium oxide, hafnium oxide, tantalum nitride or a high dielectric constant material. The gate 60 referred to in the present invention corresponds to the columnar body 30 used as a transistor, and the gate 60 is used to control the electrical conduction state of the columnar body 30, and the gate 60 is used. It is disposed in the accommodating recess 31 in a manner perpendicular to the bit line 20, and forms a checkerboard array with the bit line 20, and thus the gate 60 is used as a word line in the memory.

Referring to FIG. 2A to FIG. 2D, the method for fabricating the dynamic random access memory of the present invention is as follows: a plurality of the columns 30 are formed on the bit line 20 of the substrate 10, and the The plurality of columnar bodies 30 are spaced apart from each other to form a plurality of the accommodating recesses 31. The bit lines 20 may be formed on the surface of the substrate 10 by embedding metal wires, or may be formed by ion diffusion. The surface of the substrate 10, as shown in FIG. 2B, forms a dielectric layer 40 on the surface of the receiving recess 31, and then sets the plurality of gates 60 to the receiving recesses as shown in FIG. 2C. 31, finally, as shown in FIG. 2D, the capacitive element 50 is formed at one end of the columnar body 30 away from the substrate 10, and the capacitive element 50 shown in FIG. 2D is merely illustrative, and does not represent direct A capacitive element 50 is disposed on the columnar body 30. In addition, the gate 60 disposed in the accommodating recess 31 is not separated by etching, but is separated from the adjacent columnar bodies 30 by the dielectric layer 40, and is transmitted through the following control method. , to achieve the effect of the transistor on or off.

Please refer to "FIG. 3A" to "FIG. 3C" to define a plurality of adjacent first columnar bodies 30a and a second columnar body 30b in the columnar body 30, and the present invention For example, the gates 60 on both sides of the first column 30a are respectively a first gate 60a and a second gate 60b, and the two sides of the second column 30b are respectively the second a gate 60b and a third gate 60c, the second gate 60b being adjacent to the first column 30a and the second column 30b, respectively, in other words, the second gate 60b is disposed Between the first columnar body 30a and the second columnar body 30b. The control method of the present invention is:

When the first column 30a is in a short-circuit state, the first gate 60a and the second gate 60b are controlled to be a turn-on voltage Von. As shown in FIG. 3A, the first column is made. The drains of the two ends of the 30a are electrically connected to the source to perform charge access of the capacitive element 50 connected to the first column 30a. In this embodiment, the first column 30a and the second The columnar body 30b is an N-type transistor doped with N-type ions at both ends, and thus the on-voltage Von is a positive voltage. Since the drain and the source of the first columnar body 30a are electrically connected, the bit line 20 can obtain the charge of the capacitor element 50 connected to the first columnar body 30a through the first columnar body 30a. Store or read.

Since the reading mode in the dynamic random access memory is continuous and read or written one by one, after the first column 30a has completed reading and writing signals, the second column 30b is performed. Reading and writing, as shown in FIG. 3B, the second gate 60b and the third gate 60c are at the turn-on voltage Von, so that the source and the drain of the second column 30b are electrically connected. Turning on, and changing the first gate 60a to a cutoff voltage Voff, the first column 30a enters a pseudo open state. It should be noted that the pseudo open state referred to in the present invention refers to a columnar body. The gate 60 on both sides of the 30 has a turn-on voltage Von on one side and a turn-off voltage Voff on the other side. In the present embodiment, the turn-off voltage Voff is the opposite of the turn-on voltage Von, thus still making the ends of the column 30 The source and the drain are not electrically conductive, but the cutoff voltage Voff is not limited to the opposite of the turn-on voltage Von. When only one of the two sides of the column 30 is required to be the off voltage Voff, the non-conduction is not performed. The source and the drain of both ends of the columnar body 30 may be used. Returning to the embodiment of the present invention, when the first column 30a is switched from the short-circuit state to the pseudo-open state, the electrical transition delay time of the first gate 60a still causes the first column The body 30a exhibits a micro-conducting state, causing a problem of leakage current.

Please refer to FIG. 3C again. In order to solve the above problem, the present invention adds a clear state during the above transition state, and controls the first gate 60a and the second gate 60b during the transition state. a clearing voltage Vtran, such that the drain and the source of the first column 30a are electrically non-conductive, wherein the clear voltage Vtran is less than the turn-on voltage Von, the clear voltage Vtran can be equal to the cutoff voltage Voff, thus The first columnar body 30a is completely in an open state, and then the second gate 60b is adjusted to the turn-on voltage Von, so that the first columnar body 30a enters a pseudo open state, thereby avoiding occurrence of a transition state. The leakage current problem affects the reading of the signal. In addition, the clear voltage Vtran may be an average value of the turn-on voltage Von and the turn-off voltage Voff, and the source and the drain of the first column 30a may be prevented from being turned on. The first gate 60a is further adjusted to the cutoff voltage Voff, and the second gate 60b is adjusted to the turn-on voltage Von, so that the first columnar body 30a enters a pseudo open state, whereby the second gate 60b When the clear voltage Vtran jumps back to the turn-on voltage Von, it is not necessary to adjust the turn-off voltage Voff back to the turn-on voltage Von, and only the average value of the turn-off voltage Voff and the turn-on voltage Von jumps back to the turn-on voltage. Von has the advantage of faster reaction speed.

For example, the turn-on voltage Von is +2V (volts), the turn-off voltage Voff is -2V, and the clear voltage Vtran is 0V, so that the first pillar 30a is in the short-circuit state, the first gate is made Both the pole 60a and the second gate 60b are +2V, and then enter a clear state, so that the first gate 60a and the second gate 60b are both adjusted to 0V to avoid the ends of the first column 30a. The source and the drain are turned on, causing a problem of leakage current. Then, the first gate 60a is further adjusted to -2V, and the second gate 60b is adjusted to +2V to enter a pseudo open state, so that the source and the drain of the first column 30a are electrically non-conductive. . Finally, after the second column 30b also completes the signal reading, the second gate 60b is finally adjusted to -2V, that is, the first gate 60a and the second gate 60b are both cutoff voltages. Voff, at this point, it will enter the state of full open circuit.

In addition to the above-described manner in which the first columnar body 30a and the second columnar body 30b are designed as N-type transistors, the first columnar body 30a and the second columnar body 30b may be designed as P. In the case of the transistor, the on-voltage Von is a negative voltage, and the off-voltage Voff is a positive voltage, and the on-voltage Von and the off-voltage Voff are opposite to each other, that is, their absolute values are equal. The clear voltage Vtran is also the same as the voltage value of the cutoff voltage Voff or the average of the turn-on voltage Von and the cutoff voltage Voff.

Finally, please refer to FIG. 4, the cutoff voltage Voff of the first cutoff voltage curve 71 is: -1 (volts), and the cutoff voltage Voff of the second cutoff voltage curve 72 is: -2 (volts). The cutoff voltage Voff of the third cutoff voltage curve 73 is: -3 (volts). Compared with the reference curve 70, the threshold voltage caused by the third cutoff voltage curve 73 is significantly higher than the curves of the other two, representing the phase. The turn-on voltage Von and the turn-off voltage Voff of the different numbers can effectively avoid the one-sided conduction problem caused by the gate 60 on one side of the column 30 being the turn-on voltage Von, and the turn-off voltage Voff and the turn-on voltage The larger the voltage difference of Von is, the larger the threshold voltage value is, which means that the conduction state of the columnar body 30 is relatively opposite to the off state, and can meet the actual use requirements. The x-axis coordinates of "Fig. 4" are respectively marked with 0, δ, 2δ, 3δ, 4δ (volts), which are respectively a multiple increase, thereby taking the numerical value of the axis coordinate.

In summary, since the source and the drain of the two ends of the column 30 are electrically connected or controlled by the two gates 60 on both sides of the column 30, the plurality of the recesses are controlled. The gate 60 in the 31 does not need to be cut and separated, and the etching process in the process in which the feature size is gradually reduced can be avoided, and the problem that the process of separating the gate 60 is not easy is solved. In addition, in the clear state, the gate 60 is controlled to clear the voltage Vtran, and the leakage current problem occurs when the short-circuit state transition state is the pseudo-open state, so as to improve the correctness of data reading. Furthermore, the clear voltage Vtran is controlled to be an average value of the turn-on voltage Von and the turn-off voltage Voff, and can be more fast in the transition state. Therefore, the present invention is highly progressive and conforms to the requirements of the invention patent application, and the application is filed according to law, and the praying office grants the patent as soon as possible.

The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.

10. . . Base

20. . . Bit line

30. . . Columnar body

30a. . . First column

30b. . . Second column

31. . . Locating groove

40. . . Dielectric layer

50. . . Capacitive component

60. . . Gate

60a. . . First gate

60b. . . Second gate

60c. . . Third gate

70. . . Reference curve

71. . . First cutoff voltage curve

72. . . Second cutoff voltage curve

73. . . Third cutoff voltage curve

Von. . . Turn-on voltage

Vtran. . . Clear voltage

Voff. . . Cutoff voltage

1 is a cross-sectional structural view of a preferred embodiment of the present invention.

2A to 2D are schematic views showing a manufacturing process of a preferred embodiment of the present invention.

FIG. 3A is a schematic diagram of the operation and use of a preferred embodiment of the present invention.

FIG. 3B is a schematic diagram showing the operation and use of a preferred embodiment of the present invention.

FIG. 3C is a schematic diagram 3 of operation and use according to a preferred embodiment of the present invention.

4 is a schematic diagram of quantization standard deviation according to a preferred embodiment of the present invention.

10. . . Base

20. . . Bit line

30. . . Columnar body

30a. . . First column

30b. . . Second column

31. . . Locating groove

40. . . Dielectric layer

50. . . Capacitive component

60. . . Gate

60a. . . First gate

60b. . . Second gate

60c. . . Third gate

Von. . . Turn-on voltage

Vtran. . . Clear voltage

Voff. . . Cutoff voltage

Claims (12)

A vertical double gate dynamic random access memory control method, the memory body having a bit line disposed on a surface of a substrate, and a plurality of columnar bodies disposed on the bit line and forming a plurality of receiving grooves a dielectric layer formed on the surface of the accommodating recess, and a plurality of gates disposed in the accommodating recess and spaced apart from the pillar by the dielectric layer, defining a plurality of the pillars The first columnar body and the second columnar body are controlled by:
When in a short circuit state, the gates on both sides of the first column body are defined as a first gate and a second gate, and the first gate and the second gate are controlled to be a turn-on voltage, so that the first The drains at both ends of a column are electrically connected to the source;
When in a clear state, the first gate and the second gate are controlled to clear a voltage, so that the drains of the first column are electrically non-conductive with the source, and the absolute value of the clear voltage is less than the The absolute value of the turn-on voltage;
When in a pseudo open state, the gates defining the two sides of the second column are substantially the second gate and the third gate, so that the second gate and the third gate are electrically connected to each other, and the first gate is controlled. The gate has a cut-off voltage, and a pseudo open circuit is formed between the drain and the source of the first column, and the source and the drain of the second column are electrically connected. The method for controlling a vertical double-gate dynamic random access memory according to claim 1, wherein the turn-on voltage and the cut-off voltage are a positive voltage and a negative voltage, respectively, and the first column and the first column The second columnar body is coupled to the first gate, the second gate, and the third gate to form an N-type transistor. The method for controlling a vertical double gate dynamic random access memory according to claim 2, wherein the turn-on voltage and the turn-off voltage are opposite numbers. The method for controlling a vertical double gate dynamic random access memory according to claim 2, wherein the clear voltage is an average of the turn-on voltage and the turn-off voltage. The method for controlling a vertical double gate dynamic random access memory according to claim 2, wherein the clear voltage is equal to the cutoff voltage. The method for controlling a vertical double gate dynamic random access memory according to claim 1, wherein the turn-on voltage and the cut-off voltage are respectively a negative voltage and a positive voltage, and the first column and the first column The second column body is coupled to the first gate, the second gate, and the third gate to be a P-type transistor. The method for controlling a vertical double gate dynamic random access memory according to claim 6, wherein the turn-on voltage and the turn-off voltage are opposite numbers. The method for controlling a vertical double gate dynamic random access memory according to claim 6, wherein the clear voltage is an average of the turn-on voltage and the cutoff voltage. The method for controlling a vertical double gate dynamic random access memory according to claim 6, wherein the clear voltage is equal to the cutoff voltage. The method for controlling a vertical double gate dynamic random access memory according to claim 1, wherein the method further comprises a fully open state, wherein the first gate and the second gate are substantially the cutoff voltage, and A full open path is formed between the source and the drain of the two ends of the first column. The method for controlling a vertical double gate dynamic random access memory according to claim 1, wherein the bit line is formed on the surface of the substrate by ion implantation. The method for controlling a vertical double gate dynamic random access memory according to claim 1, wherein the plurality of columns are respectively connected to a capacitor element away from one end of the substrate.