JP4429798B2 - System LSI using fin-type channel FET and manufacturing method thereof - Google Patents

Description

  The present invention relates to an improvement in a system LSI including a memory circuit composed of a DRAM using a fin-type channel FET and a logic circuit using a fin-type channel FET, and a manufacturing method thereof.

  It is not an exaggeration to say that the development of CMOS device technology that uses Si as the material that supports the electronics industry in recent years. Therefore, miniaturization is proceeding at a faster pace than ever to further improve performance. I am trying to do.

  The generation of the CMOS device represented by the technology node has started mass production of the 90 nm node, and at the research stage, the center has shifted to the 65 nm node and is further progressing to the 45 nm node.

  As the generation progresses and miniaturization progresses in this way, the gate length of the MOSFET is reduced to 25 nm (65 nm node) and 18 nm (45 nm node), which are smaller than the size representing the generation, and rapidly reaches the physical limit. Is approaching.

  The biggest challenge for miniaturization of MOSFETs is to suppress the short channel effect from the past to the present generation, and when this suppression is not sufficient, the gate voltage, which is the basic principle of MOSFETs, can be turned on and off. Since the switching operation for controlling is not performed satisfactorily, various technical developments are being carried out as a countermeasure and are being put into practical use.

  Of these various technologies, the SOI (silicon on insulator) technology has been regarded as important in recent years, and in addition, the double gate SOI technology for controlling the channel of the MOSFET with two gates.

  When the double gate MOSFET is formed with a conventional planar (planar) structure, another gate electrode, that is, a back gate electrode is formed on the lower surface side of the channel separately from the front gate electrode formed on the upper surface side of the channel. Therefore, the device manufacturing process is significantly complicated.

  A fin-type channel FET having a three-dimensional structure in which the channel layer of the MOSFET is formed in a substantially vertical and convex shape on the substrate and having a double gate is known for the double gate type MOSFET of this planar structure, and the next generation Promising as a CMOS structure, a lot of research is currently underway.

  Since this fin-type channel FET can be applied with a process that is substantially the same as that of a conventional planar type CMOS having a single gate, a double-gate type MOSFET can be easily realized. There is a possibility that it can cope with miniaturization.

  FIG. 19 is a sectional view of a principal part showing a known fin-type channel FET, and FIG. 20 is a sectional view of the principal part taken along a plane abcd shown in FIG. , See Non-Patent Document 1.)

  In the figure, 1 is a Si substrate, 2 is a buried oxide film, 3 is a source region formed in a convex semiconductor, 4 is a drain region formed in a convex semiconductor, 5 is a channel layer made of a convex semiconductor, Reference numeral 6 denotes a Si oxide film, 7 denotes a gate insulating film, and 8 denotes a gate electrode.

  In the illustrated fin type channel FET, an SOI substrate is generally used, and a channel layer 5 of a convex semiconductor standing substantially vertically on the buried oxide film 2 is provided. The channel layer 5 includes an Si oxide film 6 and a gate insulating film 7. A source region 3 and a drain region 4 are formed at both ends of the convex semiconductor that is surrounded by the gate electrode 8 and constitutes the channel layer 5, and from the source region 3 and the drain region 4, although not shown. The source electrode and the drain electrode are led out and connected to the wiring layer.

  The conditions regarding the basic configuration for operating the fin-type channel FET at high speed are the same as those of the planar MOSFET using the SOI substrate, and the thickness of the fin, which is a channel layer made of a convex semiconductor (in the cross-sectional direction) It is in the structure which can be made into a fully depleted type by selecting appropriately.

  In addition to the technology related to the fin-type channel FET described above, currently called SOC (System-on-a-Chip), devices having various functions including a memory circuit device on a chip on which a logic circuit device is formed. Various researches and developments have been made on mounted multifunctional LSIs, that is, system LSIs.

  FIG. 21 is a plan view of a principal part showing a system LSI chip. In the figure, 11 is a chip, 12 is a logic circuit, 13 is an eDRAM (embedded DRAM), 14 is an SRAM, 15 is an analog circuit, Reference numeral 16 denotes a ROM, and 17 denotes an image processing circuit.

  Embedded memory (embedded memory) built in the same chip as the logic circuit device includes static random access memory (SRAM), dynamic random access memory (DRAM), flash memory (MRAM), and memory memory (MRAM). Examples thereof include a memory such as an ovonic unified memory (OUM).

Currently, the most commonly used SRAM is usually composed of 6 transistors, so the cell area is large, and when the minimum half pitch is F, the area is about 100 F ² and it is difficult to increase the capacity. In addition, although a DRAM composed of one transistor and one capacitor capable of increasing capacity requires only about 8F ² in area, a process unique to the DRAM is required for manufacturing. There are problems such as an increase in cost due to the increase and a decrease in characteristics of the logic circuit device to be embedded. Furthermore, other memories have problems such as difficulty in terms of commonality with the process of manufacturing logic circuit devices due to the introduction of new materials.

  To solve these problems, a partially-depleted SOI transistor, that is, a one-transistor memory that stores data by accumulating charges in a floating body that is electrically insulated from the substrate by a buried oxide film of the SOI substrate. Is promising as an embedded memory because it has features such as a single memory cell, excellent process commonality with logic devices, and high capacity. (For example, see Non-Patent Document 2 and Non-Patent Document 3).

  However, a memory circuit composed of a planar type 1-transistor type memory cell is manufactured on the same chip as the system LSI using the above-described three-dimensional fin-type channel FET as a logic circuit. Difficult in terms of sex.

In order to improve process consistency and the like, it may be possible to configure the SRAM using the same fin-type channel FET that constitutes the logic circuit, but even in that case, it is difficult to increase the capacity of the SRAM. There is a problem, and there is currently no established embedded memory technology using a fin-type channel FET as a logic circuit device.
Y. -K. Choi, et al., “Sub-20 nm CMOS FinFET Technology”, Technical Digest of International Electron Devices Meeting, USA, IEEE, 2001, p. 19.1.1-19.1.4. M.M. R. Tack, et al., “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures,” IEEE Transactions on Elect. 37, No. 5, p. 1373-1382 H. -J. Wann, et al., “A Capacitorless DRAM Cell on SOI Substrate,” Technical Digest of International Electronics Meeting, USA, 1993, p, 26.4.1-19.4.4.

  The present invention provides a system LSI including a fin-type channel FET and a manufacturing method thereof, including a DRAM or a logic circuit including a fin-type channel FET, and increasing the capacity of the embedded memory in the system LSI and reducing the capacity. Trying to reduce power consumption and cost.

  In a system LSI using a fin-type channel FET and a manufacturing method thereof according to the present invention, a unit memory cell constituting at least a memory circuit in a system LSI including at least a logic circuit and a memory circuit in the same chip Or a transistor including a transistor constituting a logic circuit has a channel layer formed on a SOI substrate and made of a convex semiconductor having a film thickness and an impurity concentration that is completely depleted when an operating voltage is applied. It is a fully depleted field effect transistor having two electrically independent gate electrodes formed on both side walls of the channel layer via a gate insulating film, and the two electrically independent gates In the process of manufacturing a fully depleted field effect transistor with electrodes, a convex semiconductor The gate electrode in a state of being formed through the insulating film from the top surface of the channel layer to the both side walls is divided by chemical mechanical polishing the portions corresponding to the top surface, and the gate layers are respectively formed on the both side walls of the channel layer. It is characterized in that it includes a step of forming two electrically independent gate electrodes extending separately.

  By adopting the above-mentioned means, a logic circuit can be configured using a fin-type channel FET that operates fully depleted, and a memory circuit composed of a one-transistor type DRAM, which is impossible with the prior art, is also produced. Therefore, it is possible to easily and easily realize a system LSI composed only of a fin-type channel FET that exhibits excellent characteristics in miniaturization and high performance, and the embedded DRAM is an existing embedded SRAM or the like. In comparison, the capacity can be increased.

  In addition, the number of process steps required to realize a system LSI with such excellent features is negligible compared to the conventional system LSI, and no special process is required. It is possible to sufficiently cope with processes that have been frequently used and matured, and a system LSI can be provided at a low cost.

  FIG. 1 is an equivalent circuit diagram of a main part representing a memory circuit in a system LSI chip. In the figure, Q1, Q2, Q3 and Q4 are FETs having a double gate, and WL1 and WL2 are connected to a front gate. WL1 'and WL2' are word lines connected to the back gate, and BL1 and BL2 are bit lines, respectively.

  In the illustrated memory circuit, word lines WL1, WL1 ′, WL2, WL2 ′ and bit lines BL1, BL2 are arranged orthogonally, and FETs Q1, Q2, Q3, Q4, etc., which become DRAM cells are formed at the intersections. Yes.

  FIG. 2 is an explanatory plan view of a main part schematically showing a word line and a bit line. WL is a word line, WLC is a word line contact, BL is a bit line, BLC is a bit line contact, and FQ is a fin type channel FET. Each line ab represents a portion for defining a surface similar to the cut surface described with reference to FIG. In the following, the cut surface in FIG. 4 to be described and other cross-sectional views of the main part is a view cut along the same plane as the cut surface.

  FIG. 3 is a fragmentary cutaway view showing a fin-type channel FET in a memory circuit used in the system LSI of the present invention, and FIG. 4 is a fragmentary view along a plane abcd seen in FIG. Cross-sectional views are respectively shown, and the same symbols as those used in FIGS. 19 and 20 represent the same parts or have the same meaning.

  In the system LSI according to the present invention, the same transistors as the fin-type channel FET described with reference to FIGS. 19 and 20 may be used as the transistors constituting the logic circuit. That is, a high transistor driving capability is achieved by appropriately selecting the thickness in the cross-sectional direction of the fin, which is a channel layer made of a convex semiconductor, to be a fully depleted type.

  On the other hand, as the transistor used in the memory circuit, a fin-type channel FET having a structure shown in FIGS. 3 and 4, that is, a double-gate fin-type channel FET is used.

  This fin type channel FET differs from the fin type channel FET described with reference to FIGS. 19 and 20 in that the gate electrode 8 is electrically connected to the top surface of the convex semiconductor channel layer 5 by the Si oxide film 6. Therefore, the front gate 8A and the back gate 8B are formed so as to be independent from each other, thereby forming a double-gate fin-type channel FET.

In this case, the transistor of the logic circuit and the transistor of the memory circuit both realize a full depletion mode operation. Therefore, the film thickness W _{fin in the} convex semiconductor channel layer 5 is approximately 1/2 to 2/2 of the gate length L _g. The impurity concentration in the convex semiconductor channel layer 5 is set to a low concentration of about 1 × 10 ¹⁶ cm ⁻³ or less.

  FIGS. 5 to 14 are cross-sectional views of the main part of the system LSI in the process key points for explaining the process of manufacturing the system LSI composed of the fin-type channel FET of the logic circuit and the fin-type channel FET of the memory circuit. Hereinafter, it will be described with reference to the drawings.

Refer to FIG. 5 (1) By applying a normal technique, an SOI substrate including the Si substrate 21, the buried oxide film 22, and the SOI layer 23 is manufactured. The area indicated by the arrow L is the logic circuit production scheduled area, and the area indicated by the arrow M is the memory circuit production scheduled area.
(2) A required well (not shown) is formed by applying an ion implantation method.

(3) By applying the CVD method, a hard mask material layer 24 such as SiO ₂ or Si ₃ N ₄ is deposited so as to have a film thickness about the height of the gate electrode. The “gate electrode height” is the height (thickness) of the portion on the Si oxide film 6 in the gate electrode 8 as shown in FIG. 19 or FIG. In order to realize the fin-type FET shown in FIGS. 3 and 4 in a later process, this corresponds to a machining allowance when the gate electrode 8 is polished by a chemical mechanical polishing (CMP) method.

Refer to FIG. 7 (4) The hard mask material layer 24 in the logic circuit and the peripheral circuit portion is removed by applying the lithography technique and the dry etching method.

Refer to FIG. 8 (5) By applying the CVD method again, the same hard mask material layer 25 such as SiO ₂ or Si ₃ N ₄ as the hard mask material layer 24 formed in the step (3) is formed.

Refer to FIG. 9 (6) A resist film 26 having a fin pattern is formed on the hard mask material layer 25 by applying a resist process in lithography technology.

(7) By applying the dry etching method, the hard mask material layer 25 and the hard mask material layer 24 are etched using the resist film 26 as a mask to form the hard masks 25L and 25M for the fin patterns. .

See FIG. 11 (8) By applying the dry etching method, the SOI layer 23 is etched using the hard masks 25L and 25M as masks to form the fin-type channel layers 23L and 23M, which are convex semiconductors.
(9) The gate insulating film 27 made of a material selected from SiO ₂ , SiON, HfO _2, etc. is formed by applying a thermal oxidation method or a CVD method.

Refer to FIG. 12 (10) An appropriate technique such as a CVD method, a vacuum evaporation method, or a sputtering method is selected, and a gate material film such as polycrystalline silicon, metal, or metal silicide compound is deposited. In the case of polycrystalline silicon, impurities are introduced by applying an ion implantation method.
(11) The gate electrode 28 and the gate electrode 29 are formed by patterning the gate material film by applying a lithography technique and a dry etching method.

Referring to FIG. 13 (12) The gap between the fin-type channel layer 23L having the gate electrode 28 and the fin-type channel layer 23M having the gate electrode 29 is filled with a resist 30 for protection. In this case, the thickness (height) of the resist 30 may be such that the top surface of the gate electrode 28 formed in the fin-type channel layer 23L is exposed. This step can be omitted if the fin-type channel layers 23L and 23M are not damaged by polishing by the CMP method to be performed next.

See FIG. 14 (13) The entire surface is polished by applying the CMP method. At this time, as is apparent from the above, since the hard mask material layer 24, the hard mask material layer 25, and the gate electrode 29 are present on the top surface of the fin type channel layer 23M, the fin type channel layer Compared with the hard mask material layer 25 and the gate electrode 28 formed on the top surface of 23L, the height is increased by the amount of the hard mask material layer 24. When the polishing is performed, only the fin-type channel layer 23M side is present. After being polished, the gate electrode 29 is divided on the hard mask material layer 25 to become a front gate electrode 29A and a back gate electrode 29B.
(14) Thereafter, although not shown in the drawing, the process is completed through steps such as diffusion of the source and drain, formation of an interlayer insulating film, and wiring formation.

  An operation example of the memory cell composed of the fin-type channel FET completed as described above will be described. In order to confirm the operation of the memory cell, analysis was performed by applying a three-dimensional device simulation method.

  A fin-type channel FET memory cell, which is a fully depleted type, basically has a thin body (channel) layer and is a device in which the body is completely depleted during operation. Therefore, carriers are accumulated in the body as it is. It is not possible.

  Therefore, in the fin-type channel FET memory cell according to the present invention, the gate electrode is divided into both sides of the fin-type channel and electrically separated to form the front gate electrode 29A and the back gate electrode 29B. It was set as the structure which can apply a voltage to.

FIG. 15 is a perspective view of the main part showing the structure of the memory cell used in the simulation, and FIG. 16 is a cross-sectional view of the main part of the memory cell. The same symbols as those used in FIGS. Or have the same meaning. In the figure, 31 indicates a source region and 32 indicates a drain region. Table 1 shows the dimensions and conditions of the main part of the memory cell.

  When a negative bias voltage is applied to the back gate electrode 29B of the memory cell shown in FIGS. 15 and 16, even if the body, that is, the channel layer 23M is completely depleted, the gate insulating film 27 corresponding to the back gate electrode 29B is used. Carriers (holes) can be accumulated on the channel layer 23M side at the interface between the channel layer 23M and the channel layer 23M.

Table 2 shows the conditions for writing “0” data and “1” data in the memory cells shown in FIGS. 15 and 16, and FIG. 17 sets the memory cells as the write conditions in Table 2. FIG. 6 is a diagram showing the transition of the body potential (vertical axis) with respect to time (horizontal axis) measured at the interface center (see * mark) of the channel layer 23M in the case of

  For writing “1” data, a positive bias voltage is applied to the front gate electrode 29A and the drain region 32, and an impact ionization phenomenon that occurs in the vicinity of the drain region 32 is used to negatively bias the generated holes. Accumulation at the interface corresponding to the electrode 29B.

  In writing “0” data, the bias voltage in the drain region 32 is lowered, and the bias voltage of the back gate electrode 29B is set to 0 V, so that holes accumulated at the interface corresponding to the back gate electrode 29B are sourced. It may be swept through the junction.

  As can be seen from the data shown in FIG. 17, the body potential after writing “1” data is higher than the body potential after writing “0” data. It depends on the holes accumulated at the interface corresponding to 29B. However, the body potential after writing “1” data decreases with time as the accumulated holes recombine and disappear.

  Such a change in body potential changes the threshold voltage of the FET constituting the memory cell, so that data can be read by sensing the drain current in the linear region.

  FIG. 18 is a diagram showing the result of simulating the time change of the drain current when data is written to the memory cell and then read. The bias conditions at the time of reading are as shown in Table 2.

  The read current of “0” data and “1” data varies greatly depending on the difference in threshold voltage in the memory cell, and the current can be easily detected by comparing the current with the current value of the reference cell. Identification is possible.

In the simulation described above, the hole current due to the impact ionization generated in the vicinity of the drain is used to write the “1” data, but a gate induced drain current (GIDL) can also be used. Table 3 shows an example of write conditions for “1” data in this case.

  In the first embodiment described above, a system LSI is configured using a normal fin-type channel FET as a logic circuit transistor and a double-gate fin-type channel FET as a memory circuit transistor.

However, the double-gate fin-type channel FET used as the memory circuit transistor has a channel width, that is, a layer thickness W _{fin in} the channel layer 5 (see FIG. 4) of the convex semiconductor is 1 of the gate length L _g . Since the channel impurity concentration is as low as about ˜1 × 10 ¹⁶ cm ⁻³ or less, it is possible to operate in the fully depleted mode. Therefore, in the second embodiment, the system LSI is configured by using the double gate fin-type channel FET used as the memory circuit transistor in the first embodiment also as the logic circuit transistor.

  Thus, when the same double gate fin-type channel FET is used for both the logic circuit and the memory circuit, it is clear that the manufacturing process of the system LSI is remarkably simplified, and as a result, the manufacturing cost is reduced.

It is a principal part equalization circuit diagram showing the memory circuit in a system LSI chip. It is a principal part plane explanatory view showing a word line and a bit line typically. It is a principal part cutting slope figure showing the fin type channel FET in the memory circuit used with the system LSI of this invention. FIG. 4 is a cross-sectional view of an essential part taken along a plane abcd seen in FIG. 3. It is a principal part cross-sectional view of the system LSI in the process important point for demonstrating the process of producing the system LSI of this invention. It is a principal part cross-sectional view of the system LSI in the process important point for demonstrating the process of producing the system LSI of this invention. It is a principal part cross-sectional view of the system LSI in the process important point for demonstrating the process of producing the system LSI of this invention. It is a principal part cross-sectional view of the system LSI in the process important point for demonstrating the process of producing the system LSI of this invention. It is a principal part cross-sectional view of the system LSI in the process important point for demonstrating the process of producing the system LSI of this invention. It is a principal part cross-sectional view of the system LSI in the process important point for demonstrating the process of producing the system LSI of this invention. It is a principal part cross-sectional view of the system LSI in the process important point for demonstrating the process of producing the system LSI of this invention. It is a principal part cross-sectional view of the system LSI in the process important point for demonstrating the process of producing the system LSI of this invention. It is a principal part cross-sectional view of the system LSI in the process important point for demonstrating the process of producing the system LSI of this invention. It is a principal part cross-sectional view of the system LSI in the process important point for demonstrating the process of producing the system LSI of this invention. It is a principal part slope view showing the structure of the memory cell used for simulation. FIG. 16 is a transverse cross-sectional view of a main part of the memory cell shown in FIG. 15. It is a diagram showing transition with respect to time (horizontal axis) of body potential (vertical axis). It is a diagram showing the result of having simulated the time change of the drain current at the time of reading data. It is a principal part cutting slope figure showing a well-known fin type channel FET. FIG. 20 is a cross-sectional view of a principal part showing a fin-type channel FET cut along a plane abcd seen in FIG. 19. It is principal part top explanatory drawing showing a system LSI chip.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Si substrate 2 Embedded oxide film 3 Source area | region formed in convex semiconductor (in this case Si) 4 Drain area | region formed in convex semiconductor 5 Channel layer which is a part of convex semiconductor 6 Si oxide film 7 Gate Insulating film 8 Gate electrode 8A Front gate electrode 8B Back gate electrode

Claims (5)

In a system LSI including at least a logic circuit and a memory circuit in the same chip,
Each transistor that makes up the logic circuit
A channel layer made of a convex semiconductor having a layer thickness and an impurity concentration which is formed on an SOI substrate and is completely depleted when an operating voltage is applied is surrounded by a gate electrode formed through a gate insulating film. Fully depleted field effect transistor,
The transistor of the unit memory cell constituting the memory circuit is
Two electric layers formed on an SOI substrate and having a channel layer made of a convex semiconductor having a layer thickness and an impurity concentration that are completely depleted when an operating voltage is applied, and are formed on both side walls of the channel layer via a gate insulating film A system LSI, characterized in that it is a single fully depleted field effect transistor having an independent gate electrode. Each transistor that makes up the logic circuit
Two electric layers formed on an SOI substrate and having a channel layer made of a convex semiconductor having a film thickness and an impurity concentration that are completely depleted when an operating voltage is applied, and are formed on both side walls of the channel layer via a gate insulating film 2. The system LSI according to claim 1, wherein the system LSI is replaced with one fully depleted field effect transistor having an independent gate electrode. The transistor of the unit memory cell constituting the memory circuit is
Two electrically independent gate electrodes form a front gate electrode and a back gate electrode, and carriers generated by impact ionization in the vicinity of the drain of the front gate electrode are applied with a bias voltage having a polarity opposite to that of the carrier. 2. The memory operation is performed by accumulating at an interface between a gate insulating film in contact with an electrode and a channel layer made of a convex semiconductor to change a threshold voltage in a transistor of a unit memory cell. Alternatively, the system LSI according to claim 2. The transistor of the unit memory cell constituting the memory circuit is
Two electrically independent gate electrodes form a front gate electrode and a back gate electrode, and carriers generated by an interband tunnel current, which is a gate-induced drain current in the vicinity of the drain of the front gate electrode, are opposite in polarity to the carriers. The memory operation is performed by changing the threshold voltage in the transistor of the unit memory cell by accumulating at the interface between the gate insulating film in contact with the back gate electrode to which the bias voltage is applied and the channel layer made of the convex semiconductor. 3. The system LSI according to claim 1, wherein the system LSI is characterized by the above. Two electrically independent layers each having a channel layer made of a convex semiconductor that is a component of the system LSI according to claim 1 or 2 and formed on both side walls of the channel layer via a gate insulating film In manufacturing a fully depleted field effect transistor having a gate electrode,
A portion corresponding to the top surface of the channel layer of the gate electrode in a state of being formed via an insulating film from the top surface of the channel layer made of a convex semiconductor to both side walls is divided by chemical mechanical polishing to divide the channel layer. A method of manufacturing a system LSI, comprising a step of forming two electrically independent gate electrodes extending separately on both side walls.

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