KR20080064001A - Capacitorless dram and method for manufacturing the same - Google Patents

Abstract

A capacitor-less DRAM and a method for manufacturing the same are provided to suppress disturbance by using a metal shielding effect. A capacitor-less DRAM includes a substrate(11), a first pin(13), a second pin(14), a first gate(15), and a second gate(17). The first pin and the second pin are protruded from the substrate to be spaced apart from each other. At least a part of the first gate is positioned between the first pin and the second pin. The second gate surrounds the first pin, the second pin, and the first gate to form a gate structure intersecting the first gate. Insulation material fills among the first pin, the second pin, the first gate, and the second gate.

Description

Capacitorless DRAM and method for manufacturing the same

1A and 1B are cross-sectional views illustrating the operation of a 1T DRAM without a capacitor.

2 is a perspective view of a capacitorless DRAM cell according to an embodiment of the present invention. 3 is a cross-sectional view taken along the line III-III of FIG. 2.

4 is a plan view of FIG. 2.

5 is a graph showing the I-V characteristics of the DRAM according to the present invention.

6 is a perspective view illustrating a capacitorless DRAM cell according to another embodiment of the present invention.

FIG. 7 is a VII-VII perspective view of FIG. 6. FIG.

8 is a cross-sectional view illustrating a capacitorless DRAM cell according to another embodiment of the present invention.

9A to 9N schematically illustrate a DRAM manufacturing process according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

11 substrate 12 insulation layer

13,14 ... First and second fins 15,17 ... First and second gates

The present invention relates to a semiconductor memory device, and more particularly, to a DRAM without a capacitor and a method of manufacturing the same.

A typical DRAM has one transistor / 1 capacitor (1T / 1C) cell. However, the 1T / 1C DRAM has a high density of chips and a complicated process of forming a capacitor in forming an embedded chip together with other devices.

The cell area of the 1T / 1C DRAM is generally 8F ² , and up to 6F ² or 4F ² has recently been proposed.

However, with a 1T / 1C cell structure, it is very difficult to reduce the area to 4F ² . It is also difficult to scale down a transistor, but it is more difficult in a structure having a capacitor.

In view of this scale-down problem, a capacitorless 1T DRAM has been proposed that can store data without forming capacitors that cause complex processes, the mainstream of which is that the channel body of the substrate is electrically floating. Capacitor-less 1T DRAM.

1A and 1B are cross-sectional views illustrating the operation of a 1T DRAM without a capacitor. Referring to FIG. 1A, excess holes 1 are generated in the floating channel body 13 between the source S and the drain D by impact ionization or the like. A buried oxide layer (10) is formed under the channel body (13) so that the excess holes generated are trapped in the channel body (13) because there is no place to escape. The state in which the excess hole 1 is trapped in the channel body 13 is '1' state. Referring to FIG. 1B, a state in which the excess hole 1 of the channel body 13 is flowed out by applying a forward bias between the channel body 13 and the drain D is '0' state.

In a 1T DRAM without a capacitor, a difference occurs in a current level due to a threshold voltage changed by holes accumulated in the channel body 10 according to a storage state, that is, a '1' state or a '0' state. A read operation is performed.

However, the 1T DRAM having the planar cell shown in FIGS. 1A and 1B requires excessive body doping to secure the channel body 13 area when scaled down, which is a junction junction. This leads to an increase in leakage, which adversely affects the refresh characteristics.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and can overcome the problems of 1T DRAM in a planar cell structure and provide a capacitorless DRAM capable of scaling down to an area of 4F ² or less. There is this.

A capacitorless DRAM according to the present invention for achieving the above object is a substrate;

First and second pins protruding from the substrate and spaced apart from each other; A first gate formed such that at least a portion is located between the first and second pins; And a second gate formed to surround the first and second fins in a direction crossing the first gate to form a gate structure that intersects the first gate. Between the first gate and the second gate is characterized in that it is filled with an insulating material by vapor deposition.

At least a portion of the first gate is preferably formed between the first and second fins and over an upper region of the first and second fins so that its cross section forms a T-shaped structure.

Preferably, the first and second pins and the first gate have a portion protruding from the second gate.

In this case, a portion of the first gate that is intersected by at least the second gate is formed between the first and second fins and an upper region of the first and second fins so that the cross section forms a T-shaped structure. Can be.

Alternatively, at least a part of the portion protruding with respect to the second gate of the first gate may be formed only between the first and second pins.

The first and second pins may be made of silicon.

The first and second gates may be made of any one of a metal material and polysilicon.

And an insulating layer formed on the semiconductor substrate, wherein the first and second pins may protrude from the insulating layer.

According to another feature, the first and second pins are formed to protrude with respect to the substrate by etching the substrate to a partial depth, the portion of the first and second pins close to the surface of the substrate and the substrate A region for electrical insulation is formed, and an insulating layer is disposed between the first and second gates and the substrate.

Here, the insulating material and the insulating layer may be made of the same material, for example, SiO ₂ .

The first gate may be a back gate and the second gate may be a front gate.

According to an aspect of the present invention, there is provided a method of manufacturing a capacitorless DRAM according to the present invention, which comprises: (a) contacting first and second pins spaced apart from each other on a semiconductor substrate and outer surfaces of the first and second pins; And forming a first structure including a first insulating material region protruding from the second fin to form a step with the first and second fins. (B) depositing an insulating material on the upper and opposite surfaces of the first and second fins, and depositing a first gate material in the space between the first and second fins and in an upper region of the first and second fins. Depositing to form a first gate whose cross section is a T-shaped structure; (C) removing the first insulating material region to expose outer surfaces of the first and second pins; (D) depositing an insulating material on the first and second fins and the first gate, and depositing a second gate material to intersect the first and second fins and the first gate. And forming a second gate crossing the first gate so as to surround the second fin and the upper portion of the first gate and the sides of the first and second fins with an insulating material. do.

And forming a structure in which the first and second pins and a portion of the first gate protrude from the second gate.

The method may further include removing an upper portion of the first gate forming a “T” shape from at least a portion of the portion protruding from the second gate.

The forming of the first structure may include preparing a stacked structure of a semiconductor substrate, an insulating layer on the substrate, and a first material layer forming first and second pins on the insulating layer; Forming a second material layer on the first material layer, and forming a hard mask film thereon; The first material layer, the second material layer, and the hard mask protruding from the insulating layer by removing portions of the hard mask layer, the second material layer, and the first material layer outside the range where the first and second fins are formed. Forming a membrane structure; Depositing an insulating material constituting the first insulating material region on the protruding structure; Polishing the top surface of the hard mask layer to be exposed; A portion of the insulating material forming the hard mask layer and the first insulating material region adjacent thereto is removed, and the second material layer is etched to expose the first material layer, thereby forming a stepped first insulating material region. Making a step; Depositing a spacer on the first material layer and the stepped first insulating material region, and etching the spacer to leave the spacer material only in the stepped portion; Etching the first material layer using the spacer material remaining in the stepped portion as a mask to form first and second fins spaced apart from each other; And removing the spacer material of the stepped portion.

According to another feature, the forming of the first structure may include a protruding range including a position where the first and second pins of the semiconductor substrate are to be formed, and a first material layer formed on the protruding portion of the semiconductor substrate. And forming a protruding structure comprising a hard mask film; Depositing an insulating material constituting the first insulating material region on the protruding structure; Polishing the top surface of the hard mask layer to be exposed; A portion of the insulating material forming the hard mask layer and the first insulating material region adjacent thereto is removed, and the first material layer is etched to expose the protruding portion of the semiconductor substrate, and the stepped first insulating material region is removed. Forming; Depositing a spacer on the protruding portion of the semiconductor substrate and the stepped first insulating material region, and etching the spacer to leave the spacer material only in the stepped portion; Etching the protrusions of the semiconductor substrate using the spacer material left in the stepped portions as a mask to form first and second fins spaced apart from each other; Removing the spacer material of the stepped portion.

In this case, the method may further include electrically insulating the first and second pins from the semiconductor substrate.

Hereinafter, a preferred embodiment of a capacitorless DRAM and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the thicknesses and sizes of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

In a capacitorless 1T DRAM that stores charge in a channel body of a semiconductor substrate, when the charge stored in the channel body leaks or flows into the channel body, the data retention time is shortened. Therefore, in order to increase the holding time, the volume of the channel body storing the charge is increased, or the cross-sectional area of the contact portion between the source and the drain and the channel body, which is a leakage path from which the charge escapes from the channel body, is reduced. Consider back gate biasing on the channel body to hold more charge.

The present invention relates to a capacitorless DRAM intended to apply a back gate bias. According to the present invention, the back gate bias is applied to the channel region to increase the retention time of the hole, and has a vertical channel to have a channel body volume larger than that of a typical 1T DRAM cell, so it is refreshed even when scaled down. It is advantageous for the property.

2 is a perspective view of a capacitorless DRAM cell 10 according to an embodiment of the present invention, FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2, and FIG. 4 is a plan view of FIG. 2. 2 to 4 show a cell structure of a DRAM according to the present invention, which may be configured as a two-dimensional array of such cells.

Referring to the drawings, the DRAM cell 10 is formed to protrude in a vertical direction with respect to the substrate 11, for example, a semiconductor substrate such as silicon, and includes first and second fins 13 and 14 spaced apart from each other. . The first gate 15 is formed between the first and second fins 13 and 14 in parallel with the first and second fins 13 and 14. In the direction crossing the first and second fins 13 and 14 and the first gate 15, the upper side and the first of the first and second fins 13 and 14 and the first gate 15 are located. And a second gate 17 is formed to surround the side portion used as the channel region of the second fin 13 and 14. The insulating material 19 is filled between the first and second fins 14, the first gate 15, and the second gate 17 by various deposition processes.

An insulating layer 12, for example, an SiO ₂ layer may be provided between the semiconductor substrate 11 and the structure of the DRAM cell 10. The first and second pins 13 and 14 may be made of silicon (Si). The semiconductor substrate 11, the insulating layer 12, and the first and second fins 13 and 14 may be formed using a silicon on insulator (SOI) substrate.

That is, when the first and second fins 13 and 14 are formed on the SOI substrate by a lithography process or the like, the semiconductor substrate 11, the insulating layer 12, and the first and second fins protruding in the vertical direction thereon. The structure which has (13) (14) can be formed.

The first gate 15 is used as a back gate and the second gate 17 is used as a front gate. The first and second gates 15 and 17 may be made of any one of a metal material and polysilicon.

The first gate 15 is formed such that at least a portion thereof is positioned between the first and second pins 13 and 14. For example, at least a portion of the first gate 15 is formed between the first and second fins 13 and 14 and over an upper region of the first and second fins 13 and 14. It is preferable that the cross section is configured to form a T-shaped structure.

In addition, when the first and second pins 13 and 14 and the first gate 15 have a portion 16 protruding from the second gate 17 as described below, the first gate 15 ) At least a portion intersected by the second gate 17 is located between the first and second fins 13 and 14 and in an upper region of the first and second fins 13 and 14. It is preferable that it is formed over and its cross section forms a T-shaped structure.

As a more specific example, as shown in FIGS. 2 and 3, the first gate 15 is disposed between the first and second pins 13 and 14 and between the first and second pins 13 and 14. It may be formed over the upper region so that its cross section forms a T-shaped structure. In this case, the holding of the hole may be made larger at the portion bent in the T-shape of the first gate 15, so that the hole may be held more efficiently in the edge area.

In the present embodiment, the first gate 15 has a T-shaped cross section of the protruding portion 16 as well.

The second gate 17 forms a gate structure that intersects the first gate 15. To this end, the second gate 17 is the channel of the first and second pins 13 and 14 and the first gate 15 and the first and second pins 13 and 14. The side used as the region is formed to surround the insulating material 19 as a medium.

As shown in FIGS. 2 and 4, the second gate 17 is formed to surround only a portion of the first and second fins 13 and 14 and the first gate 15. As a result, the DRAM cell 10 has a portion 16 in which the first and second pins 13 and 14 and the first gate 15 protrude from the second gate 17. At least a portion of the first and second fins 13 and 14 of the protruding portion 16 may be formed as a doped region and used as a source and a drain.

Between the first and second fins 13 and 14, the first gate 15, and the second gate 17, the insulating material 19 filled by various deposition processes is substantially the insulating layer. 12 and preferably in the same material, for example, SiO _2.

In the DRAM cell 10 according to the present invention having the above-described structure, each of the regions A1 and A2 facing the second gate 17 of each of the first and second pins 13 and 14 is channeled. Area B1 (B2) close to the first gate 15 of the first and second fins is used as the channel body.

Accordingly, the DRAM according to the present invention has a surface perpendicular to the first and second gates 15 and 17, that is, the substrate 11 having a double gate structure in which the back gate and the front gate vertically cross each other. It becomes a vertical capacitorless DRAM in which a channel is formed.

In addition, in the DRAM according to the present invention, substantially two channels may be formed per DRAM cell 10, and thus, the integration degree may be significantly increased, for example, a capacitorless having a cell area of 2F ² per bit. DRAM can be realized.

That is, a cell area of a DRAM having a 1T / 1C cell structure is generally 8F ² , and recently, up to 6F ² or 4F ^{2 has} also been proposed. However, with a 1T / 1C cell structure, it is very difficult to reduce the area to 4F ² . On the other hand, it is known that a capacitorless DRAM having a 1T cell structure can be formed to have a cell area of 4F ² .

Therefore, when the DRAM according to the present invention is formed such that its cell area is 4F ² , since substantially two channels are formed per single cell structure of the DRAM according to the present invention, the cell area per bit becomes 2F ² , and in general, It is possible to substantially increase the integration to at least twice or more compared to capacitorless DRAMs with known 1T cell structures.

In addition, the DRAM according to the present invention has the advantage that interference is suppressed by metal shielding effect due to the double gate, so that adjacent cells are close to each other and there is no mutual interference. This advantage is obtained because a constant voltage is applied to the first gate 15, that is, the back gate.

In addition, although the conventional planar structure reduces the storage space by the inverse of the square according to the decrease in the channel length (channel length), in the present invention, because the channel region is formed vertically, it is possible to maintain the channel width (channel width), A sense margin can be secured.

5 is a graph showing the I-V characteristics of the DRAM according to the present invention. 5, the thickness and height of the first and second pins 13 and 14 are 11 nm and 50 nm, respectively, for the sample having the DRAM cell 10 structure according to the exemplary embodiment of the present invention shown in FIG. 2. Shows a simulation result for the sample when the gate length is formed to be 63 nm. In FIG. 5, the horizontal axis represents the front gate (second gate 17) voltage (unit: Volt), and the vertical axis represents the drain current (unit: ampere).

In FIG. 5, the "1" state graph shows the drain current change obtained by increasing the front gate voltage Vg when the DRAM sample is operated to inject holes into the channel body. The "0" state graph shows the DRAM sample. When operated to flow holes from this channel body, it shows the drain current change obtained by increasing the front gate voltage (Vg). In FIG. 5, the "1" state graph and the "0" state graph each have a drain voltage Vd of 1.5 V and − with a source voltage Vs of 0 V and a back gate voltage Vb of −0.7 V, respectively. It was obtained at 1V.

As can be seen in FIG. 5, the DRAM sample of the present invention has an IV sufficient to exhibit a "1" state in which holes are injected into the channel body to become an excess hole state and a "0" state in which holes flow from the channel body. Characteristics.

When 1 V of the front gate voltage Vg is applied while the back gate voltage Vb is set to -0.7 V, the "1" state and the "0" state become respectively at 1.5 V and -0,7 V of the drain voltage Vd. Obtained.

According to FIG. 5, in the DRAM sample of the present invention, when the front gate voltage Vg is about 0.8V, it can be seen that current sensing (ΔId) for read operation is possible. In the read operation, the drain voltage Vd may be about 0.2V.

Table 1 shows the "1" state write, "0" state write, storage state hold, front gate voltage (Vg) during read operation, and back gate for the DRAM sample exhibiting IV characteristics of FIG. The voltage Vg, the drain voltage Vd, and the source voltage Vs (unit: Volt) are summarized in a table.

 Write "1" Write "0" hold read Vg One One 0 0.8 Vb -0.7 -0.7 -0.7 -0.7 Vd 1.5 -One 0 0.2 Vs 0 0 0 0

As can be seen from the above description with reference to FIG. 5, the DRAM cell 10 according to the exemplary embodiment of the present invention having a double gate structure forms a channel region perpendicular to the substrate 11 to form a planar shape. It can overcome the problem of 1T DRAM of cell structure and can scale down to a size smaller than 4F ² .

FIG. 6 is a perspective view illustrating a capacitorless DRAM cell 30 according to another embodiment of the present invention, and FIG. 7 is a VII-VII perspective view of FIG. 6, according to an embodiment of the present invention described with reference to FIGS. 2 to 4. Compared to the DRAM cell 10 according to the present invention, only the portion intersected by the second gate 17 of the first gate 15 has a T-shaped structure, and the portion 16 protruding with respect to the second gate 17. The first gate part 15 located in the N) is characterized in that it is formed to be located only between the first and second pins 13 and 14. The DRAM cell 30 may have a structure in which a bent portion of the first gate 15 (back gate) protruding from the second gate 17 in the structure of FIG. 2 is etched.

According to the DRAM cell 30 configured as described above, the area where the source and drain regions are in contact with the back gate can be reduced. As described above, reducing the contact area with the back gate in the source and drain regions has an advantage of preventing unnecessary expansion of the hole storage region even when the back gate voltage is greatly increased.

FIG. 8 is a cross-sectional view illustrating a capacitorless DRAM cell 50 according to another embodiment of the present invention. Compared with the embodiment of FIG. 2, the insulating layer 12 is provided on the substrate 11. Instead of forming the first and second pins 13 and 14 to protrude with respect to 12, the first and second fins may be etched to a predetermined depth by etching a predetermined area of the substrate 11 to some depth. Two pins 13 and 14 may be formed. In this case, portions of the first and second pins 13 and 14 that are adjacent to the surface of the substrate 11 are hatched by dotted lines in regions 13a and 14a for FIG. 6 for electrical insulation with the substrate 11. Portion), and an insulating layer 51 may be formed on the substrate 11 on which the first and second pins 13 and 14 are formed. The insulating layer 51 provides an electrical insulation between the substrate 11 and the first and second gates 15 and 17, and at the same time forms a base layer for forming the first and second gates 15 and 17. It can play a role.

The insulating layer 510 may be made of the same material as the insulating material 19.

Hereinafter, a method of manufacturing a DRAM according to the present invention will be described, for example, in the case of the DRAM cell 10 shown in FIG. 2. According to the manufacturing method of the present invention described below it is possible to easily implement a DRAM cell having a double gate structure.

9A to 9N schematically illustrate a DRAM manufacturing process according to an embodiment of the present invention. 9A to 9N, illustration of the semiconductor substrate is omitted.

In order to manufacture the DRAM according to the present invention, first, through the process shown in Figs. 9a to 9i, the first and second pins 13 and 14 spaced apart from each other on the semiconductor substrate and the first and second A first structure made of a first insulating material region (67 in FIG. 9I) which contacts the outer surface of the fins 13 and 14 and forms a step with the first and second pins 13 and 14 (FIG. 9I). Form 60).

In order to form the first structure 60, as shown in FIG. 9A, a first material for forming the insulating layer 12 and the first and second fins 13 and 14 on the semiconductor substrate 11. A layer 62, for example, a laminated structure in which a silicon layer is sequentially formed is prepared. In order to obtain such an SOI layer structure, an SOI substrate may be used, or the first insulating layer 12 and the first material layer 62 may be sequentially stacked on the semiconductor substrate. The insulating layer 12 may be a layer made of an oxide, for example, an SiO ₂ layer.

A second material layer 63 is formed on the SOI layer structure to obtain a stepped structure between the first and second fins 13 and 14 and the first insulating material region 67, and the hard mask layer 64 is formed thereon. ) And the third material layer 65 are sequentially formed. Here, the structure without the third material layer 65 is also possible.

The second material layer 63 and the third material layer 65 may be formed of the same material as the insulating layer 12. That is, the second and third material layers 65 may be layers of oxides, for example, SiO ₂ layers. The hard mask layer 64 may be a nitride layer, for example, a Si ₃ N ₄ layer. Thus, a structure in which an oxide-nitride-oxide (ONO) layer is stacked on the SOI layer is formed.

Next, as shown in FIG. 9B, the third material layer 65, the hard mask film, the second material layer 63 and the second material layer other than the range in which the first and second fins 13 and 14 are formed by the lithography process, and A portion of the first material layer 62 is removed to form a structure I protruding from the insulating layer 12.

Then, as in FIG. 9C, an insulating material 67 ′, for example, an oxide such as SiO ₂ is deposited to wrap both sides of the protruding structure I in FIG. 9B with the insulating material 67 ′.

In this state, as shown in FIG. 9D, the hard mask film 64 is exposed by removing the third material layer 65 and the insulating material thereon by a polishing process such as chemical mechanical polishing (CMP).

Next, as shown in FIG. 9E, the hard mask layer 64 and the portion of the insulating material 67 ′ adjacent thereto are removed, and the second material layer 63 is etched to expose the first material layer 62. The first insulating material region 67 having a stepped structure is formed on the first material layer 62.

The spacer 69 is entirely deposited on the first material layer 62 and the first insulating material region 67 having the stepped structure as shown in FIG. 9F. The spacer 69 may be formed by depositing a nitride such as Si ₃ N ₄ . Next, as in FIG. 9G, the spacer 69, for example, nitride is etched so that the spacer material 69 ′ remains only in the stepped portion.

Then, the material layer 62 is etched using the spacer material 69 'left in the stepped portion as a mask to form the first and second fins 13 and 14 spaced apart from each other as shown in FIG. 9H. do.

Next, removing the spacer material 69 'of the stepped portion, the first and second fins 13 and 14 and the first and second fins 13 spaced apart from each other, as shown in FIG. 9I. A first structure 60 is obtained, which is composed of a first insulating material region 67 in contact with the outer surface of (14) and making a step with the first and second pins 13 and 14.

By separating the first material layer 62 using the spacer as described above, the first structure 60 having the first and second fins 13 and 14 spaced apart from each other is formed, and then FIGS. 9J and 9K. As in the first structure (60) is used to form a first gate 15 having a T-shaped cross section. The first gate 15 having a T-shaped cross section is implemented by a damascene pattern using the first structure 60 as a frame.

In order to form the first gate 15, first, the second and second fins 13, 14 and the first gate 15 are disposed on the upper surfaces of the first and second fins 13 and 14 and the surfaces facing each other. After thinly depositing an insulating material 71 to serve as a gate insulating film therebetween, the space between the first and second fins 13 and 14 and the first and second fins 13 as shown in FIG. 9J. The first gate material 15 ′ is deposited in the upper region of 14. The first gate material 15 ′ may be any one of metal and polysilicon.

Next, by the CMP process or the etching process, the first gate 15 having a T-shaped cross section is formed as shown in Fig. 9K.

As described above, after the T-shaped first gate 15 is formed, the first insulating material region is exposed to expose the outer surfaces of the first and second fins 13 and 14 as shown in FIG. 9L by an etching process. Remove (67).

Then, on the first and second fins 13 and 14 and the first gate 15, the gate insulating layer serves as a gate insulating film between the first and second fins 13 and 14 and the second gate 17. A thin layer of insulating material 75 is deposited, and as shown in FIG. 9M, the second gate material 17 ′ is interposed between the first and second fins 13 and 14 and the first gate 15. By depositing, the second gate 17 perpendicular to the first gate is formed. As a result, a capacitorless DRAM having a structure in which the back gate and the front gate cross each other perpendicularly is obtained.

The second gate 17 moves to the channel region of the first and second pins 13 and 14 and the first gate 15 and the first and second pins 13 and 14. The side to be wrapped is surrounded by the insulating material (75).

After the formation of the second gate 17, a portion of the first and second fins 13, 14 and part of the first gate 15 is formed in the second gate 17 by a lithography process, as shown in FIG. 9N. To form a projecting structure 16.

Thereafter, regions of the first and second fins 13 and 14 protruding from the second gate 17 are doped to form a doped region to be used as a source and a drain. The process of doping partial regions of the first and second fins 13 and 14 to form a doped region may be performed after forming the first and second fins 13 and 14 and before forming the first gate 15. (Ie, after the process of FIG. 7H or FIG. 7I).

Meanwhile, in the case of the DRAM cell 30 according to another embodiment of the present invention described with reference to FIGS. 6 and 7, after the processes of FIGS. 9A to 9N described above, the DRAM cell 30 protrudes with respect to the second gate 17. The bent portion of the first gate 15, that is, the upper portion of the T-shaped structure may be removed by etching, and a process of depositing an insulating material on the etched region may be performed.

Meanwhile, in the case of the DRAM cell 50 according to another embodiment of the present invention described with reference to FIG. 8, a substrate, for example, may be a material of the first and second pins 13 and 14 as the semiconductor substrate 11. By using a silicon substrate, the substrate 11 is etched to some depth (corresponding to the height of the first and second pins 13 and 14) to form the first and second pins 13 and 14. And first and second electrodes for electrically insulating between the formed first and second pins 13 and 14 and the substrate 11 without the insulating layer 12 in FIGS. 9A-9N. Except for doping the lower ends of the pins 13 and 14, the overall manufacturing process is similar to the method of manufacturing the DRAM cell 10 according to the embodiment of the present invention described with reference to FIGS. 9A-9N. .

In this case, the first and second fins 13 and 14 are spaced apart from each other, and the first insulating material region 67 is formed to be in contact with the outside and to form a step with the first and second fins 13 and 14. In order to form the first structure, the first material layer, the hard mask layer, and the second layer for forming the stepped structure of the first and second fins 13 and 14 and the first insulating material region 67 on the semiconductor substrate. After forming the layer structure of the material layer, the layer structure and the portion of the semiconductor substrate other than the range in which the first and second fins 13 and 14 are formed are partially formed at the depth of the semiconductor substrate (the first and second fins 13 And a portion of the semiconductor substrate (corresponding to the first material layer 62 in FIG. 9B) protruding with respect to the semiconductor substrate surface, the first material layer, the hard mask film, and A protruding structure of the second material layer can be formed. As in the above-described embodiment, a structure without the second material layer is also possible.

Alternatively, the portion of the semiconductor substrate in the range in which the first and second fins 13 and 14 are formed is etched to a certain depth, and then the first material layer, the hard mask film, and the second material on the protruding semiconductor substrate portion. The process may be performed to form a laminated structure of the material layer.

This process yields a structure without the insulating layer 12 in Fig. 9B. The manufacturing process of the DRAM cell 50 according to another embodiment of the present invention is substantially the same as the case where the first insulating layer 12 is not provided in FIGS. 9B to 9N.

However, in order to electrically insulate the first and second pins 13 and 14 from the semiconductor substrate, the lower end portion of the semiconductor substrate portion (corresponding to the first material layer 62) protruding after the process as shown in FIG. 9B. The doping process may be performed, or the process of doping the lower ends of the first and second pins 13 and 14 may be performed after the process of FIG. 9H or 9I.

According to the capacitorless DRAM according to the present invention as described above and a method of manufacturing the same, two fins are separated by using a spacer, and the two fins spaced apart from each other and protrude upwards on the outer surface thereof. A back gate having a T-shaped cross section is realized by a multi-margin pattern using a structure made of an insulating material region, and a front gate vertically intersecting with the back gate is formed in a direction crossing thereon.

The DRAM according to the present invention is a double gate capacitorless vertical 1T DRAM vertically intersecting with each other, and may form two channel regions per cell, thereby easily increasing the integration degree while implementing a double gate structure.

In the above description, specific embodiments of the capacitorless DRAM and its manufacturing method of the present invention have been described with reference to the drawings. However, the present invention is not limited thereto, and various modifications and equivalents may be made within the scope of the technical spirit described in the claims. Other embodiments are possible.

According to the present invention as described above, it is possible to overcome the problem of the 1T DRAM of the planar cell structure, and to provide a capacitorless DRAM capable of scaling down to an area of 4F ² or less.

That is, since two channels are formed per single cell structure of the DRAM according to the present invention, the degree of integration may be substantially increased to at least twice or more than that of a capacitorless DRAM having a generally known 1T cell structure.

In addition, since the DRAM according to the present invention has a double gate structure, interference is suppressed by metal shielding, and adjacent cells are close to each other, so that there is no mutual interference.

In addition, although the conventional planar structure reduces the storage space by the inverse of the square according to the decrease in the channel length (channel length), in the present invention, because the channel region is formed vertically, it is possible to maintain the channel width (channel width), A sense margin can be secured.

Claims (22)

A substrate; First and second pins protruding from the substrate and spaced apart from each other; A first gate formed such that at least a portion is located between the first and second pins; And a second gate formed to surround the first and second fins and the first gate in a direction crossing the first gate to form a gate structure intersecting the first gate. And between the first and second pins, the first gate, and the second gate are filled with an insulating material by vapor deposition. The capacitor of claim 1, wherein at least a portion of the first gate is formed between the first and second fins and over an upper region of the first and second fins so that a cross section thereof forms a T-shaped structure. Reese DRAM. The capacitorless DRAM of claim 2, wherein the first and second pins and the first gate have a protruding portion with respect to the second gate. The capacitorless DRAM of claim 1, wherein the first and second pins and the first gate have a protruding portion with respect to the second gate. 5. The cross-section of claim 4, wherein a portion of the first gate that is intersected by at least the second gate is formed between the first and second fins and over an upper region of the first and second fins. Capacitorless DRAM characterized in that to form a structure. 6. The capacitorless DRAM of claim 5, wherein at least a portion of the portion of the first gate protruding with respect to the second gate is formed only between the first and second pins. The capacitorless DRAM of claim 1, wherein the first and second pins are made of silicon. 2. The capacitorless DRAM of claim 1, wherein the first and second gates are made of any one of a metal material and polysilicon. The method of claim 1, wherein the first and second pins are made of silicon, The first and second gate capacitorless DRAM, characterized in that made of any one of a metal material and polysilicon. The semiconductor device of claim 1, further comprising an insulating layer formed on the semiconductor substrate. And the first and second pins protrude from the insulating layer. The capacitorless DRAM of claim 10, wherein the insulating material and the insulating layer are made of the same material. The capacitorless DRAM of claim 11, wherein the insulating material and the insulating layer are made of SiO ₂ . The method of claim 1, wherein the first and second pins are formed to protrude from the substrate by etching the substrate to a partial depth. A portion of the first and second pins adjacent to the surface of the substrate is formed with an area for electrical insulation with the substrate, And a dielectric layer disposed between the first and second gates and the substrate. The capacitorless DRAM of claim 13, wherein the insulating material and the insulating layer are made of the same material. The capacitorless DRAM of claim 14, wherein the insulating material and the insulating layer are made of SiO ₂ . 10. The capacitorless DRAM of claim 1, wherein the first gate is a back gate and the second gate is a front gate. (A) contacting the first and second fins spaced apart from each other on the semiconductor substrate and the outer surfaces of the first and second fins, protruding from the first and second fins to form a step with the first and second fins; Forming a first structure comprising a formed first insulating material region; (B) depositing an insulating material on the upper and opposite surfaces of the first and second fins, and depositing a first gate material in the space between the first and second fins and in an upper region of the first and second fins. Depositing to form a first gate whose cross section is a T-shaped structure; (C) removing the first insulating material region to expose outer surfaces of the first and second pins; (D) depositing an insulating material on the first and second fins and the first gate, and depositing a second gate material to intersect the first and second fins and the first gate. And forming a second gate crossing the first gate to cover the second fin and the upper portion of the first gate and the sides of the first and second fins with an insulating material. Method for manufacturing capacitorless DRAM. 18. The method of claim 17, further comprising forming a structure in which the first and second pins and a portion of the first gate protrude from the second gate. 19. The capacitorless DRAM of claim 18, further comprising: removing an upper portion of the first gate forming a “T” shape from at least a portion of the portion protruding from the second gate. Manufacturing method. The method of claim 17, wherein the forming of the first structure comprises: Preparing a stacked structure of a semiconductor substrate, an insulating layer on the substrate, and a first material layer forming first and second pins on the insulating layer; Forming a second material layer on the first material layer, and forming a hard mask film thereon; The first material layer, the second material layer, and the hard mask protruding from the insulating layer by removing portions of the hard mask layer, the second material layer, and the first material layer outside the range where the first and second fins are formed. Forming a membrane structure; Depositing an insulating material constituting the first insulating material region on the protruding structure; Polishing the top surface of the hard mask layer to be exposed; A portion of the insulating material forming the hard mask layer and the first insulating material region adjacent thereto is removed, and the second material layer is etched to expose the first material layer, thereby forming a stepped first insulating material region. Making a step; Depositing a spacer on the first material layer and the stepped first insulating material region, and etching the spacer to leave the spacer material only in the stepped portion; Etching the first material layer using the spacer material remaining in the stepped portion as a mask to form first and second fins spaced apart from each other; And removing the spacer material of the stepped portion. The method of claim 17, wherein the forming of the first structure comprises: Forming a protruding structure including a first material layer and a hard mask layer on a protruding portion of the semiconductor substrate, the protruding range including a position to form the first and second pins of the semiconductor substrate; Depositing an insulating material constituting the first insulating material region on the protruding structure; Polishing the top surface of the hard mask layer to be exposed; A portion of the insulating material forming the hard mask layer and the first insulating material region adjacent thereto is removed, and the first material layer is etched to expose the protruding portion of the semiconductor substrate, and the stepped first insulating material region is removed. Forming; Depositing a spacer on the protruding portion of the semiconductor substrate and the stepped first insulating material region, and etching the spacer to leave the spacer material only in the stepped portion; Etching the protrusions of the semiconductor substrate using the spacer material left in the stepped portions as a mask to form first and second fins spaced apart from each other; And removing the spacer material of the stepped portion. 22. The method of claim 21, further comprising causing the first and second pins to be electrically insulated from the semiconductor substrate.

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